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DE68922692D1 - Matrixverbindungssystem. - Google Patents

Matrixverbindungssystem.

Info

Publication number
DE68922692D1
DE68922692D1 DE68922692T DE68922692T DE68922692D1 DE 68922692 D1 DE68922692 D1 DE 68922692D1 DE 68922692 T DE68922692 T DE 68922692T DE 68922692 T DE68922692 T DE 68922692T DE 68922692 D1 DE68922692 D1 DE 68922692D1
Authority
DE
Germany
Prior art keywords
connection system
matrix connection
matrix
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68922692T
Other languages
English (en)
Other versions
DE68922692T2 (de
Inventor
Jimmie D Childers
Hugh P Mcadams
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=23011756&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE68922692(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE68922692D1 publication Critical patent/DE68922692D1/de
Publication of DE68922692T2 publication Critical patent/DE68922692T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
DE68922692T 1988-11-01 1989-10-27 Matrixverbindungssystem. Expired - Fee Related DE68922692T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07265750 US4975874B1 (en) 1988-11-01 1988-11-01 Metrix interconnection system with different width conductors

Publications (2)

Publication Number Publication Date
DE68922692D1 true DE68922692D1 (de) 1995-06-22
DE68922692T2 DE68922692T2 (de) 1995-09-14

Family

ID=23011756

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68922692T Expired - Fee Related DE68922692T2 (de) 1988-11-01 1989-10-27 Matrixverbindungssystem.

Country Status (5)

Country Link
US (1) US4975874B1 (de)
EP (1) EP0367138B1 (de)
JP (1) JPH02284368A (de)
KR (1) KR0146291B1 (de)
DE (1) DE68922692T2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6512257B2 (en) 1995-11-09 2003-01-28 Hitachi, Inc. System with meshed power and signal buses on cell array
JP3869045B2 (ja) * 1995-11-09 2007-01-17 株式会社日立製作所 半導体記憶装置
US6831317B2 (en) * 1995-11-09 2004-12-14 Hitachi, Ltd. System with meshed power and signal buses on cell array
US5649126A (en) * 1995-12-04 1997-07-15 Sun Microsystems, Inc. Parallel signal bus with reduced miller effect capacitance
US5847986A (en) * 1997-12-17 1998-12-08 Siemens Aktiengesellschaft Memory array with reduced charging current

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4045783A (en) * 1976-04-12 1977-08-30 Standard Microsystems Corporation Mos one transistor cell ram having divided and balanced bit lines, coupled by regenerative flip-flop sense amplifiers, and balanced access circuitry
US4239993A (en) * 1978-09-22 1980-12-16 Texas Instruments Incorporated High performance dynamic sense amplifier with active loads
JPS60234295A (ja) * 1984-05-04 1985-11-20 Fujitsu Ltd 半導体記憶装置
JPS61199297A (ja) * 1985-02-28 1986-09-03 Toshiba Corp 半導体記憶装置
US4807191A (en) * 1988-01-04 1989-02-21 Motorola, Inc. Redundancy for a block-architecture memory

Also Published As

Publication number Publication date
US4975874B1 (en) 1997-09-23
US4975874A (en) 1990-12-04
KR0146291B1 (ko) 1998-11-02
JPH02284368A (ja) 1990-11-21
JPH057828B2 (de) 1993-01-29
EP0367138A3 (de) 1991-02-27
DE68922692T2 (de) 1995-09-14
EP0367138A2 (de) 1990-05-09
EP0367138B1 (de) 1995-05-17
KR900008519A (ko) 1990-06-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8310 Action for declaration of annulment
8313 Request for invalidation rejected/withdrawn
8339 Ceased/non-payment of the annual fee