DE60239391D1 - rgungsringes mit großem parasitärem Widerstand - Google Patents
rgungsringes mit großem parasitärem WiderstandInfo
- Publication number
- DE60239391D1 DE60239391D1 DE60239391T DE60239391T DE60239391D1 DE 60239391 D1 DE60239391 D1 DE 60239391D1 DE 60239391 T DE60239391 T DE 60239391T DE 60239391 T DE60239391 T DE 60239391T DE 60239391 D1 DE60239391 D1 DE 60239391D1
- Authority
- DE
- Germany
- Prior art keywords
- ring
- parasitic resistance
- large parasitic
- resistance
- parasitic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000003071 parasitic effect Effects 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP02425376A EP1369922B1 (de) | 2002-06-07 | 2002-06-07 | Mehrschichtige Metallstruktur eines Spannungsversorgungsringes mit großem parasitärem Widerstand |
Publications (1)
Publication Number | Publication Date |
---|---|
DE60239391D1 true DE60239391D1 (de) | 2011-04-21 |
Family
ID=29433252
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60239391T Expired - Lifetime DE60239391D1 (de) | 2002-06-07 | 2002-06-07 | rgungsringes mit großem parasitärem Widerstand |
Country Status (3)
Country | Link |
---|---|
US (1) | US7196363B2 (de) |
EP (1) | EP1369922B1 (de) |
DE (1) | DE60239391D1 (de) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2870042B1 (fr) * | 2004-05-07 | 2006-09-29 | St Microelectronics Sa | Structure capacitive de circuit integre |
US7939856B2 (en) * | 2004-12-31 | 2011-05-10 | Stmicroelectronics Pvt. Ltd. | Area-efficient distributed device structure for integrated voltage regulators |
JP2007173760A (ja) * | 2005-11-25 | 2007-07-05 | Matsushita Electric Ind Co Ltd | 半導体集積回路及びその設計方法 |
JP4997786B2 (ja) * | 2006-02-17 | 2012-08-08 | 富士通セミコンダクター株式会社 | 半導体集積回路装置 |
US7750375B2 (en) | 2006-09-30 | 2010-07-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Power line layout techniques for integrated circuits having modular cells |
DE102006049740A1 (de) * | 2006-10-21 | 2008-04-24 | Atmel Germany Gmbh | Halbleiterbauelement |
US8549447B2 (en) | 2010-04-24 | 2013-10-01 | Robert Eisenstadt | Integrated circuits with multiple I/O regions |
TW201140786A (en) * | 2010-05-14 | 2011-11-16 | Realtek Semiconductor Corp | Layout structure and version control circuit for integrated circuit |
US9478505B2 (en) | 2012-04-12 | 2016-10-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Guard ring design structure for semiconductor devices |
JP6342165B2 (ja) * | 2014-01-24 | 2018-06-13 | ルネサスエレクトロニクス株式会社 | 半導体装置及びioセル |
US10540471B2 (en) | 2016-05-11 | 2020-01-21 | Samsung Electronics Co., Ltd. | Layout design system and semiconductor device fabricated using the same |
Family Cites Families (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6344742A (ja) * | 1986-08-12 | 1988-02-25 | Fujitsu Ltd | 半導体装置 |
JP2606845B2 (ja) * | 1987-06-19 | 1997-05-07 | 富士通株式会社 | 半導体集積回路 |
JPH025550A (ja) * | 1988-06-24 | 1990-01-10 | Kawasaki Steel Corp | 半導体装置 |
JPH04116850A (ja) | 1990-09-06 | 1992-04-17 | Seiko Epson Corp | 半導体装置 |
JP3185271B2 (ja) * | 1991-09-13 | 2001-07-09 | 日本電気株式会社 | 半導体集積回路 |
JP2919241B2 (ja) * | 1993-09-13 | 1999-07-12 | 日本電気株式会社 | 電源配線 |
US5583359A (en) * | 1995-03-03 | 1996-12-10 | Northern Telecom Limited | Capacitor structure for an integrated circuit |
US5765279A (en) * | 1995-05-22 | 1998-06-16 | Fujitsu Limited | Methods of manufacturing power supply distribution structures for multichip modules |
JP3432963B2 (ja) * | 1995-06-15 | 2003-08-04 | 沖電気工業株式会社 | 半導体集積回路 |
US5774326A (en) * | 1995-08-25 | 1998-06-30 | General Electric Company | Multilayer capacitors using amorphous hydrogenated carbon |
US5864177A (en) * | 1996-12-12 | 1999-01-26 | Honeywell Inc. | Bypass capacitors for chip and wire circuit assembly |
DE19736197C1 (de) * | 1997-08-20 | 1999-03-04 | Siemens Ag | Integrierte Schaltung mit Kondensatoren |
US6034864A (en) * | 1997-11-14 | 2000-03-07 | Murata Manufacturing Co., Ltd. | Multilayer capacitor |
US6285050B1 (en) * | 1997-12-24 | 2001-09-04 | International Business Machines Corporation | Decoupling capacitor structure distributed above an integrated circuit and method for making same |
US6066537A (en) * | 1998-02-02 | 2000-05-23 | Tritech Microelectronics, Ltd. | Method for fabricating a shielded multilevel integrated circuit capacitor |
US6252177B1 (en) * | 1998-02-18 | 2001-06-26 | Compaq Computer Corporation | Low inductance capacitor mounting structure for capacitors of a printed circuit board |
US6016000A (en) * | 1998-04-22 | 2000-01-18 | Cvc, Inc. | Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics |
US6146939A (en) * | 1998-09-18 | 2000-11-14 | Tritech Microelectronics, Ltd. | Metal-polycrystalline silicon-N-well multiple layered capacitor |
JP3522144B2 (ja) * | 1999-02-25 | 2004-04-26 | 富士通株式会社 | 容量回路および半導体集積回路装置 |
US6218729B1 (en) * | 1999-03-11 | 2001-04-17 | Atmel Corporation | Apparatus and method for an integrated circuit having high Q reactive components |
US6424022B1 (en) * | 2000-03-12 | 2002-07-23 | Mobilink Telecom, Inc. | Guard mesh for noise isolation in highly integrated circuits |
JP2000349238A (ja) * | 1999-06-04 | 2000-12-15 | Seiko Epson Corp | 半導体装置 |
US6470545B1 (en) * | 1999-09-15 | 2002-10-29 | National Semiconductor Corporation | Method of making an embedded green multi-layer ceramic chip capacitor in a low-temperature co-fired ceramic (LTCC) substrate |
JP3489729B2 (ja) * | 1999-11-19 | 2004-01-26 | 株式会社村田製作所 | 積層コンデンサ、配線基板、デカップリング回路および高周波回路 |
US6300161B1 (en) * | 2000-02-15 | 2001-10-09 | Alpine Microsystems, Inc. | Module and method for interconnecting integrated circuits that facilitates high speed signal propagation with reduced noise |
JP3666371B2 (ja) * | 2000-08-08 | 2005-06-29 | 株式会社村田製作所 | 導電性ペーストおよび積層セラミック電子部品 |
US6385033B1 (en) * | 2000-09-29 | 2002-05-07 | Intel Corporation | Fingered capacitor in an integrated circuit |
JP4332634B2 (ja) * | 2000-10-06 | 2009-09-16 | Tdk株式会社 | 積層型電子部品 |
JP2002260959A (ja) * | 2001-03-01 | 2002-09-13 | Nec Corp | 積層コンデンサとその製造方法およびこのコンデンサを用いた半導体装置、電子回路基板 |
US6476497B1 (en) * | 2001-03-26 | 2002-11-05 | Lsi Logic Corporation | Concentric metal density power routing |
US6777755B2 (en) * | 2001-12-05 | 2004-08-17 | Agilent Technologies, Inc. | Method and apparatus for creating a reliable long RC time constant |
US6559544B1 (en) * | 2002-03-28 | 2003-05-06 | Alan Roth | Programmable interconnect for semiconductor devices |
-
2002
- 2002-06-07 EP EP02425376A patent/EP1369922B1/de not_active Expired - Lifetime
- 2002-06-07 DE DE60239391T patent/DE60239391D1/de not_active Expired - Lifetime
-
2003
- 2003-06-06 US US10/456,940 patent/US7196363B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP1369922B1 (de) | 2011-03-09 |
US7196363B2 (en) | 2007-03-27 |
US20040041268A1 (en) | 2004-03-04 |
EP1369922A1 (de) | 2003-12-10 |
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