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DE60139219D1 - Dynamisch konfigurierbare Debug-Schnittstelle mit gleichzeitiger Verwendung von Fehlerbeseitigung von mehreren Prozessorkernen - Google Patents

Dynamisch konfigurierbare Debug-Schnittstelle mit gleichzeitiger Verwendung von Fehlerbeseitigung von mehreren Prozessorkernen

Info

Publication number
DE60139219D1
DE60139219D1 DE60139219T DE60139219T DE60139219D1 DE 60139219 D1 DE60139219 D1 DE 60139219D1 DE 60139219 T DE60139219 T DE 60139219T DE 60139219 T DE60139219 T DE 60139219T DE 60139219 D1 DE60139219 D1 DE 60139219D1
Authority
DE
Germany
Prior art keywords
pin
data processing
integrated circuit
processing core
multiple cores
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60139219T
Other languages
English (en)
Inventor
Gary L Swoboda
Douglas E Deao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE60139219D1 publication Critical patent/DE60139219D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31705—Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/22—Means for limiting or controlling the pin/gate ratio
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G06F11/2733—Test interface between tester and unit under test
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Debugging And Monitoring (AREA)
  • Time-Division Multiplex Systems (AREA)
DE60139219T 2000-03-02 2001-03-02 Dynamisch konfigurierbare Debug-Schnittstelle mit gleichzeitiger Verwendung von Fehlerbeseitigung von mehreren Prozessorkernen Expired - Lifetime DE60139219D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US21934000P 2000-03-02 2000-03-02
US18632600P 2000-03-02 2000-03-02
US51509300A 2000-03-02 2000-03-02

Publications (1)

Publication Number Publication Date
DE60139219D1 true DE60139219D1 (de) 2009-08-27

Family

ID=27392080

Family Applications (2)

Application Number Title Priority Date Filing Date
DE60139219T Expired - Lifetime DE60139219D1 (de) 2000-03-02 2001-03-02 Dynamisch konfigurierbare Debug-Schnittstelle mit gleichzeitiger Verwendung von Fehlerbeseitigung von mehreren Prozessorkernen
DE60118089T Expired - Lifetime DE60118089T2 (de) 2000-03-02 2001-03-02 Abtastschnittstelle mit Zeitmultiplexmerkmal zur Signalüberlagerung

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE60118089T Expired - Lifetime DE60118089T2 (de) 2000-03-02 2001-03-02 Abtastschnittstelle mit Zeitmultiplexmerkmal zur Signalüberlagerung

Country Status (2)

Country Link
EP (4) EP1139220B1 (de)
DE (2) DE60139219D1 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7702964B2 (en) * 2004-05-11 2010-04-20 Qualcomm Incorporated Compression of data traces for an integrated circuit with multiple memories
EP1720100B1 (de) * 2005-05-02 2007-07-18 Accemic GmbH & Co. KG Verfahren und Vorrichtung zur Emulation einer programmierbaren Einheit
DE102007017865A1 (de) 2007-04-13 2008-11-13 Dspace Digital Signal Processing And Control Engineering Gmbh Adaptions-Element und Testanordnung sowie Verfahren zum Betrieb derselben
CN103136138B (zh) * 2011-11-24 2015-07-01 炬力集成电路设计有限公司 一种芯片、芯片调试方法以及芯片与外部设备通信的方法
GB2501333B (en) 2012-07-09 2014-03-05 Ultrasoc Technologies Ltd Debug architecture
US9323620B2 (en) 2013-06-12 2016-04-26 International Business Machines Corporation Implementing shared adapter configuration updates concurrent with maintenance actions in a virtualized system
US9317317B2 (en) 2013-06-12 2016-04-19 International Business Machines Corporation Implementing concurrent device driver maintenance and recovery for an SRIOV adapter in a virtualized system
US9400704B2 (en) 2013-06-12 2016-07-26 Globalfoundries Inc. Implementing distributed debug data collection and analysis for a shared adapter in a virtualized system
US9304849B2 (en) 2013-06-12 2016-04-05 International Business Machines Corporation Implementing enhanced error handling of a shared adapter in a virtualized system
US9720775B2 (en) 2013-06-12 2017-08-01 International Business Machines Corporation Implementing concurrent adapter firmware update for an SRIOV adapter in a virtualized system
US9111046B2 (en) 2013-06-12 2015-08-18 International Business Machines Corporation Implementing capacity and user-based resource allocation for a shared adapter in a virtualized system
WO2016080969A1 (en) * 2014-11-18 2016-05-26 Hewlett Packard Enterprise Development Lp User interface overlay
US10073137B2 (en) 2016-08-02 2018-09-11 Qualcomm Incorporated Soundwire-based embedded debugging in an electronic device
CN111209193B (zh) * 2019-12-30 2023-09-22 北京水滴科技集团有限公司 程序的调试方法及装置
CN114062896B (zh) * 2021-11-11 2024-10-25 南京金理念信息技术有限公司 一种集成电路的成品测试方法和存储介质

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4703484A (en) * 1985-12-19 1987-10-27 Harris Corporation Programmable integrated circuit fault detection apparatus
JPH01259274A (ja) * 1988-04-08 1989-10-16 Fujitsu Ltd 集積回路の試験方式
GB2218816B (en) * 1988-05-19 1992-07-29 Plessey Co Plc Improvements in and relating to methods of testing integrated circuits
US5369645A (en) * 1991-07-02 1994-11-29 Hewlett-Packard Company Testing integrated circuit pad input and output structures
JPH06214821A (ja) * 1992-03-02 1994-08-05 Motorola Inc 逐次自己アドレス解読機能を有するデ−タ処理システムとその動作方法
US5513186A (en) * 1993-12-07 1996-04-30 Sun Microsystems, Inc. Method and apparatus for interconnect testing without speed degradation
EP0720093B1 (de) * 1994-12-28 2001-11-14 Kabushiki Kaisha Toshiba Mikroprozessor mit Fehlersuchsystem
US5615357A (en) * 1994-12-29 1997-03-25 Sun Microsystems, Inc. System and method for verifying processor performance
US5729726A (en) * 1995-10-02 1998-03-17 International Business Machines Corporation Method and system for performance monitoring efficiency of branch unit operation in a processing system
US5832490A (en) * 1996-05-31 1998-11-03 Siemens Medical Systems, Inc. Lossless data compression technique that also facilitates signal analysis
US5848264A (en) * 1996-10-25 1998-12-08 S3 Incorporated Debug and video queue for multi-processor chip
US5978902A (en) * 1997-04-08 1999-11-02 Advanced Micro Devices, Inc. Debug interface including operating system access of a serial/parallel debug port
US6154857A (en) * 1997-04-08 2000-11-28 Advanced Micro Devices, Inc. Microprocessor-based device incorporating a cache for capturing software performance profiling data
US5943490A (en) * 1997-05-30 1999-08-24 Quickturn Design Systems, Inc. Distributed logic analyzer for use in a hardware logic emulation system
GB9805479D0 (en) 1998-03-13 1998-05-13 Sgs Thomson Microelectronics Microcomputer
CN1439101A (zh) 1998-06-16 2003-08-27 因芬尼昂技术股份公司 用于测量和分析集成电路块的电信号的装置

Also Published As

Publication number Publication date
EP1130501B1 (de) 2009-07-15
DE60118089D1 (de) 2006-05-11
EP1132816B1 (de) 2019-03-13
EP1139108B1 (de) 2006-03-22
EP1130501A1 (de) 2001-09-05
EP1139220B1 (de) 2017-10-25
EP1139108A2 (de) 2001-10-04
EP1139108A3 (de) 2004-01-02
EP1139220A3 (de) 2009-10-28
EP1139220A2 (de) 2001-10-04
DE60118089T2 (de) 2006-10-05
EP1132816A3 (de) 2005-09-07
EP1132816A2 (de) 2001-09-12

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Legal Events

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8364 No opposition during term of opposition