DE60136025D1 - Datenübertragungsverbindung zwischen zwei ASICs - Google Patents
Datenübertragungsverbindung zwischen zwei ASICsInfo
- Publication number
- DE60136025D1 DE60136025D1 DE60136025T DE60136025T DE60136025D1 DE 60136025 D1 DE60136025 D1 DE 60136025D1 DE 60136025 T DE60136025 T DE 60136025T DE 60136025 T DE60136025 T DE 60136025T DE 60136025 D1 DE60136025 D1 DE 60136025D1
- Authority
- DE
- Germany
- Prior art keywords
- asics
- data transfer
- transfer connection
- connection
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4009—Coupling between buses with data restructuring
- G06F13/4018—Coupling between buses with data restructuring with data-width conversion
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Communication Control (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GBGB0006291.9A GB0006291D0 (en) | 2000-03-15 | 2000-03-15 | Data communication link |
Publications (1)
Publication Number | Publication Date |
---|---|
DE60136025D1 true DE60136025D1 (de) | 2008-11-20 |
Family
ID=9887706
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60136025T Expired - Lifetime DE60136025D1 (de) | 2000-03-15 | 2001-01-22 | Datenübertragungsverbindung zwischen zwei ASICs |
Country Status (4)
Country | Link |
---|---|
US (2) | US7031347B2 (de) |
EP (1) | EP1134668B1 (de) |
DE (1) | DE60136025D1 (de) |
GB (1) | GB0006291D0 (de) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7137048B2 (en) | 2001-02-02 | 2006-11-14 | Rambus Inc. | Method and apparatus for evaluating and optimizing a signaling system |
US7490275B2 (en) | 2001-02-02 | 2009-02-10 | Rambus Inc. | Method and apparatus for evaluating and optimizing a signaling system |
US6873939B1 (en) | 2001-02-02 | 2005-03-29 | Rambus Inc. | Method and apparatus for evaluating and calibrating a signaling system |
US7032139B1 (en) * | 2002-03-18 | 2006-04-18 | Finisar Corporation | Bit error rate tester |
US7231558B2 (en) | 2002-03-18 | 2007-06-12 | Finisar Corporation | System and method for network error rate testing |
JP4407104B2 (ja) * | 2002-08-30 | 2010-02-03 | 富士ゼロックス株式会社 | 信号伝送システム |
US7076377B2 (en) | 2003-02-11 | 2006-07-11 | Rambus Inc. | Circuit, apparatus and method for capturing a representation of a waveform from a clock-data recovery (CDR) unit |
US7627029B2 (en) | 2003-05-20 | 2009-12-01 | Rambus Inc. | Margin test methods and circuits |
US7336749B2 (en) | 2004-05-18 | 2008-02-26 | Rambus Inc. | Statistical margin test methods and circuits |
US8572289B1 (en) * | 2003-12-19 | 2013-10-29 | Nvidia Corporation | System, method and computer program product for stateless offloading of upper level network protocol operations |
TWI254210B (en) * | 2004-05-26 | 2006-05-01 | Benq Corp | Serial transmission control system for accessing data based on status signal, system capable of multiplex controlling to output at different times, and printer and control method thereof |
US7434192B2 (en) | 2004-12-13 | 2008-10-07 | Altera Corporation | Techniques for optimizing design of a hard intellectual property block for data transmission |
US7936793B2 (en) * | 2005-04-01 | 2011-05-03 | Freescale Semiconductor, Inc. | Methods and apparatus for synchronizing data transferred across a multi-pin asynchronous serial interface |
GB2442501B (en) | 2006-10-05 | 2011-04-13 | Advanced Risc Mach Ltd | Apparatus and method for data processing having an on-chip or off-chip interconnect between two or more devices |
US7953162B2 (en) * | 2006-11-17 | 2011-05-31 | Intersil Americas Inc. | Use of differential pair as single-ended data paths to transport low speed data |
JP4336860B2 (ja) * | 2007-02-21 | 2009-09-30 | 日本電気株式会社 | シリアルインタフェース回路、及びシリアル受信器 |
US20100262887A1 (en) * | 2009-04-13 | 2010-10-14 | Lockheed Martin Corporation | High Integrity Data Network System and Method |
US8627156B1 (en) * | 2010-10-26 | 2014-01-07 | Agilent Technologies, Inc. | Method and system of testing bit error rate using signal with mixture of scrambled and unscrambled bits |
US11353582B2 (en) * | 2016-09-02 | 2022-06-07 | Koninklijke Philips N.V. | Ultrasound probe with low frequency, low voltage digital microbeamformer |
US20230046788A1 (en) * | 2021-08-16 | 2023-02-16 | Capital One Services, Llc | Systems and methods for resetting an authentication counter |
US12119335B2 (en) | 2021-12-16 | 2024-10-15 | International Business Machines Corporation | Interconnection structures for high bandwidth data transfer |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3811014A (en) * | 1973-03-12 | 1974-05-14 | Logicon Inc | Adaptive pulse code modulation system |
US5175727A (en) * | 1990-04-16 | 1992-12-29 | Maher John W | Communication system network interconnecting a plurality of communication systems |
US5228056A (en) * | 1990-12-14 | 1993-07-13 | Interdigital Technology Corporation | Synchronous spread-spectrum communications system and method |
JP3158213B2 (ja) * | 1991-09-12 | 2001-04-23 | 富士通株式会社 | 並列伝送方法および装置 |
JP3192030B2 (ja) * | 1993-06-08 | 2001-07-23 | 富士通株式会社 | インターフェイス装置および通信システム |
US5522088A (en) * | 1994-06-17 | 1996-05-28 | International Business Machines Corporation | Shared channel subsystem has a self timed interface using a received clock signal to individually phase align bits received from a parallel bus |
US5570356A (en) * | 1995-06-07 | 1996-10-29 | International Business Machines Corporation | High bandwidth communications system having multiple serial links |
US5751724A (en) * | 1996-02-23 | 1998-05-12 | Dsc Communications Corporation | Demultiplexer for a multi-bitline bus |
US6072781A (en) * | 1996-10-22 | 2000-06-06 | International Business Machines Corporation | Multi-tasking adapter for parallel network applications |
US6150922A (en) * | 1997-01-23 | 2000-11-21 | Lucent Technologies Inc. | Serial communication technique |
US6202108B1 (en) * | 1997-03-13 | 2001-03-13 | Bull S.A. | Process and system for initializing a serial link between two integrated circuits comprising a parallel-serial port using two clocks with different frequencies |
US6167077A (en) * | 1997-12-23 | 2000-12-26 | Lsi Logic Corporation | Using multiple high speed serial lines to transmit high data rates while compensating for overall skew |
US6201829B1 (en) * | 1998-04-03 | 2001-03-13 | Adaptec, Inc. | Serial/parallel GHZ transceiver with pseudo-random built in self test pattern generator |
US6594275B1 (en) * | 1998-04-03 | 2003-07-15 | Texas Instruments Incorporated | Fibre channel host bus adapter having multi-frequency clock buffer for reduced power consumption |
US6377575B1 (en) * | 1998-08-05 | 2002-04-23 | Vitesse Semiconductor Corporation | High speed cross point switch routing circuit with word-synchronous serial back plane |
EP0996262A1 (de) * | 1998-10-22 | 2000-04-26 | Texas Instruments France | Kommunikationssystem mit mehreren synchronisierten Datenverbindungen |
US6618395B1 (en) * | 1999-05-27 | 2003-09-09 | 3Com Corporation | Physical coding sub-layer for transmission of data over multi-channel media |
US6140926A (en) * | 1999-07-21 | 2000-10-31 | Hewlett-Packard Company | Redundant status indicators for fault tolerance |
US6775328B1 (en) * | 1999-08-11 | 2004-08-10 | Rambus Inc. | High-speed communication system with a feedback synchronization loop |
US6577649B1 (en) * | 1999-11-12 | 2003-06-10 | International Business Machines Corporation | Multiplexer for asynchronous data |
US6738935B1 (en) * | 2000-02-07 | 2004-05-18 | 3Com Corporation | Coding sublayer for multi-channel media with error correction |
JP4407104B2 (ja) * | 2002-08-30 | 2010-02-03 | 富士ゼロックス株式会社 | 信号伝送システム |
-
2000
- 2000-03-15 GB GBGB0006291.9A patent/GB0006291D0/en not_active Ceased
-
2001
- 2001-01-22 DE DE60136025T patent/DE60136025D1/de not_active Expired - Lifetime
- 2001-01-22 EP EP01300531A patent/EP1134668B1/de not_active Expired - Lifetime
- 2001-03-15 US US09/808,664 patent/US7031347B2/en not_active Expired - Fee Related
-
2006
- 2006-03-22 US US11/386,418 patent/US20060187968A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
EP1134668B1 (de) | 2008-10-08 |
US20060187968A1 (en) | 2006-08-24 |
EP1134668A3 (de) | 2006-02-08 |
US20010033568A1 (en) | 2001-10-25 |
EP1134668A2 (de) | 2001-09-19 |
US7031347B2 (en) | 2006-04-18 |
GB0006291D0 (en) | 2000-05-03 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |