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DE60021623D1 - Multiplizierer und verschiebungsanordnung mit benutzung von vorzeichenzifferzahlen darstellung - Google Patents

Multiplizierer und verschiebungsanordnung mit benutzung von vorzeichenzifferzahlen darstellung

Info

Publication number
DE60021623D1
DE60021623D1 DE60021623T DE60021623T DE60021623D1 DE 60021623 D1 DE60021623 D1 DE 60021623D1 DE 60021623 T DE60021623 T DE 60021623T DE 60021623 T DE60021623 T DE 60021623T DE 60021623 D1 DE60021623 D1 DE 60021623D1
Authority
DE
Germany
Prior art keywords
reduced
shifting
hardware
multiplication
multiplier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60021623T
Other languages
English (en)
Other versions
DE60021623T2 (de
Inventor
Marko Kosunen
Kari Halonen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Oyj
Nokia Inc
Original Assignee
Nokia Oyj
Nokia Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Oyj, Nokia Inc filed Critical Nokia Oyj
Application granted granted Critical
Publication of DE60021623D1 publication Critical patent/DE60021623D1/de
Publication of DE60021623T2 publication Critical patent/DE60021623T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/527—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel
    • G06F7/5272—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel with row wise addition of partial products
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
    • G06F5/015—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising having at least two separately controlled shifting levels, e.g. using shifting matrices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30025—Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Complex Calculations (AREA)
  • Filters That Use Time-Delay Elements (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Calculators And Similar Devices (AREA)
DE60021623T 2000-10-16 2000-10-16 Multiplizierer und verschiebungsanordnung mit benutzung von vorzeichenzifferzahlen darstellung Expired - Fee Related DE60021623T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2000/010166 WO2002033537A1 (en) 2000-10-16 2000-10-16 Multiplier and shift device using signed digit representation

Publications (2)

Publication Number Publication Date
DE60021623D1 true DE60021623D1 (de) 2005-09-01
DE60021623T2 DE60021623T2 (de) 2006-06-01

Family

ID=8164134

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60021623T Expired - Fee Related DE60021623T2 (de) 2000-10-16 2000-10-16 Multiplizierer und verschiebungsanordnung mit benutzung von vorzeichenzifferzahlen darstellung

Country Status (7)

Country Link
US (1) US7257609B1 (de)
EP (1) EP1330700B1 (de)
CN (1) CN1306390C (de)
AT (1) ATE300761T1 (de)
AU (1) AU2001212724A1 (de)
DE (1) DE60021623T2 (de)
WO (1) WO2002033537A1 (de)

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US8213467B2 (en) * 2004-04-08 2012-07-03 Sonosite, Inc. Systems and methods providing ASICs for use in multiple applications
WO2005114415A2 (en) * 2004-05-11 2005-12-01 North Dakota State University Parallel architecture for low power linear feedback shift registers
DE602004008904D1 (de) * 2004-07-13 2007-10-25 St Microelectronics Srl Vorrichtung zur digitalen Signalverarbeitung unter Verwendung der CSD Darstellung
US7680872B2 (en) * 2005-01-11 2010-03-16 Via Telecom Co., Ltd. Canonical signed digit (CSD) coefficient multiplier with optimization
DE602006007828D1 (de) * 2005-03-31 2009-08-27 Nxp Bv Kanonisch gezeichneter digitaler multiplikator
JP2007097089A (ja) * 2005-09-30 2007-04-12 Yokogawa Electric Corp コーディング回路及びコーディング装置
US7680474B2 (en) * 2005-10-04 2010-03-16 Hypres Inc. Superconducting digital mixer
US7904841B1 (en) * 2007-10-12 2011-03-08 Lockheed Martin Corporation Method and system for optimizing digital filters
CN101840322B (zh) * 2010-01-08 2016-03-09 北京中星微电子有限公司 滤波器运算单元复用的方法和滤波器的运算系统
CN101866278B (zh) * 2010-06-18 2013-05-15 广东工业大学 一种异步迭代的64位整型乘法器及其计算方法
CN102314215B (zh) * 2011-09-27 2014-03-12 西安电子科技大学 集成电路系统中小数乘法器的低功耗优化方法
EP2608015B1 (de) 2011-12-21 2019-02-06 IMEC vzw System und Verfahren zur Ausführung einer Multiplikation
CN103051420B (zh) * 2012-12-14 2015-04-08 无锡北邮感知技术产业研究院有限公司 一种mimo系统码本生成方法
GB2535426B (en) * 2014-10-31 2021-08-11 Advanced Risc Mach Ltd Apparatus, method and program for calculating the result of a repeating iterative sum
US10313641B2 (en) 2015-12-04 2019-06-04 Google Llc Shift register with reduced wiring complexity
CN109194307B (zh) * 2018-08-01 2022-05-27 南京中感微电子有限公司 数据处理方法及系统
US10761847B2 (en) * 2018-08-17 2020-09-01 Micron Technology, Inc. Linear feedback shift register for a reconfigurable logic unit
WO2020155136A1 (en) * 2019-01-31 2020-08-06 Hong Kong Applied Science and Technology Research Institute Company Limited Reconfigurable segmented scalable shifter
US10826529B2 (en) 2019-01-31 2020-11-03 Hong Kong Applied Science And Technology Research Institute Co., Ltd. Parallel LDPC decoder
US10877729B2 (en) 2019-01-31 2020-12-29 Hong Kong Applied Science And Technology Research Institute Co., Ltd. Reconfigurable segmented scalable shifter
CN110515587B (zh) * 2019-08-30 2024-01-19 上海寒武纪信息科技有限公司 乘法器、数据处理方法、芯片及电子设备
CN110515589B (zh) * 2019-08-30 2024-04-09 上海寒武纪信息科技有限公司 乘法器、数据处理方法、芯片及电子设备
CN110413254B (zh) * 2019-09-24 2020-01-10 上海寒武纪信息科技有限公司 数据处理器、方法、芯片及电子设备
US11658643B2 (en) * 2021-01-18 2023-05-23 Raytheon Company Configurable multiplier-free multirate filter
US11575390B2 (en) 2021-07-02 2023-02-07 Hong Kong Applied Science and Technology Research Insitute Co., Ltd. Low-latency segmented quasi-cyclic low-density parity-check (QC-LDPC) decoder

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57141753A (en) 1981-02-25 1982-09-02 Nec Corp Multiplication circuit
US4947364A (en) * 1985-10-23 1990-08-07 Hewlett-Packard Company Method in a computing system for performing a multiplication
US4967388A (en) 1988-04-21 1990-10-30 Harris Semiconductor Patents Inc. Truncated product partial canonical signed digit multiplier
US5253195A (en) * 1991-09-26 1993-10-12 International Business Machines Corporation High speed multiplier
US5262974A (en) * 1991-10-28 1993-11-16 Trw Inc. Programmable canonic signed digit filter chip
JPH06259228A (ja) * 1993-03-10 1994-09-16 Mitsubishi Electric Corp 乗算器
US5465222A (en) * 1994-02-14 1995-11-07 Tektronix, Inc. Barrel shifter or multiply/divide IC structure
US5978822A (en) * 1995-12-29 1999-11-02 Atmel Corporation Circuit for rotating, left shifting, or right shifting bits
US6590931B1 (en) * 1999-12-09 2003-07-08 Koninklijke Philips Electronics N.V. Reconfigurable FIR filter using CSD coefficient representation
US7080115B2 (en) * 2002-05-22 2006-07-18 Broadcom Corporation Low-error canonic-signed-digit fixed-width multiplier, and method for designing same
US7277479B2 (en) * 2003-03-02 2007-10-02 Mediatek Inc. Reconfigurable fir filter

Also Published As

Publication number Publication date
DE60021623T2 (de) 2006-06-01
CN1306390C (zh) 2007-03-21
ATE300761T1 (de) 2005-08-15
CN1454347A (zh) 2003-11-05
US7257609B1 (en) 2007-08-14
WO2002033537A1 (en) 2002-04-25
EP1330700A1 (de) 2003-07-30
AU2001212724A1 (en) 2002-04-29
EP1330700B1 (de) 2005-07-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee