DE4408020B4 - Process for the production of silicon chips with test structures - Google Patents

Abstract

method for the production of silicon chips (1), wherein the elongated structures (2) in one Etched silicon wafer (3) and the wafer (3) along dividing lines (4, 14) Introducing cuts (16) into individual chips (1), characterized in that in nearby the dicing lines (14) Test structures (5), in which a check on the parallelism of the cuts (16) to the elongated ones Structures (2) possible is.

Description

The The invention is based on a silicon chip according to the preamble of independent claim 1. From an article by Hillerich in Microsystems Technology 90, publisher Reichl, Springer Verlag, 1990, pages 456 to 464 are already silicon chips with oblong Structures known for coupling glass fibers to waveguides be used. The elongated ones Structures are as trenches formed in the silicon chips.

From the DE 40 20 195 A1 For example, a semiconductor chip obtained by cutting a semiconductor wafer is known while preventing cracks or cracks from entering the inside of the electronic element region.

From the US 4,890,895 A1 For example, an optical device is known in which a trench is provided in a silicon substrate for alignment and reception of an optical (glass) fiber.

Advantages of invention

The inventive method with the characterizing features of independent claim 1 has the other hand Advantage that the parallelism the elongated one Structures relative to the chip edge can be checked. The chip edge can thus for used the further processing of the silicon chip as a stop be that high-precision aligned parallel to the actual structures.

By those in the dependent Claims listed measures are advantageous developments and improvements of the independent claim specified method possible. To obtain a high precision the relative orientation of test structure too elongated Structure, it is advantageous to produce these with the same process steps, because so the relative alignment of these structures with each other remains. Especially precise This can be done by using a mask. By use of alignment structures in the area of the dicing lines the cuts are precise Align along the dicing lines. Especially easy the introduction of the cuts by sawing.

drawings

Embodiments of the invention are illustrated in the drawings and explained in more detail in the following description. It show the 1 a plan view of a silicon wafer with structures for a silicon chip, 2 an enlarged detail view of 1 , and 3 a cross section through a silicon wafer.

description

In the 1 is a plan view of a section of a silicon wafer 3 shown. By dividing along the dividing lines 4 . 14 becomes the silicon wafer 3 into individual silicon chips 1 divided. In the silicon wafer are elongated structures 2 brought in. These structures represent the actual useful elements of the silicon chip 1 dar. In the elongated structures 2 As shown here, these can be, for example, trenches for the adjustment of glass fibers. Glass fibers are inserted into these trenches and thus have a defined position and alignment with each other. It may now be desirable for the cut to be along the dicing line 14 through the wafer 3 is guided, a defined position relative to the elongated structures 2 in particular, that the resulting cut parallel to the elongated structures 2 is. For applications in which an adjustment of glass fibers takes place, a misalignment of a few micrometers already represent a significant deterioration. It must therefore be ensured that the cut exactly on the dicing line 14 to come to rest. In a finished chip must continue to exist the possibility of parallelism of the elongated structures 2 to measure relative to the chip edge. For aligning the cut on the dicing line 14 are the alignment structures 8th intended. In the finished chip, a measurement of the chip edge relative to the elongated structures 2 to enable, are the test structures 5 intended. The 2 shows the alignment structures 8th and the test structures 5 in an enlarged view.

For aligning the cuts on the dicing lines 4 . 14 are the alignment crosses 9 and the alignment structures 8th intended. The alignment structures are elongated trenches running on both sides of the dicing lines 14 are arranged. The alignment crosses 9 serve to align the cuts on the dicing lines 4 , Since the cutting width is usually wider than the Justierkreuzstrukturen 9 (For example, 50 microns), these are destroyed in these first dicing cuts. The orientation of the top-to-bottom cuts on the dicing lines 14 then takes place on the basis of the alignment structures 8th , In principle would be for the alignment of the cuts on the dicing lines 14 Also suitable other crosshairs, which are arranged such that they from the cuts on the dicing lines 4 not be destroyed. The here shown, designed as elongated trench structures alignment structures 8th however, have white terhin the advantage that deviations from the parallelism under a microscope can be detected very well, since then form elongated sharp triangles or trapezoids, which are particularly easy to recognize.

To check the parallel alignment of the elongated structures 2 relative to the cuts on the dividing lines 14 It would also be possible in principle, the distances between the chip edge thus formed and the structures 2 to measure directly. Technically, this approach is problematic because the structures 2 often several hundred micrometers are removed from the chip edge thus formed and a measurement accuracy of a few micrometers is required. Meßtechnisch is the use of test structures 5 much easier, as these are at a very short distance to the dividing line 14 are arranged. In the 2 become test structures 5 shown formed as a plurality of elongated trenches. However, they are any structures other than test structures 5 conceivable. The trench structures shown here for the alignment structures 8th and the test structures 5 are here, for example, each ten microns wide. In the 3 will now be shown how an exact alignment of the test structures 5 relative to the elongated structures 2 can be achieved. On the surface of the silicon wafer 3 initially becomes a masking layer over the whole area 6 , For example, of silicon oxide or silicon nitride applied. The surface of the masking layer is then coated with a photoresist 17 covered. The photoresist is through a mask 7 , the opaque structures 15 has, durchbelichtet. The exposure causes the photoresist layer 17 changed so that it can be removed in certain areas. The masking layer is then removed through this opening, so that in certain areas the silicon surface is exposed. After removal of the photoresist, trench structures for the elongated structures are then etched by means of an anisotropic etchant such as sodium hydroxide solution 2 or for the test structures 5 brought in. Subsequently, the silicon wafer is transformed into individual silicon chips 1 divided by on the dividing lines 14 slice 16 be introduced. By measuring the distance between the test structure 5 and the chip edge 18 can then also on the distance between the chip edge 18 and the elongated structure 2 getting closed. It is particularly important that the elongated structure 2 and the test structure 5 be made with the same method and only a single mask 7 is needed. The accuracy with which the structures on the mask 7 are also defined, the accuracy with which the structure 5 relative to the structure 2 is arranged. For masks 7 For example, accuracies on the order of less than 0.3 microns can be achieved over a distance of 10 cm. As this accuracy also affects the alignment of test structure 5 relative to the elongated structure 2 transmits, can thus by measuring the distance from the chip edge 18 to the test structure 5 on the distance from chip edge 18 to the elongated structure 2 getting closed. If, as in the 1 shown, two widely spaced test structures 5 are provided, so very much the parallelism of chip edge 18 and elongated structure 2 be determined.

Because of the test structures 5 in a simple way the distance of the chip edge 18 to the test structures 5 can be determined, in addition to the determination of the parallel orientation also further statements about the quality of the saw cut can be made. When sawing, the silicon wafer 3 usually with the bottom 20 on an adhesive foil 21 fixed. The cut 16 extends like in the 3 is shown only a little way into the film 21 in, so that the relative position of the chips 1 initially preserved. By the in 2 shown arrangement of test structures 5 on both sides of the dividing line 14 can then be removed before removing the chips 1 from the slide 21 the centrality of the arrangement of the cut 16 determine. By in the 3 shown further test structure 22 on the bottom 20 of the wafer 3 can be a deviation of the cut 16 from the perpendicular.

Claims (4)

Method for producing silicon chips ( 1 ), in which elongated structures ( 2 ) in a silicon wafer ( 3 ) and the wafer ( 3 ) along dividing lines ( 4 . 14 ) by introducing cuts ( 16 ) into individual chips ( 1 ), characterized in that in the vicinity of the dicing lines ( 14 ) Test structures ( 5 ), in which a check on the parallelism of the cuts ( 16 ) to the elongated structures ( 2 ) is possible. Method according to claim 1, characterized in that the production of the elongated structures ( 2 ) and the test structures ( 5 ) by applying a masking layer ( 6 ), Structuring the masking layer ( 6 ) by means of a mask ( 7 ) and then applying the silicon wafer ( 3 ) with an etchant. Method according to one of the preceding claims, characterized in that furthermore an alignment structure ( 8th ) generated in the region of the dicing lines ( 14 ) an orientation of the cuts ( 16 ) on the dividing lines ( 14 ) allowed. Method according to one of the preceding claims, characterized in that the cuts ( 16 ) are introduced by sawing.