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DE4332783A1 - Configurable electronic component for surface mounting - Google Patents

Configurable electronic component for surface mounting

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Publication number
DE4332783A1
DE4332783A1 DE4332783A DE4332783A DE4332783A1 DE 4332783 A1 DE4332783 A1 DE 4332783A1 DE 4332783 A DE4332783 A DE 4332783A DE 4332783 A DE4332783 A DE 4332783A DE 4332783 A1 DE4332783 A1 DE 4332783A1
Authority
DE
Germany
Prior art keywords
solid
electronic component
state circuit
component
surface mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE4332783A
Other languages
German (de)
Inventor
Hans Ulrich Jacob
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
REICHHARDT BERND
Original Assignee
REICHHARDT BERND
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by REICHHARDT BERND filed Critical REICHHARDT BERND
Priority to DE4332783A priority Critical patent/DE4332783A1/en
Publication of DE4332783A1 publication Critical patent/DE4332783A1/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5382—Adaptable interconnections, e.g. for engineering changes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

The object of the invention is to specify a configurable component which requires little space and allows rational fabrication and testing. The object is achieved in that one or more electronic components are applied on the same support plate for all configuration variants. The invention relates to a configurable electronic component for surface mounting. The electronic component produces, for various configuration, the same electrical connection conditions and geometrical dimensions. <IMAGE>

Description

Die Erfindung bezieht sich auf ein konfigurierbares elektronisches Bauelement für die Oberflächenmon­ tage. Das elektronische Bauelement realisiert für verschiedene Konfigurationen gleiche elektrische Anschlußbedingungen und geometrische Abmessungen.The invention relates to a configurable electronic component for the surface mon days. The electronic component realized for different configurations same electrical Connection conditions and geometric dimensions.

Im Stand der Technik sind Bauelemente zur Oberflä­ chenmontage unterschiedlicher Bauformen bekannt. So sind beispielsweise für hochpolige Festkörper­ schaltkreise Gehäuseformen entwickelt worden, in denen die Festkörperschaltkreise auf Trägern aufge­ bracht werden, welche die elektrische Kontaktierung zum Löten auf einer Leiterplatte realisieren. Durch eine Verpackung in einem sogenannten Standardge­ häuse werden die Festkörperschaltkreise vor mecha­ nischen Einflüssen geschützt. Nachteile dieser Ge­ häuseformen entstehen bei steigender Komplexität der Festkörperschaltkreise durch die steigende An­ zahl der Anschlußkontakte und einer damit verbun­ denen Vergrößerung des Gehäuses und Verringerung der Anschlußabstände. In the prior art, components for surface Chen Montage known different designs. So are for example for multi-pole solids circuits housing shapes have been developed in which the solid-state circuits on carriers are brought, which is the electrical contacting for soldering on a circuit board. By a package in a so-called standard package the solid-state circuits in front of mecha protected from African influences. Disadvantages of this Ge Housing shapes arise with increasing complexity the solid state circuits by the increasing on Number of contacts and one connected to it which enlargement of the housing and reduction the connection distances.  

Ferner sind sogenannte multifunktionale Festkörper­ schaltkreise bekannt. Bei diesen besteht die Mög­ lichkeit, durch unterschiedliche Signalbelegung der auf dem Festkörperschaltkreis vorhandenen Anschluß­ punkte diesem unterschiedliche Funktionen zuzuwei­ sen. Dies ist insbesondere bei Speicherschaltkrei­ sen und Gate-Arrays möglich. Die Nutzung dieser Konfigurierbarkeit ist bei Festkörperschaltkreisen in Standardgehäusen in allgemeinen nicht möglich, weil die dafür notwendige Verbindung aller An­ schlußpunkte des Festkörperschaltkreises mit den Gehäuseanschlüssen einen hohen Aufwand erfordern würde.Furthermore, so-called multifunctional solids circuits known. With these there is the possibility by different signal assignment of the existing connection on the solid state circuit assign different functions to it sen. This is particularly the case with memory circuits sen and gate arrays possible. The use of this Configurability is with solid state circuits generally not possible in standard housings, because the necessary connection of all people ends of the solid-state circuit with the Housing connections require a lot of effort would.

Zur Realisierung der oben beschriebenen Konfigu­ rierbarkeit wird im Stand der Technik die allgemein bekannte COB-Montage (Chip-On-Board-Technik oder Nacktchipmontage) angewendet. Diese Montageart er­ möglicht zwar die flexible Ausführung der Anschluß­ belegung. Der Nachteil dieses Verfahrens bei ge­ meinsamer Montage mehrerer Festkörperschaltkreise auf dem Träger besteht jedoch in einer hohen Monta­ gezeit. Wegen der verschiedenen einsatzspezifischen Ausführungen der Träger werden vielfältige Handha­ bungsoperationen notwendig. Weiterhin erhöht sich der Anteil nicht funktionsfähiger Baugruppen bei Ausfall einzelner Festkörperschaltkreise, wobei die Prüfung der Baugruppen aus funktionellen Gründen am Ende des Montageprozesses durchgeführt wird. Dabei auftretende Ausfälle einzelner Bauelemente führen zur Funktionsunfähigkeit der Baugruppe und damit zu hohen Kosten.To implement the configuration described above The general state of the art in the prior art well-known COB assembly (chip-on-board technology or Naked chip assembly) applied. This type of assembly he possible the flexible execution of the connection occupancy. The disadvantage of this method with ge joint assembly of several solid-state circuits on the carrier, however, there is a high monta tide. Because of the different mission-specific Executions of the carriers become diverse handha exercise operations necessary. Further increases the proportion of non-functional assemblies Failure of individual solid-state circuits, the Checking the modules for functional reasons on At the end of the assembly process. Here failures of individual components to the inoperability of the module and thus to high costs.

Der Erfindung liegt die Aufgabe zugrunde, ein kon­ figurierbares Bauelement anzugeben, das einen ge­ ringen Platzbedarf aufweist und eine rationelle Fertigung und Prüfung ermöglicht.The invention has for its object a con specifiable component that a ge wrestle requires space and a rational Manufacturing and testing enabled.

Erfindungsgemäß wird die Aufgabe dadurch gelöst, daß ein oder mehrere elektronische Komponenten auf einer für alle Konfigurationsvarianten gleichen Trägerplatte aufgebracht werden.According to the invention, the object is achieved by that one or more electronic components are on one is the same for all configuration variants Carrier plate are applied.

Die Konfigurierbarkeit wird dabei dadurch erreicht, daß die unverkappten Festkörperschaltkreise mittels Drahtbonden bei beliebig wählbaren Bondoptionen mit der Trägerplatte verbunden werden.The configurability is achieved by that the uncapped solid state circuit means Wire bonding with any selectable bond options the carrier plate are connected.

Die Bearbeitung der Trägerplatten kann in Einzel- oder Mehrfachanordnung erfolgen.The processing of the carrier plates can be or multiple arrangement.

Eine vorteilhafte Ausgestaltung des erfindungsgemä­ ßen Bauelementes sieht vor, daß zum Schutz der ge­ bondeten Aufbauten vor äußeren Einflüssen eine Um­ hüllung der Bauelemente angebracht wird. Dabei kann die Bauhöhe dieser Umhüllung durch Verwendung eines dünnen Abdeckmaterials minimiert werden.An advantageous embodiment of the ß component provides that to protect the ge bonded superstructures against external influences envelope of the components is attached. It can the height of this envelope by using a thin cover material can be minimized.

Ferner ist es möglich, die Leiterbahnen der Ober­ seite mittels Durchkontaktierungen mit den Leiter­ bahnen der Unterseite zu verbinden, um die elek­ trische Anschlußbelegung der Trägerplatten zu ver­ einheitlichen.It is also possible to use the conductor tracks of the upper side through vias with the conductor tracks to connect the bottom to the elec trical pin assignment of the carrier plates to ver uniform.

Die Erfindung wird nachfolgend anhand eines Ausfüh­ rungsbeispieles näher erläutert. In der zugehörigen Zeichnung zeigen:The invention is based on an Ausfüh Example explained approximately. In the associated Show drawing:

Fig. 1 ein konfigurierbares Bauelement in per­ spektivischer Darstellung, FIG. 1 a configurable component in via spectral tivi shear representation,

Fig. 2 ein umhülltes Bauelement in Schnittdar­ stellung und Fig. 2 is a covered component in Schnittdar position and

Fig. 3 eine Mehrfachanordnung der Träger­ platte. Fig. 3 shows a multiple arrangement of the carrier plate.

Wie aus Fig. 1 ersichtlich ist, wird ein Festkör­ perschaltkreis (2) auf eine Trägerplatte (1) mon­ tiert. Die Trägerplatte (1) weist für alle Be­ stückungsvariaten gleiche Abmessungen sowie gleiche Positionen und Gestaltung der Anschlußkontakte (6) auf. Der Festkörperschaltkreis (2) wird mit Bond­ drähten (3) mit den Anschlußflächen (7), (8) elek­ trisch verbunden, wobei je nach dem vorgesehen An­ wendungsfall jeweils unterschiedliche Bondoptionen vorgegebenen werden können.As can be seen from Fig. 1, a solid state circuit ( 2 ) on a carrier plate ( 1 ) is installed. The carrier plate ( 1 ) has the same dimensions for all loading variants, as well as the same positions and design of the connecting contacts ( 6 ). The solid-state circuit ( 2 ) with wires ( 3 ) with the pads ( 7 ), ( 8 ) electrically connected, depending on the intended application, different bond options can be specified.

Die wählbare, funktionelle Konfigurierbarkeit des Bauelementes wird durch Auswahl der Verbindungen der Anschlußpunkte (9) des Festkörperschaltkreises mit den Anschlußflächen (7) oder (8) der Träger­ platte (1) erreicht.The selectable, functional configurability of the component is achieved by selecting the connections of the connection points ( 9 ) of the solid-state circuit with the connection surfaces ( 7 ) or ( 8 ) of the carrier plate ( 1 ).

Die elektrische Verbindung zwischen den Anschluß­ flächen (7, 8) oder weiteren Anschlußflächen und den Anschlußkontakten (6) der Trägerplatte (1) wird durch die oben liegenden Leiterbahnen (10) gewährleistet. Durch unten liegende Leiterbahnen (13) können sie weiter ergänzt werden.The electrical connection between the connection surfaces ( 7 , 8 ) or further connection surfaces and the connection contacts ( 6 ) of the carrier plate ( 1 ) is ensured by the conductor tracks ( 10 ) located above. They can be further supplemented by conductor tracks ( 13 ) located below.

Fig. 2 veranschaulicht die elektrische Verbindung einer oben liegenden Leiterbahn (10) mit einer un­ ten liegenden Leiterbahn (13) durch innen liegende Durchkontaktierungen (11) sowie Anschlußkontakte (6). Weiterhin ist die Umhüllung (5) des gebondeten Festkörperschaltkreises (2) ersichtlich, wobei mit einem dünnen Abdeckmaterial (4) die Bauhöhe mini­ miert werden kann. Fig. 2 illustrates the electrical connection of an overhead conductor track ( 10 ) with a un th lying conductor track ( 13 ) through internal vias ( 11 ) and contacts ( 6 ). Furthermore, the envelope ( 5 ) of the bonded solid-state circuit ( 2 ) can be seen, with a thin covering material ( 4 ) the overall height can be minimized.

Fig. 3 zeigt eine Ausführungsform der Trägerplatte in Mehrfachanordnung (12). Die einzelnen Träger­ platten (1) können durch Freischnitt (14) für das Vereinzeln aus der Mehrfachanordnung vorbereitet sein. Fig. 3 shows an embodiment of the carrier plate in a multiple arrangement ( 12 ). The individual carrier plates ( 1 ) can be prepared by cutting ( 14 ) for separating them from the multiple arrangement.

BezugszeichenlisteReference list

1 Trägerplatte
2 Festkörperschaltkreis
3 Bonddraht
4 dünnes Abdeckmaterial
5 Umhüllung
6 Anschlußkontakt
7 Anschlußfläche
8 Anschlußfläche
9 Anschlußpunkt auf Festkörperschaltkreis
10 oben liegende Leiterbahn
11 innen liegende Leiterbahn
12 Mehrfachanordnung
13 unten liegende Leiterbahn
14 Freischnitt 1 carrier plate
2 solid state circuit
3 bond wire
4 thin cover material
5 wrapping
6 connection contact
7 pad
8 pad
9 Connection point on solid-state circuit
10 conductor tracks on top
11 internal tracks
12 multiple arrangement
13 conductor track below
14 free cut

Claims (4)

1. Konfigurierbares elektronisches Bauelement für die Oberflächenmontage, bei der mindestens ein Festkörperschaltkreis (2) auf einer mit Anschluß­ kontakten (6) versehenen Trägerplatte (1) angeord­ net ist, dadurch gekennzeichnet, daß ein unverkapp­ ter Festkörperschaltkreis (2) auf einer für belie­ big wählbare Konfigurationsvariaten einheitlichen Trägerplatte (1) angeordnet ist und der Festkörper­ schaltkreis (2) mit Bonddrähten (3) wahlweise je nach vorzugebenden Bondoptionen mit elektrischen Anschlußflächen (7), (8) verbunden ist.1. Configurable electronic component for surface mounting, in which at least one solid-state circuit ( 2 ) on a with contacts ( 6 ) provided support plate ( 1 ) is angeord net, characterized in that an uncapped ter solid-state circuit ( 2 ) on one for belie big Selectable configuration variants uniform support plate ( 1 ) is arranged and the solid-state circuit ( 2 ) with bond wires ( 3 ) optionally depending on the bond options to be specified with electrical connection surfaces ( 7 ), ( 8 ). 2. Bauelement nach Anspruch 1, dadurch gekennzeich­ net, daß neben Festkörperschaltkreisen weitere elektronische Komponenten auf der Trägerplatte (1) angeordnet sind.2. Component according to claim 1, characterized in that in addition to solid-state circuits, further electronic components are arranged on the carrier plate ( 1 ). 3. Bauelement nach Anspruch 1 oder 2, dadurch ge­ kennzeichnet, daß an dem optischen Bauelement Um­ hüllungen aus einem dünnen Abdeckmaterial angeord­ net sind. 3. Component according to claim 1 or 2, characterized ge indicates that on the optical component Um sleeves arranged from a thin covering material are not.   4. Bauelement nach einem der Ansprüche 1 bis 4, da­ durch gekennzeichnet, daß auf der Trägerplatte (1) die oben liegenden Leiterbahnen (10) mittels Durch­ kontaktierungen (11) mit unten liegenden Leiterbah­ nen (13) verbunden sind.4. Component according to one of claims 1 to 4, characterized in that on the carrier plate ( 1 ) the overhead conductor tracks ( 10 ) by means of contacts ( 11 ) with the underlying conductor tracks NEN ( 13 ) are connected.
DE4332783A 1993-09-27 1993-09-27 Configurable electronic component for surface mounting Withdrawn DE4332783A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE4332783A DE4332783A1 (en) 1993-09-27 1993-09-27 Configurable electronic component for surface mounting

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DE4332783A DE4332783A1 (en) 1993-09-27 1993-09-27 Configurable electronic component for surface mounting

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002078076A2 (en) * 2001-03-26 2002-10-03 Micronas Gmbh Method for realizing wiring options in an integrated circuit and a corresponding integrated circuit
DE102007003481A1 (en) * 2006-12-11 2008-06-12 Kreton Corp., Jhonghe Memory chip and insert card with the same on it

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2138210A (en) * 1982-02-05 1984-10-17 Hitachi Ltd A multiple frame
DE8717620U1 (en) * 1986-04-25 1991-02-07 Wolf, Eckhard, Dr.-Ing., 7000 Stuttgart Device for connecting a connection-incompatible integrated circuit to a printed circuit board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2138210A (en) * 1982-02-05 1984-10-17 Hitachi Ltd A multiple frame
DE8717620U1 (en) * 1986-04-25 1991-02-07 Wolf, Eckhard, Dr.-Ing., 7000 Stuttgart Device for connecting a connection-incompatible integrated circuit to a printed circuit board

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
et.al.: Precision Flip-Chip Solder Bump Interconnects for Optical Packaging. In: IEEE Transactions on Components, Hybrids, and Manufacturing Technology,Dec.1992,Vol.15,No.6, S.977-982 *
IMLER, William R. *
JP 2-280346 A. In: Patents Abstracts of Japan, E-1030, Feb. 6, 1991, Vol. 15, No. 50 *
KEHLER, Walt *
MEADOR, Richard: IC Chip Carrier with Internal Ground and VCC Bus. In: Motorola Technical Developments,Oct.1988,Vol.8,S.74 *
TAUBITZ, Gerhard: Miniaturleiterplatten für die moderne Mikroelektronik. In: Elektronik, 23, 16.11.1984, S.125-129 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002078076A2 (en) * 2001-03-26 2002-10-03 Micronas Gmbh Method for realizing wiring options in an integrated circuit and a corresponding integrated circuit
WO2002078076A3 (en) * 2001-03-26 2003-10-02 Micronas Gmbh Method for realizing wiring options in an integrated circuit and a corresponding integrated circuit
DE10114767B4 (en) * 2001-03-26 2017-04-27 Tdk-Micronas Gmbh Method for implementing integrated circuit and integrated circuit wiring options
DE102007003481A1 (en) * 2006-12-11 2008-06-12 Kreton Corp., Jhonghe Memory chip and insert card with the same on it

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