DE4223679A1 - Status signal transmission system for monitoring and alarm installations - uses bus distributors to alert control unit to presence of noise signals in bus system - Google Patents

Abstract

The transmission system has a control unit (1) with a microprocessor, a memory, an input-output unit and a display. It also has a number of addressable bus distributors (V01-V16) to report noise signals to the control unit (1). A four-wire connection system (2) with current supply lines connects the control unit (1) to the bus distributers (V01-V16). The connection system (2) has a control line, a timing line and two current supply lines. Addressing time signals to the bus distributors and also status queries from the addressed distributors (V01-V16) are transmitted along the timing line. The control line prevents blocking of the timing line by close report signals. The distributors (VO1-V16) can be connected to each other in series or parallel and are connected to the control unit (1) via the connection system (2). ADVANTAGE - Report signals can be accurately identified or allocated to respective distributors. Guarantees variable and flexible connection between individual reporting units. Cost and complexity kept to min.

Description

The invention relates to a message signal transmission System according to the preamble of claim 1.

Conventional monitoring and alarm systems exist übli possibly from a central office to which a connection sy stem several signaling lines are connected.

Fig. 1 shows a block diagram of a conventional moni monitoring and alarm system in which the connection system consists of egg nem 4-wire system with a reference potential line 15 , a data signal line 17 , an interrogation signal line 16 and egg ner Störsignalleitung 14 . In such systems, individual message units 11 , 12 and 13 are serially unterein other and connected to the center, the noise signal line 14 is connected to the delay-free message a disturbance un indirectly with the center, ie through the Mel deeinheiten 11 , 12 and 13 is looped through , After a meeting of such a signal, the individual message units are interrogated by means of a Abfra gezyklus from the central unit until the alarm signal associated reporting unit is identified to average the detector specific Informa tion via the data signal line 17 of the center.

The disadvantage of such message signal Übertragungssyste men, however, that the individual message units only serially with can be connected to each other and that when occurrence of Interference signals a reaction in the control center is possible, wah the assignment to the message unit takes place with a time delay. Before the assignment takes place, the fault could already be be gone again, so that the quick reaction to all if without identification of the causal reporting unit can take place.

The invention is therefore the object of a Meldesi gnal transmission system for monitoring and alarm systems  create a flexible and flexible interconnection of the individual message units is ensured and in which the Assignment of the interfering signal to the respective message unit tig is, whereby the technical expenditure in the reporting units remains low.

This object is achieved with the characterizing in the invention Part of claim 1 specified features solved.

By the message signal transmission system according to the invention it is possible in a surveillance and alarm system the individual message units or bus distributor in any manner and way to connect and thus optimally to the correspond adapt to the requirements. Thus, for each Überwa fast and easy an ideal solution be found, on the one hand a clear assignment or individual identification of interference signal and respective bus Distributor or respective reporting line guaranteed and others on the other hand a high flexibility and a nearly arbitrary He has continuity.

Another advantage is that the technical Auf wall and thus the costs of development and production the individual bus distributor are very low, since all Steu functions are performed by the control unit.

In the dependent claims are advantageous embodiments of Invention listed.

The invention is described below with reference to a Embodiment with reference to the drawing nä her explained.

Show it:

Fig. 1 is a block diagram of a conventional signaling signal transmission system for monitoring and alarm systems;

FIG. 2 shows a block diagram of the signaling signal transmission system according to the invention for monitoring and alarm systems; FIG.

Fig. 3 is a block diagram of a control unit;

4 is a block diagram of a bus distributor.

Fig. 5 is a timing chart for a normal polling cycle;

Fig. 6 is a timing diagram for the control of Sammelausgän gene; and

Fig. 7 is a timing diagram for a fast passage after He know a fault that could lead to the alarm.

Fig. 2 shows a block diagram of the alarming signal Übertra supply system for monitoring and alarm systems, the dividers from egg ner control unit 1, a bus 2 and several Busver V is (V01 to V16). Up to 16 bus distributor V can be connected to the control unit 1 via the bus system 2 , the bus distributors V being individually addressable via DIP switches. Each bus distributor V has ever Weil 4 reporting lines ML, which can be queried individually via the bus system abge.

This is due to a fault on the reporting line ML, if the value of the connected terminating resistor z. For example, more than 40% changed.

In addition to monitoring the max. 64 individually identifiable ML reporting lines have 3 additional transmission modes available at the same time via appropriate addressing each of the max. 16 available bus distributor V forwarded can be. Specifically, these are the modes "out of focus", "Walking test" and "signal line reset". In the mode "out of focus" the "disarmed" output of all 16 connectable bus distributors V on [-] potential, d. H. at level L (open collector). in the Mode "walk test" is the output "walk test" of all 16 switchable bus distributor V to level L (open collector), to  z. B. to the detection range of motion detectors to test can. In the mode "Detector Line Reset" is for the duration of the Reset the line voltage on all connected Detection lines switched off. This can z. B. the stored Noise signals from glass-breakage sensors are reset.

control unit

Fig. 3 shows a block diagram of the control unit 1. The control unit 1 is installed either in the immediate vicinity or directly in the control center and monitors up to 16 bus distributors V or 64 reporting lines ML.

The control unit 1 consists essentially of a Mi microprocessor, a memory device, an input / output unit and a display unit and is connected via the common inputs, the common outputs and the bus system to the control center or the bus manifolds V. The control unit 1 can be part of a security control center and can meet their requirements with appropriate hardware and software expenditure.

bus system

The bus system consists of a 4-wire interface, whereby Two lines of power supply serve, one line as a control line and another as a clock / interrogation line is used, d. H. on the one hand provides the clock and others on the other hand is used for signal request. The range of the Bus system is up to 500 m, depending on the cable cross-section being serial, parallel or tree-shaped can.

Bus distributor

At each bus distributor V are via reporting lines ML the various sensors (eg motion sensors, glass breakage sensors,. , , ), resulting in a certain order or Systematisierung the monitoring and alarm system he is possible.  

Fig. 4 shows a block diagram of the bus distributor V, which consists essentially of an address decoder, a counter, a multiplexer, a window comparator and an intermediate memory. Each bus distributor V has a connection for the bus system 2 and four lines for the reporting lines ML. Furthermore, each bus distributor V has two lines for the outputs "walk test" and "out of focus" mentioned above.

In this case, the clock signals sent by the clock line are counted up in the counter and compared in the address decoder with an address set via DIP switches. If the set address matches the count of the counter, the address decoder sends an enable signal to the multiplexer. On the basis of this enable signal, the signal lines ML determined by the value-high bits of the 7-bit counter are applied to the clock line of the bus system 2 via a window comparator and an output stage.

The outgoing from the bus distributor V reporting lines ML are a zeln on z. B. +/- 40% of a change in the respective Ab Resistance monitored. The terminator must be in Idle state 10 kOhm at a line voltage of approx. 8 V DC be carry. It is therefore possible to use all commercially available sensors and to connect detectors who are able to the connection resistance in the o. g. Way to change. So can z. B. also glass breakage sensors are used, the their supply voltage directly from the monitored Meldeli never refer to ML.

addressing

Each of the max. 16 bus distributor V receives its own address. Addressing takes place via a four-bit DIP switch on the respective bus distributor V.

The distribution of the individual addresses is as follows set:

Bus distributor address 0000, Connection 1 → Signal line 01   Connection 2 → Signal line 02 Connection 3 → Signal line 03 Connection 4 → Signal line 04 0001, Connection 1 → Signal line 05 Connection 2 → Signal line 06 Connection 3 → Signal line 07 Connection 4 → Signal line 08 0010, Connection 1 → Signal line 09 Connection 2 → Signal line 10 Connection 3 → Signal line 11 Connection 4 → Signal line 12 , , , 1111 Connection 1 → Signal line 61 Connection 2 → Signal line 62 Connection 3 → Signal line 63 Connection 4 → Signal line 64

In this way, a unique assignment of a Störsig nals to a bus distributor V or a reporting line ML ge guaranteed.

The common signals "out of focus", "walking test" and "Detection Line Reset" are sent from the control unit via the Bus system forwarded to the bus distributor. The 3 ver various modes ("out of focus", "walking test" and "reporting line re set ") are the connectable to the bus V distributors Peri pherie as static control signals available.

Subsequently, the control of the message signal Übertra system described.

According to FIG. 4, each of the attached Schlos Senen to the bus system 2 bus distributor has a V counter which is counted up from the common clock line of the 4-wire interface. A decoder compares the first 4 bits of the counter output with the address of the bus distributor V set to DIP switches and releases the multiplexer if they match. The next 2 bits of the counter output switch one of the 4 input channels, ie one of the 4 detector lines to the window comparator. From here, the result signal is put on the clock line.

For monitoring and individual identification of the max. 64 reporting lines ML, 64 clock pulses are needed. Here, the Evaluation of the 64 inputs on the basis of 64 clock pulses in following order:

1st bar Request distribution 2 (0001), input 1 2nd bar Request distribution 3 (0010), input 1 3rd bar Request distribution 4 (0011), input 1 , @ , @ , @ 15th bar Polling Distributor 16 (1111), input 1 16th bar Request distribution 1 (0000), input 2 17th bar Request distribution 2 (0001), input 2 , @ , @ , @ 62nd bar Polling distributor 15 (1110), input 4 63rd bar Polling Distributor 16 (1111), input 4 64th bar Request distribution 1 (0000), input 1

In this way, first the inputs 1 or the reporting lines 1 of all 16 bus distributors evaluated and then inputs 2 to 4 or reporting lines 2 to 4 all bus distributor.

After each poll cycle, a longer clock pause is provided in which the counters of the individual bus distributors are set to 0 reset so that the next cycle can begin.

Switching on the common output signals

To turn on the above common output signals "Disarm", "Walk Test" and "Reset", the clock cycle is continued as follows, before the counters are reset:
65th-79th Clock: Safety distance
80.-95. Clock: signal "out of focus"
96.-111th Clock: signal "out of focus" + signal "walk test"
112th-127th Clock: signal "out of focus" + signal "walk test" + signal "reset".

The in o. G. Example of inevitable dependence of the signals is by choosing the order without any further logical Links compatible with how it works Intrusion detection systems.

Furthermore, the division has the consequence that ge in externally sharpened state one cycle remains limited to 64 bars, since in this case none of the three signals is required. Thus, the required time for the alarm detection mi kept nimal.

The outputs are each a volatile buffer upstream, which by Nachtriggerung the next Taktzy klus provides a static signal.

The clock line is used to trigger the counters installed in the bus distributors and to transmit the line states to the control unit 1 . The control line can block messages present on the clock line.

Hereinafter, the interrogation cycle will be explained in more detail with reference to the timing diagrams shown in FIGS . 5 to 7, in which S is a fault, R is an idle state and? a not he conceived condition are designated.

The following conditions apply:

• - The counters of the individual bus distributors are connected to the po positive edge of the clock signal.  
• - The counters of each bus distributor are provided with a lan gene level L reset on the clock line.
• - Disturbed lines report with level L on the clock line tung.
• - Non-disturbed lines report with level H on the Clock line.
• - The control line blocks with level H the messages on the Clock line.

Further, in Figs. 5 to 7 to simplify the Dar position, the numbering of the individual reporting lines ML by going from 1 to 64 and not selected according to the actual counting of the bus V01 to V16.

In the clock break, the clock output is high impedance. Through a Pull-down resistor in the control unit becomes the clock line to ground. The control line is during this Time at level H and thus blocks possibly pending state Messages to the clock line.

After the clock break, the clock line at level H and the Control line set to level L. All counters of the connected senen bus distributor V are now on 0001. Will now the clock high impedance output, there are two options:

• 1. The selected line is disturbed and reports a level L- Signal to the clock line so that the next clock follows can.
• 2. The selected line is at rest and reports a level H-Si gnal to the clock line, whereby it is blocked. In the In this case, the clock line becomes over the control line again unlocked, so that the next clock can follow.

In the same way, the lines are switched on and off asked until the first 6 bits of all counters back to 0 ste hen (= signaling line 1, bus distributor 0000). This condition is reached after 64 cycles. From here is either a clock break  inserted, or the clock continues to run, possibly pending Start or refresh output signals.

As can be seen from the timing diagram, the flan run ken of the signals on the control line always such that an over do not speak on the clock line in any case a rising Flank (level L → level H) can cause what an unbe intentional counting clock would correspond.

During the clock break are ge in the polling cycle collected data further processed.

To be by externally occurring electromagnetic disturbances be To counteract false alarms, the fault becomes was asked twice for a ML reporting line. This Doppelab ask with an intervening short time delay is made to shorten the detection time only if:

• - the reporting line ML is connected,
• - the reporting line ML is sharp,
• - the ML was previously at rest and
• - no alarm is stored on the ML reporting line.

Another source of false alarms would be a clock error. This would mean that an already recognized fault could be attributed to other reporting lines ML, since the current count no longer coincides with the reporting line ML to be interrogated. To counteract such effects, the query cycle is aborted immediately after detecting a fault, carried out a short reset counter and polled in the fast passage of FIG. 7 without interrogation of the other reporting lines ML the address of the fault again.

Fig. 5 shows the timing diagram for a normal query cycle.

In the clock break, the control line locks the access of the Kom parators in the bus distributors V to the clock line.

• 1 - The control line releases the reporting path, the clock line switches all counters from 0000000 to 0000001.
• 2 - The clock signal is removed, but the line remains at level H, since the reporting line 2 is at rest.
• 3 - To release the blocked clock line, the Control line again access to the clock line.
• 4 - The control line releases the message path again, the Clock line switches to the next signal line.
• 5 - The clock signal is removed again, but the clock line tion goes to level L, because at the reporting line 3 a fault is present. The control line does not intervene here because up Due to the fault on the reporting line 3 no level H through is switched.
• ,
• ,
• ,

Fig. 6 shows the timing diagram for the control of the common output signals. When queuing these common output signals is further indexed to their switching to the appropriate place, the control line again blocks the reporting path. A query does not take place here.

Fig. 7 shows the timing diagram for a fast passage after detection of a fault. In order to counteract false alarms, the query cycle is aborted immediately after detection of a fault, carried out a short counter reset and interrogated in rapid passage without interrogating the other reporting lines, the address of the fault again.

This is up to the reporting line X, which will be reviewed should, durchgetaktet and queried again. After that the fast passage is continued until the last bar. This only applies to reporting lines ML, which are the normal query  cycle connected, armed, not yet fed chert and were not disturbed before.

• 1 to 6 - The control line blocks the reporting path, the clock line device switches to the message line X without which had a fault during the normal polling cycle.
• 7 - The clock line switches to signaling line X, the control line tion releases the reporting path.
• 8 and 9 - The reporting line X is again detected as disturbed.

To ensure even processing of all reporting lines to get the fast passage to the last message line continued before the normal poll cycle again starts.

If 100% individual identification is waived, then Several bus distributors can provide the same address become. The programming of the connectable reporting lines 1, 2, 3 and 4 then apply to all bus distributors with the same Address alike, regardless of location to each other in Ver drahtungsbaum. In case of a fault on a reporting line is ever but not detectable, which the same addressed bus distributor has submitted the message. The number of connectable reporting lines ML increases by 4 each per bus distributor with address already assigned elsewhere.

Claims (8)

1. Signaling signal transmission system with
a control unit having a microprocessor, a memory device, an input / output unit and a display unit;
a plurality of addressable bus distributors for reporting faults to the control unit; and
a 4-wire connection system with power supply lines for connecting the control unit to the bus distributors, characterized in that
that the connection system comprises a control line, a Taktlei device and two lines for the power supply,
the supply of addressing clock signals to the bus distributors (V01 to V16) as well as the interrogation of messages from the addressed bus distributors (V01 to V16) take place via the clock line,
that blocking of the clock line by applied messages is prevented via the control line, and
in that the bus distributors (V01 to V16) can be interconnected in series and / or in parallel via the connection system ( 2 ) and connected to the control unit ( 1 ). 2. Signaling signal transmission system according to claim 1, characterized in that the control unit ( 1 ) on receipt of a fault message an immediate re-query the Busvertei ler (V01 to V16) performs. 3. Signaling signal transmission system according to claim 2, characterized in that the control unit ( 1 ) Runaway led renewed query is done in a quick pass. 4. Signaling signal transmission system according to one of claims 1 to 3, characterized in that each bus distributor (V01 to V16)
a counter for counting the applied clock signals,
an address decoder for outputting a strobe signal upon coincidence of the counter count with a set address,
a multiplexer for switching through respective signal line signals when the enable signal is applied,
a window comparator for evaluating the multiplexer output signal,
a switchable via the control line output stage for output from the comparator output signal to the clock line and
a latch for providing a static output signal of the bus distributor (V01 to V16). 5. Signaling signal transmission system according to claim 4, characterized in that a plurality of reporting lines ML can be switched on. 6. Signaling signal transmission system according to claim 5, characterized characterized in that connected to the multiplexer Detector lines ML via the 4-wire connection system individually are identifiable. 7. Signaling signal transmission system according to one of claims 1 to 6, characterized in that the transmission of further signals from the control unit ( 1 ) to the bus distributors (V01 to V16) by turning on a common bus address for all distributors (V01 to V16) address. 8. Signaling signal transmission system according to one of claims 1 to 7, characterized in that the signals for preventing of blocking the clock line on the control line against  in progress with the addressing clock signals on the clock line are.