DE4133594A1 - Digital data communications with direct memory access - using new DMA controller for efficient, effective and reliable communications in avionics systems - Google Patents

Abstract

The circuit is for digital data communications with direct memory access or DMA in a digital information communications system with an input/output or I/O processor. The process involves identifying a starting command word via the I/O processor (20) and initialising and activating a DMA controller (24) according to the identified start word. The I/O processor receives an interrupt generated by the I/O controller and finally performs an error check routine depending on the interrupt received. USE/ADVANTAGE - Esp. for effective, efficient and reliable digital data communications between the elements of an avionic system using a new and improved type of DMA controller.

Description

The present invention relates to digital information tion transmission system (DITS) and in particular a Ver drive and a facility for digital data transfer transfer between elements of an aviation electronics system stems using direct memory access.

For the transmission of digital data between elements aviation electronics systems are different Arrangements used. Fulfill typical such arrangements len the standards, which are in the ARINC specification 429-11 entitled "Mark 33 Digital Information Transfer Sy stem (DITS) ", published August 29, 1988 by Aero nautical Radio Inc. The ARINC spec  fication 429 facilitates compatibility between sy system interfaces of systems used by several ver different manufacturers. Through the ARINC Specification 429 are predefined general digi tal data word formats and coding examples created. In the ARINC-429 data system is used for the high speed a bit rate of 100 kilobits per second ± 1% and a selected bit rate for the low speed Operation in the range between 12.0 and 14.5 kg bits defined per second. Also the selected Nieder speed rate should be kept in the range of ± 1% will.

From US 42 80 221-A is a digital data communication known system that is a data source, a sources interface and a digital data bus for the over carrying coded information from the data source to one or more recipients, each with an Emp have catcher interface, contains. The sources Interface can be adjusted so that the An Rise and fall times of the signals on the data bus for controls a plurality of different frequencies. The Source interface and the receiver interface can with a high data rate of 100 kilobits per Second as well with a low data rate of 12 to 14.5 kilobits per second.

From US 42 98 959-A a DITS receiver is known with direct memory for a signal processor handle (DMA) can be created. The DITS receiver stores the data it stores over a plurality of ones receiving channels asynchronously, in the received Rei order directly in a random access memory (RAM) for DITS data. The first byte ID of the data word information  field that identifies the data source is called Address pointer used that defi the position in RAM on which the subsequent signal bits of the data word be saved. A common scanning network scans the Da received over each of the input channels so that samples with a duration of ge is less than that of a bit cell. The Ab tactile network creates at least one sample in which respective signal speed period both high speed as well as low speed signals are included. The sampled data is a Mul undergone tiplex operation, thereby in a serial Da tenstrom converted and either to an address register for the first byte or directly to the data RAM.

From US 46 46 324-A is a transmitter of a digital information mation transmission system known with the serial word ter of a given length with selected speed sent to a plurality of parals lel channels to be output. The digital transmitter is designed to provide test data for a flight parameter ter simulation from a database to the DITS receiver the US 42 98 959-A can deliver. The words for the serial transmission over the parallel output channels are selected, are repeated in succession in one The multiplexer entered the selected bits these words with fixed and variably adjustable Ge speeds to a shift register and signal memory combination for transferring the output different. The known from US 42 98 959-A and US 46 46 324-A Systems are suitable for broadcast data consisting of 32-bit Words exist and are spoken periodically and generally the instrument status and contain discrete signals.  

The conventional ARINC-429 file data transfer prototype koll uses polling ARINC 429 interface logic, d. H. an interrupt activated ARINC-429- Interface logic for common input / System one output processor (I / O processor) considerable additional processing time required. In the the arrangement is activated via an interruption I / O processor with every data word of the transmission under broken. With each interruption, a significant one becomes generates additional processing requirements, which for the I / O Processor is a huge burden. For on-demand Interface logic in which a continuous "Quit operation "between two devices the constant test the status of an interface transceiver calls for even more additional processing necessary. Due to the processing of the Da Part transfers become important tasks of the I / O process sors stopped. The frequency and duration of such Un Breaks are particularly in a data manager unit system (DMU system) problematic.

It is therefore an object of the present invention a new and improved control device for direct Memory Access (DMA) and a method by which an ef fective, efficient and reliable data transmission is possible to create.

It is another object of the present invention a DMA controller and a DMA method for a to create digital information transmission system with which an ARINC-429 file data transfer protocol in essentially independent of an input / output pro processor (I / O processor) can be implemented.  

It is another object of the present invention a system and method for an ARINC-429 receiver to create control with which the disadvantages ent speaking systems and methods of the prior art can be eliminated.

According to the invention, these tasks are performed by a DMA Control device and a method for digital data transmission in a digital information transmission system solved with an input / output processor. First, the I / O processor issues a start command word identified. Because of the identified start command words becomes a controller for direct storage Access (DMA) initialized and activated by the I / O processor fourth. After the transfer of all intermediate data words ter of the data record is a Un Break created and entered into the I / O processor. Due to the interruption received during the data receive operation, the I / O processor completes eating error checking routine. This allows the I / O Processor do other tasks while the DMA Control device transfers the individual records where at the I / O processor after receipt or transfer interrupted each complete data record becomes.

Other objects, features and advantages of the invention are in the subclaims that relate to special aus relate to embodiments of the present invention give.

The invention is based on a preferred Embodiment with reference to the drawings he closer purifies; show it:  

Fig. 1 is a block diagram of a digital ARINC-429 information transmission system according to the invention, which is used for file transfer based on DMA ver;

FIG. 2 shows a detailed block diagram of the arrangement of a data management unit (DMU) of the digital ARINC-429 information transmission system according to the invention from FIG. 1;

Fig. 3 is a flowchart for explaining the logical steps which are carried out by the input / output processor of the digital ARINC-429 information transmission system according to the invention from Fig. 1 when a file is received; and

Fig. 4 is a flow chart for explaining the logical steps which are carried out by the input / output processor of the digital ARINC-429 information transmission system according to the invention from Fig. 1 when sending a file.

In Fig. 1, a block diagram of a generally designated by the reference numeral 10 ARINC-429 information transmission system is shown, which has a structure according to the Invention. The ARINC-429 system 10 comprises, as primary components, an ARINC-429 transceiver 12 , a data management subsystem 14 (DMU subsystem) which is functionally coupled to the transceiver 12 , a memory 16 such as a static random access memory (SRAM) for storing data and status information and a data bus 18 for bidirectional communication between the transceiver 12 , the DMU subsystem 14 and the SRAM 16 . The DMU subsystem 14 includes an input / output processor (I / O processor) 20 , an interrupt controller 22 , a direct memory access controller 24 (DMA controller), a DMA control logic 26 , and an error handling logic 28 and the associated ARINC-429 transceiver 12 . The primary function of the DMU subsystem 14 includes the collection and monitoring of various data generated on the aircraft. The architecture of the DMU subsystem 14 is based on the use of a plurality of processing elements that are resident on a single system bus and communicate with the I / O processor 20 . The I / O processor 20 uses ARINC 429 standard serial data links to other aircraft systems such as the input / output element 30 shown .

The format defined by the ARINC-429 standard for the di gital file data transfer is under records Splits. Each record contains 1 to 126 intermediate dates words, the initial word preceding the data consequences. Each record in the file is as follows Using the ARINC-429 file data transfer pro tokolls transmitted consecutively: a station that which has data to be sent to a recipient on a bus that connects it to this receiver, a request to send (RTS) the initial word. The Recipient replies to one for the opposite Data flow provided, separate bus with a Sendebe riding feedback (CTS). Then the transmitter sends that Data previous start word. That preceded the data The beginning word conveys the number of intermediate sent in the following data record transfer data words. After the start command and start ant words between the sender and the receiver  the data record transfer by the transfer of the Zwi human data words continued, followed by an error Exam final. The recipient processes the mistake Exam final and ends in the case where No errors occur during the transfer process a word to the broadcaster regarding the proper Da transmission (ACK). On the other hand, if mistakes are made the receiver sends a word to the sender regarding incorrect data reception (NAK). The ACK or NAK confirmation from the recipient becomes internal half a predetermined time interval of about 50 milli seconds after the error check completion word expected.

According to the invention, when using the ARINC-429 data transfer protocol, the processing requirements for the I / O processor 20 for large data files that are transferred between the DMU subsystem and other aircraft systems such as the storage unit 30 based on a disk storage device, minimized. The conventional polling protocol or interrupt activated protocol between the I / O processor 20 and the ARINC 429 transceiver 12 is used during the transmission of the initial command words and initial response words prior to the transmission of the intermediate data words of a record. After a predefined command word, such as the initial word preceding the data, has been sent, the I / O processor 20 enables the DMA controller 24 to operate to transfer the data set. Each of the data words is transferred quentiell se, wherein the DMA controller 20 performs the data transmission irrespective of the E / O processor 20th Upon completion of the data set transfer, the DMA controller 24 provides an interrupt to the I / O processor 20 via the interrupt controller 22 . Then the I / O processor 20 performs the final error checking steps that complete the transfer. Both the sending and the receiving of the data is carried out by the DMA controller 24 .

For the transceiver 12 , a conventional ARINC-429 transceiver on an integrated circuit chip that includes a transmitter and at least one receiver can be used. The ARINC-429 transceiver 12 in the DMU subsystem 14 provides the I / O processor 20 with a single 8-bit read / write channel. Because a complete ARINC-429 word is 32 bits in length, the DMA control logic 26 enables four 8-bit DMA operations for each transfer of a 32-bit ARINC-429 data word. The required DMA control logic 26 can be reduced in complexity to a transceiver with a 16-bit channel or eliminated by using a transceiver with a 32-bit channel. In the DMA control logic 26 and in the interrupt control device 22 , a receiver logic signal is input via the line labeled RCVR HIT, which corresponds to a logical "OR" of the data transmission block ready bits of all receivers of the transceiver 12 . A transmitter logic signal that returns incorrectly when the first byte of the next frame is loaded into a FIFO register of transceiver 12 is sent to the DMA control logic 26 and the interrupt controller via the XMIT-MT designated data line 22 entered. Data transfer requests from the DMA control logic 26 are input to the DMA controller 24 via a line labeled DMA REQ (S).

Error handling logic 28 performs an error check in conjunction with DMA control logic 26 . An error condition is identified by the error handling logic 28 when the number of intermediate data words transmitted is less than a number incorrectly specified from the initial word preceding the data. Error handling logic 28 then generates an interrupt to avoid an unprogrammed stop of DMA controller 24 while I / O processor 20 is performing other tasks. The DMA control logic 26 provides a control signal for the error handling logic 28 via the line shown in dashed lines and identified by SSM VALID, with which it can scan the SSM bits on the data bus 18 . The error handling logic 28 monitors the SSM data bits 30 and 31 of the sign / status matrix, which are set in such a way that a data word can be uniquely identified: if they are set to (01), for example, they are extracted from the command / Answer initial words are identified while a data word is identified from the error check completion word when set to (10). If SSM data bits do not have a predefined value, such as a low logic level (00), in the further course of the DMA data transmission, the error handling logic 28 generates an error interruption. The error interruption generated is input to the I / O processor 20 via a line designated ERROR INT via the interrupt control device 22 . From the I / O processor 20 , an error confirmation signal is entered into the error handling logic 28 via a line designated ERROR NAK. Otherwise, I / O processor 20 can perform all of the conventional error checks for the received data set.

FIG. 2 shows an arrangement in which two disk storage units 30 are connected to the DMU subsystem 14 via an interface. Two sets of differential ARINC-429 signal lines, designated MDDU IN, PDL IN and MDDU OUT, PDL OUT, provide bidirectional data transmission via the ARINC-429 transceiver 12 of the DMU subsystem 14 . The static random access memory SRAM 16 contains an assigned transmit XMIT data buffer and a receiver RCVR data buffer for buffering sequential data words in received or transmitted data records. From the DMA control device 24 , ARINC-429 read, ARINC-429 write and ARINC-429 control signals are transmitted via a standard bus control logic 31 via a line designated 429-XCVR-RD / WR / CS-SI GNALE entered in the transceiver 12 .

As shown in FIG. 2, the DMA controller can support 24 various commercially available microprocessors with standard features, such as a highly integrated 80C186 16-bit microprocessor manufactured and sold by the Intel Corporation of Santa Clara, California , be used. The integrated features of the 80C186 microprocessor include two independent high-speed channels 0 and 1 for direct memory access (DMA), a programmable interrupt control device, three programmable 16-bit timers, a bus interface unit, a programmable memory and peripheral chip selection logic programmable control registers. While a single DMA channel can be programmed either for reception or for the transmission of data functions of the DMA control device 24 , one of the DMA channels 0 or 1 of the 80C186 DMA control device 24 is advantageously programmed for reception, while the other channel is being programmed to send data. DMA channels 0 or 1 enable full duplex operation. Each of the DMA channels 0 and 1 contains a plurality of registers, which are denoted with SOURCE ADDRESS, DESTINATION ADDRESS, TRANSMISSION COUNT and CONTROL REGISTER and are provided with the reference symbols 36 and 38, respectively.

Error protection logic EPLD 39 includes control word detection logic 40 which determines that the number of data words received is less than the number programmed in the TRANSMISSION COUNT register of the DMA control register 36 . The control word recognition logic 40 monitors the SSM data bits 30 and 31 of the sign / status matrix, which uniquely identify the data word in the command / response initial words and the error check completion word. If the SSM data bits do not have the predefined low logic value (00) in the further course of the DMA data record transmission, an error interruption is generated by the control word recognition logic 40 . The generated interrupt is entered into the I / O processor 20 through the interrupt controller 22 over a line labeled RECORD ERROR.

An ARINC 429 readout counter 42 and an ARINC 429 versing counter 44 perform the function shown in FIG. 1, DMA control logic 26 out to 12 executed for each of the ARINC 429 transceivers 32-bit ARINC 429 data word transfer to enable four 8-bit DMA transactions. The ARINC 429 readout counter 42 can provide a signal for the control word recognition logic 40 with which the SSM bits 30 and 31 of the last byte of each data word transmission are sampled.

Via a line labeled ANY RCVR HIT, a receiver logic signal is input into the EPLD 39 , which corresponds to a logical "OR" of the frame ready bits of all receivers in the transceiver 12 . The individual frame providing schaftsbits of each of the two receivers of the broadcast receptions and seminars gers 12 are inputted through a pair of lines which are designated MDDU HIT and PDL HIT, in the interrupt control means 22nd A transmitter output signal, which changes its logic level when the first byte of the next frame is loaded into a FIFO register of the transceiver 12 , is sent to the EPLD 39 and the interrupt controller 22 via a line labeled XMIT EMPTY entered. Via a line designated DMA-RQ 0 or DMA-RQ 1 , data transfer requests are entered into the DMA control device 24 by the byte readout counter 42 and byte read-in counter 44, respectively.

If the ARINC-429 transceiver 12 of the DMU Untersy stems 14 is to be used to send a file, the DMA channel 1, the DMA controller 14 from the I / O processor 20 is initialized to the the memory 16 to Transceiver 12 to move data. The initialization of channel 1 of the DMA control device 24 comprises the setting of the DMA register 38 . The DMA source pointer is set to the address of the first record in memory 16 , while the destination pointer is set to the ARINC-429 transceiver 12 . The size of the data record is set in a suitable DMA control device register (TRANSMISSION COUNT) and a checksum word is arranged at the end of the data record and is transmitted after the transfer of the data record words. Then the transmission of the data file record begins with the blocking of the DMA controller 24 and the release of the transmitter and receiver interruptions of the I / O processor 20 . Then the command / response initial words such as RTS and CTS and the words preceding the data are sent out. Then the interruption of the I / O processor 20 is blocked by the transmitter 12 and an interruption is activated by the DMA control device 24 . The DMA data transfer process is then activated so that it can be carried out in synchronism with the transmitter of the transceiver 12 with the DMA controller 24 . When the transmitter XMIT buffer of the transceiver 12 is empty, the next 32-bit word is transmitted from the DMA controller 24 to the transmitter XMIT buffer to be output. In the course of this DMA data record transfer, the I / O processor 20 is free to carry out other tasks. When the DMA record transfer is complete, the DMA controller 24 interrupts the I / O processor 20 , which then verifies the correct ACK / NAK response from the receiver within about 50 milliseconds. This process is repeated until the data file transfer is complete. If the ARINC-429 receiver interrupt persists throughout transmission, the I / O processor 20 can intercept any error messages from the receiver, such as the final ACK / NAK message after each record.

If the ARINC transceiver 429 12 of the DMU Untersy stems 14 is used for receiving a file, the DMA channel 0 of the DMA controller 24 initializes the I / O-Pro cessor to data from the transceiver 12 to move to memory 16 . This includes setting the register 36 including setting the DMA source pointer to the transceiver 12 and setting the determination pointer to the memory 16 . The data set size is set in a suitable DMA controller register after this information has been received in the initial word preceding the data. The reception of the file data record begins with the RTS word from the transmitter of the transceiver 12 . First, the DMA controller 24 is locked while transmitter and receiver interrupts are activated. Using this interrupt interface with transceiver 12 , the initial command / response transactions, such as RTS / CTS initial words and initial data preceding the data, are handled. At closing, the interruption of the I / O processor 20 is blocked by the receiver of the transceiver 12 and an interruption is activated by the DMA controller 24 . Then the DMA data transfer process is enabled to continue by the DMA controller 24 synchronized with the transceiver 12 receiver. For example, if the receiver RCVR buffer of the transceiver 12 is full, the 32-bit word is transferred to the SRAM memory 16 by means of a direct memory access from the DMA controller 24 .

During the receive function, the SSM bits are sampled by the error protection logic 39 to determine whether a non-data word has been received using the DMA. When the originally be from file source riding asked and in the receive DMA word counter 42 program-optimized word count does not coincide with the actual number of words received or when a unerwarte tes Datensatzendwort is (non-data word) is received, an error is detected. It should be noted that this error function is only applicable when the DMA controller 24 receives a file. The error detection when sending a file is monitored by the ARINC-429 receiver. If the receiving device detects an error in the transmitted data, an error NAK is sent back for this data record.

As the DMA record transfer continues, the I / O processor 20 is free to perform other tasks. When the DMA record transfer is complete, the DMA controller 24 interrupts the I / O processor 20 . Then the I / O processor 20 rewrites the interrupt log relating to the receiver of the transceiver 12 and executes the final error checking routine. I / O processor 20 then sends or receives the correct ACK / NAK response within about 50 milliseconds. This process is repeated for each data set until the file transfer is complete.

In Fig. 3, a flowchart is shown, which serves to explain the logic steps performed by the I / O processor 20 for a file reception function. The subsequent steps begin, as shown, at block 300 with a start command word received from I / O processor 20 and identified at block 302 . Then, in block 304 , the DMA controller 24 is initialized and activated by the I / O processor 20 based on an identified start command word in block 302 . Then, when the I / O processor 20 receives an error interrupt as shown in block 306 , an error NAK is sent by it, as indicated by block 308 . On the other hand, if at block 306 the I / O processor 20 does not receive an error interrupt, the DMA controller 24 inputs a complete record interrupt to the I / O processor 20 , followed by the transfer of all intermediate data of the complete record as by block 310 is shown. Then, the I / O processor 20 executes a final error checking routine based on the complete record interruption received in block 310 , as indicated by block 312 . Finally, in block 314, an ACK or NAK message corresponding to the particular data file transfer operations is sent to the I / O processor 20 .

FIG. 4 shows a flow chart which serves to explain the logic steps carried out by the I / O processor 20 for a data transmission function. The successive steps begin in block 400 with a ready-to-send command word received from I / O processor 20 that is identified in block 402 . The DMA control device 24 is initialized and activated, whereupon, based on the ready-to-send command word identified in block 402 , a start command and a data record are transmitted by the I / O processor 20 , as shown by block 404 . If an unexpected interrupt is subsequently received by the I / O processor 20 in block 406 , an error processing routine is executed in block 408 by the I / O processor 20 . Then the successive operations return to block 402 to retransmit the record. On the other hand, if, in block 406, the I / O processor 20 does not receive an unexpected interrupt, the I / O processor 20 will identify a complete data record interruption from the DMA controller 24 , whereupon all intermediate data words of the complete data set will be transmitted, as by the Block 410 is displayed. Then, the I / O processor 20 verifies an ACK message in block 412 based on the full record break sent in block 410 . If no ACK message is received within a predefined time interval of approximately 50 milliseconds, the sequential operations return to block 402 to retransmit the record. On the other hand, on the basis of an ACK message verified in block 412, the DMA control device 24 is set to the next data record. Subsequently, the successive steps for the transmission of the next data record are repeated by returning to block 402 .

Although the invention has been described with respect to the details of it refined embodiment has been described it is not intended that these details limit the scope of the Invention, which is defined by the claims, limit.

Claims (17)

1. A method for digital data transmission in a digital information transmission system (DITS) with an input / output processor (I / O processor) ( 20 ), characterized by the steps
the I / O processor ( 20 ) identifying a start command word;
initializing and activating a direct memory access controller (DMA controller) ( 24 ) by the I / O processor ( 20 ) based on the identified start command word;
the I / O processor ( 20 ) receiving an interrupt generated by the DMA controller ( 24 ); and
executing a final error checking routine based on the received interrupt from the I / O processor ( 20 ). 2. The method according to claim 1, characterized by the step of successively transmitting inter mediate data words by the DMA control device ( 24 ) due to the initialization by the I / O processor ( 20 ). 3. The method according to claim 2, characterized in that
each of the successively transmitted intermediate data words contains 32 bits and
four 8-bit bytes are transmitted sequentially for each of the successively transmitted intermediate data words. 4. The method according to claim 2, characterized in that
a data record contains a predetermined number of intermediate data words and
the interruption is generated by the DMA control device ( 24 ) due to a transfer of the data record. 5. The method according to claim 4, characterized in that
a data file contains a plurality of data records and
the steps mentioned are carried out successively for each of the plurality of data records. 6. The method according to claim 2, characterized in that the step of sequential transmission of the intermediate data words by the DMA control device ( 24 ) includes the step of scanning at least one predetermined data bit in order to identify an error condition. 7. The method according to claim 6, characterized in that
the bits of a given sign / status matrix (SSM) are scanned and
the steps of generating an error signal based on a predetermined sample value of the sampled SSM bits and entering the generated error signal into the I / O processor ( 20 ) are provided. 8. The method according to claim 7, characterized in that
each of the sequentially transmitted intermediate data words contains 32 bits,
for each of the sequentially transmitted intermediate data words, four 8-bit bytes are sequentially transmitted and
the SSM bits are sampled based on a predetermined 8-bit byte of the four transmitted 8-bit bytes. 9. The method according to claim 1, characterized in that the step of identifying a Startbe missword by the I / O processor ( 20 ) ent ent either sending or receiving a data word beginning by the I / O processor ( 20 ) contains. 10. The method according to claim 1, characterized in that the step of initializing the DMA control device ( 24 ) by the I / O processor ( 20 ) based on the identified start command word contains the following steps:
Identify the number of intermediate data words, and
Set a value corresponding to the identified number of intermediate data words in a transfer count register ( 42 ). 11. The method according to claim 10, characterized by the steps
setting a data source address;
setting a data destination address; and
activating the DMA controller ( 24 ). 12. Device for digital data transmission in egg nem digital information transmission system (DITS), characterized in that
direct memory access control means ( 24 ) ( 24 ); and
an input / output processor (I / O processor) ( 20 ), which is connected to the DMA control device ( 24 ), is provided,
the I / O processor ( 20 ) includes means for identifying a start command word received from it and means responsive to the identified start command word to initialize the DMA controller ( 24 );
the DMA controller ( 24 ) means responsive to initialization by the I / O processor ( 20 ) to transfer a record containing a predetermined number of intermediate data words, and means for generating an interrupt and for inputting the Interruption in the I / O processor ( 20 ) summarizes; and
the I / O processor ( 20 ) comprises a device ( 28 ) with which a final error checking routine is carried out due to the received interruption with respect to the transmitted data record. 13. Device according to claim 12, characterized by an error handling logic device ( 28 ) for sampling at least one predetermined data bit in the intermediate data word in order to identify an error condition. 14. The device according to claim 13, characterized in that
bits of a predetermined sign / status matrix (SSM) are sampled by the error handling logic device ( 28 ) and
means for generating an error signal based on a predetermined sample value of the sampled SSM bits and means for inputting a generated error signal into the I / O processor ( 20 ) are provided. 15. The device according to claim 12, characterized in that the DMA control device ( 24 ) contains a micro processor device. 16. The device according to claim 12, characterized in that the DMA control device ( 24 ) for the transmission of a data record contains an ARINC-429 transmit / receive device ( 12 ). 17. The device according to claim 16, characterized by a control logic device ( 26 ) for the sequential transmission of a predetermined number of data bytes contained in each of the intermediate data words.