DE4121863C2 - Method and arrangement for monitoring and avoiding an overflow and / or emptying of a buffer store - Google Patents

Description

A buffer memory is known from DE 26 54 070 C1 is used in communication systems.

The overview circuit diagram of a digital signal multiplex device DSMX140 / 565 is also known from the magazine "telcom report", Special Multiplex- und Linieneinrichtung, 10 (1987) March, pages 57 to 61, Figure 1. This contains a send and receive insert, each with an F2 interface with a buffer memory.

On the transmission side, received plesiochronous digital signals in the buffer memory are adapted to the bit rate and the structure of the pulse frame using a positive pulse stuffing method. The buffer memory itself determines whether a fill or stuff bit is to be displayed instead of a data bit at a defined position in the frame by a control circuit for fill or stuff information monitoring the read-in and read-out address. While the plesiochronous data stream is being continuously written into the buffer memory, the readout is "stuttering" because the readout clock is stopped at the times when additional information and filler or stuffing bits have to be inserted into the frame. Figure 3 shows that there was always a stand between a read-in address, which is determined by a read-in address counter, and a read-out address, which is defined by a slower read-out address counter, to be kept.

At the receiving end of a digital signal connection the plesiochronous data from four from the multiplex signal Channels recovered. In a "buffer memory" block  if filling or stuffing information bits are evaluated, a Read gap clock is formed and becomes a continuous out generated reading pulse.

There is a monitor for a possible memory overflow intended. So far, however, one has been content with one fixed predetermined distance between a read-in and a Read address in a specific, roughly rasterized sequence to recognize.

From semiconductor circuit technology, Tietze u. Schenk, jumper Verlag, 9th edition are on pages 285-288 controls described for memories in which the read pulses and the readout pulses are counted. By subtracting the The fill level is determined by meter readings. In the same teaching book is described on pages 610 and 611 as one Subtraction by adding the two's complement can be carried out.

In US Patent 4,864,543, a FIRST-IN, FIRST-OUT- Memory described in which also input and Readout pulses are counted, compared and evaluated. In German comparison 2317687 makes this comparison in a buffer storage system continuously by one UP / DOWN counter.

The invention specified in claim 1 addresses the problem basic, continuous monitoring of the distance between To enable read-in and read-out addresses.

The advantages achieved with the invention exist in addition to Realization of such a continuous monitoring and Evaluation both in a quick display of an overflow or an emptying and in a quick request one Plugging or unblocking, or filling or a gap education in data to be stored, as well as in the possibility the threshold for such a request is adjustable design.

An advantageous embodiment of the invention is in the claim 2 specified, after which the threshold mentioned are set can.

An arrangement for performing the method according to the invention can be seen from claims 3 and 4.

An embodiment of the invention is in the drawing is shown and described in more detail below:

Show it:  

Fig. 1 shows an arrangement for performing the method according to the invention,

Fig. 2 is a binary decoding and evaluation device,

Fig. 3 is a table for explaining the method according to the invention,

Fig. 4 is a first pointer diagram for explaining the inventive method and

Fig. 5 shows a second vector diagram to explain the inventive method.

Fig. 1 shows an arrangement for performing the method according to the Invention with a read-in arrangement 2 , a read-out arrangement 17 , a buffer memory 16 and an alarming and control arrangement 9th

The read-in arrangement 2 contains a read-in clock binary counter 3 and a read-in address decoder 5 . The readout device 17 comprises a read-out clock binary counter 22, a readout address decoder 20 and a read-out multiplexer 18 to A switches 18 a to 18 d. The buffer memory 16 includes memory cells 16 a to 16 d. The alarm and control arrangement 9 contains a full adder 10 and a binary value decoding and evaluation device 12 . Further, optionally, a spike filter 24 a or Spike filter 24 b, 24 c and 14 d is provided. Fig. 2 shows the binary value decoding and evaluation device 12 with AND gates 25 to 29 and with OR gates 30 and 31 detailed.

The data to be received D1 are applied via an input 7 to the inputs of the memory cells 16 a to 16 d. Via an input 1 , the read-in clock TE arrives at the input of the read-in clock binary counter 3 , which counts binary from zero to seven. The counter readings are output via the outputs 4 a to 4 c both to the read-in address decoder 5 and to A inputs of the full adder 10 . The read-in address decoder 5 determines which of its outputs 6 a to 6 d each memory cell 16 a to 16 d is occupied.

The read-out gap clock TA is applied to an input 8 and thus to the input of the read-out clock binary counter 22 , the gaps of which outside the arrangement shown allow the additional information and fill or stuff bits to be recorded. From the read clock binary counter 22 outputs its binary counter readings via its outputs 21 a to 21 c to the read-out address decoder 20 and B inputs of the full adder 10 . The read-out address decoder 20 determines, via its outputs 19 a to 19 d, which switch 18 a to 18 d is closed in the read-out multiplexer 18 , and thus, from which memory cell 16 a to 16 d the data to be delivered D2 to the Exit 23 .

The full adder 10 adds the counter readings present at its A and B inputs and feeds the sum over its outputs 11 a to 11 c to the binary value decoding and evaluation device 12 without the carry at output 11 d. This gives an alarm signal AS when the overflow or emptying has taken place at the output 13 of the AND gate 27 according to FIG. 2 with a sum "111", with sums "001" or "000" at the outputs of the AND gates 25 or 26 and switching through the OR gate 30 a distance-to-small signal AKS to an output 14 a and with sums "110" and "101" at the outputs of the AND gates 28 and 29 and switching through the OR gate 31 from a stand-too-large signal AGS at an output 15 a. In many applications, only either a distance-to-small signal AKS or a distance-to-large signal AGS is required. The type of addresses and the criteria for these signals will be explained later with reference to FIGS. 3 and 4.

The alarm signal AS occurs when the Einlesetakt-Binärzäh ler 3 and the Auslesetakt-binary counter 22 either coming from too small or too large a distance from each other.

Since 10 spikes in the form of incorrect addresses can arise in the full adder, the signals are only passed on if they are available for a sufficiently long time, namely longer than the longest running time, by the full adder 10 and the binary value decoding and evaluation device 12 . To achieve this, spike filters 24 a or 24 b to 24 d can be inserted.

Fig. 3 shows, among TE eight clock steps x and these repeating four other clock steps of the Einlesetakts x TE decimal (D) and to the right the associated read-in addresses at the terminals x 4 a to 4 c binary (B). Under TA are further time-Lich coincident with the clock steps of the Einlesetakts TE, clock steps y of the read gap clock TA decimal (D) in the reverse order and next to these, the corresponding one of read address y to the terminals 21 a to 21 c binary (B) represents. On the far right, the sum x + y at the outputs 11 a- 11 c is shown in binary (B) and decimal (D), the total formation taking place in the direction of the arrow. The sums x + y are used without the carry in brackets.

From the two framed number fields you can see that one Add each binary value x with the simultaneous binary value y or a defined leading or lagging binary value y results in an equal individual sum. The decimal sum "7" shows overflow or emptying, the decimal sums "0" and "1" impending emptying and the decimal sums "5" and "6" impending overflow.

Fig. 4 shows an outer ring with the binary values of y and x is an inner ring with the binary values. Both rings rotate at different speeds as a result of reading in EL and reading out AL. Corresponding to the upper framed field in FIG. 3, the selected binary value x is in FIG. 4 and the five selected binary values y are highlighted by a stronger border. The binary value y = "001" coincides with the binary value x = "011". The decimal sum is "4". This is not a reason for an alarm signal AS, a stand-too-small signal AKS or a distance-too-large signal AGS.

FIG. 5 shows a diagram corresponding to FIG. 4, but in which the rings are shifted against one another by one segment. The binary value y = "010" now meets the binary value x = "011". The decimal sum of both is "5", which means an impending overflow and triggers a distance-to-small signal AKS.

Claims (4)

1. A method for monitoring the degree of filling and avoiding an overflow and / or emptying of a buffer memory ( 16 ), the memory locations of which are filled with a read cycle (TE) and emptied with a read cycle (TA), the read cycles and the read cycles being counted and the difference between the number of cycles is determined, characterized in that
that the read-in cycles (TE) continuously in the order 0, 1,. . . x,. . . n are counted in binary form, the counts being read-in addresses at the same time,
that the read-out clocks (TA) continuously in the reverse order n,. . y,. . . 1, 0 are counted in binary, the counter readings being recoded into readout addresses,
that the read-in address is continuously added to the read-out counter in binary form,
that an overflow or a complete emptying is signaled in the case of a binary sum resulting from this addition without transfer of n,
that with a resulting binary sum without carry, which is equal to or less than a first decimal value a = 0, 1, 2,. . . is an impending emptying and
that for a sum equal to or greater than a second decimal value b <a; b = n-1, n-2,. . . an impending overflow is signaled. 2. The method according to claim 1, characterized, that with a sum without carry a = 0, 1, 2,. . . , the a distance of a + 1 clock steps between reading (EL) and reading (AL) before emptying "Distance-to-small signal (AKS) is signaled and that with a binary sum b <a; b = n-1, n-2,. . . , the a distance of n - b clock steps between reading (EL)  and readout (AL) before an overflow "Distance-to-large signal" (AGS) is signaled.   3. buffer storage arrangement for performing the method according to claim 2,
with a buffer memory ( 16 ) for storing data (D1) to be received, which are transmitted in pulse frames with time segments for useful and additional information,
with a reading arrangement ( 2 ) for the data to be received (D1), which is operated with a synchronous reading clock (TE),
with a readout arrangement ( 17 ) with read multiplexer ( 18 ) for data to be delivered (D2), which is operated with a locally generated readout clock (TA), and
with an alarm and control arrangement ( 9 ) for generating an alarm signal (AS), a distance-to-small signal (AKS) and a distance-to-large signal (AGS),
characterized,
that a read-in binary counter ( 3 ) and a read-in address decoder ( 5 ) connected downstream of the read-in arrangement ( 2 ) are provided,
that a readout clock binary counter ( 22 ), a readout address decoder ( 20 ) connected downstream thereof and the readout multiplexer ( 18 ) controlled by this are provided as readout arrangement ( 17 ) and
that as alarm and control arrangement ( 9 ) a full adder ( 10 ), the first inputs with the outputs ( 4 a- 4 c) of the read clock binary counter ( 3 ) and the second inputs with the outputs ( 21 a- 21 c) of the read clock binary counter ( 22 ) are connected, and a binary value decoding and evaluation device ( 12 ) are provided, the inputs of which are connected to the outputs ( 11 a- 11 c) of the full adder ( 10 ). 4. Buffer memory arrangement according to claim 3, characterized in that as a binary value decoding and evaluation device ( 12 ), a first AND gate ( 25 ), the first inverting input with the first output ( 11 a), the second inverting input with the second Output ( 11 b) and its third input is connected to the third output ( 11 c) of the full adder ( 10 ),
a second AND gate ( 26 ), the three inverting inputs of which are each connected to one of the three outputs ( 11 a- 11 c) of the full adder ( 10 ),
a first OR gate ( 30 ), the two inputs of which are connected to an output of the first ( 25 ) and second ( 26 ) AND gates, and whose output ( 14 a) is used to emit a distance-to-small signal ( AKS) serves
a third AND gate ( 27 ), the three inputs of which are each connected to one of the three outputs ( 11 a- 11 c) of the full adder ( 10 ) and whose output ( 13 ) is used to emit the alarm signal (AS),
a fourth AND gate ( 28 ), the first input of which with the first output ( 11 a), the second input of which has the second output ( 11 b) and the third inverting input of which has the third output ( 11 c) of the full adder ( 10 ) connected is,
a fifth AND gate ( 29 ), the first input with the first output ( 11 a), the second inverting input with the second output ( 11 b) and the third input with the third output ( 11 c) of the full adder ( 10 ) is connected, and a second OR gate ( 31 ) is provided, the two inputs of which are each connected to an output of the fourth AND gate ( 24-28 ) and the output ( 15 a) of the output of the distance-too-large Signal (AGS) is used.