DE4016173C2 - - Google Patents

Description

The invention relates to a bit error measuring device for determination the bit error rate of digital signal transmission links the preamble of claim 1.

Compared to an analog signal, one is digital over carried information against signal distortion and interference influences much less sensitive. However also digital signal transmission lines usually band limited and subject to fluctuating track damping. There ago it is necessary to transmit the digital signal by a line code so that, for example no equivalent share arises or the number of the maximum successive bits of equal value are limited.

A simple line code is the so-called NRZ code, the the property has that bits with value "1" also in the code the value "1" and bits with the value "0" also in Code have the value "0". Hence the after partly that the frequencies of the NRZ line code up to Fre go zero and on the other hand it can be difficult under certain circumstances is to regenerate the clock from the received NRZ signal, since with longer signal sequences of the same value, the tact formation in the received pulse train is missing.

By recoding an NRZ code, a so-called AMI Code are generated in which consecutive "1" values alternately sent as "+1" and "-1". About one longer period of time, the DC component of the Sig nals to zero. Due to the polarity change from original The continuous "1" values of the bit clock are regenerated  the. The AMI code also has the advantage that the receiver signal can be more easily checked for code violation. At Longer "0" sequences are also missing in the AMI coding the clock information.

A line code resulting from the AMI code, which as HDB-3 code does not have these disadvantages, since only three "0" elements appear in succession here can. With this code, longer "0" sequences are divided into blocks divided by four bits and sent, the fourth Bit is reversed in each case contrary to the AMI coding regulation.

Such an HDB-3 code is used in particular in the PCM multiplex systems used for voice signal transmission.

To determine the bit error rate of digital signal over transmission lines, e.g. B. microwave links or data lines, it is known to preselected data patterns over the transmission route to send and at the end of the transmission route the number of the disturbed data words with the total number of transmitted Compare data words. The measured value found represents the Bit error rate represents. This measured variable allows a statement about the quality of the transmission link.

A universal bit error measuring device that is suitable for different Line codes can be used and a clear clock return win with any data word is allowed in the Re gel very expensive. Known bit error measuring devices are sufficient therefore, the bit error rate at fixed clock frequencies to determine.

PF5 error measuring device from Wandel & Goltermann describes a bit error measuring device with a frequency  synthesizer, with its output frequency after frequency division the clock frequency of a measurement signal is determined. The measurement signal contains a selectable data word that is repeated on the test section is given. The one received at the end of the link The signal is then sent in accordance with the broadcast Checked signal or correctness. If the An alarm signal is given at intervals.

DE 29 35 535 discloses a device for synchronization the receive bit clock of a data receiver, in which one with N times the frequency of the nominal bit rate of the data signal oscillating crystal oscillator in phase through that Switching edges of the input signal can be controlled. To Further processing of the input signal is therefore carried out in each case the clock artificially generated in this way is phase-controlled derived from the quartz oscillator. It is not intended, the clock of the input signal itself for further processing prepare.

From DE 35 43 826 is a circuit arrangement for a digital locked loop usable phase locked loop known in which the phase of a voltage controlled oscillator using a phase detector with the phase of an input signal is compared and adjusted, in the event of occurrence malfunctions caused by switching a switching device the transfer clock as a phase comparison signal of the phase locked loop is derived from the oscillator of the phase locked loop and is used until after a certain time the Switching device back to the transmission clock of the input signal toggles for use in the phase locked loop.

DE 20 58 098 describes a method for checking an im  Short circuit according to the PCM process multi-channel terminal known, during which the short circuit test Sending out the synchronization characters on the one hand and receiving the synchronization character on the other hand via transmit or Receiving parts of different channel devices. Here is the test signal given over the transmission link recognizable and evaluable. How detection and This document cannot be deduced from an evaluation.

The invention lies on the basis of the aforementioned company publication based on the task of determining a bit error measuring device the bit error rate of digital signal transmission links specify that universal at a low cost at a large Clock frequency bandwidth can be used, different line codes as well as data words and both when closed as well as unidirectional transmission links is usable.

This object is achieved by the inven in claim 1 solved. Advantageous developments of the invention are specified in subclaims.

The invention enables bit error rate detection via a very large frequency range from, for example, 100 Hz to 50 MHz. A multitude of data words of the most varied can be used Codes with different data word lengths can be used. It is not, in particular, for unilateral transmission links required that the data word to be checked in the evaluation unit is known since according to a feature of claim 1 the received data signal to a feedback shift register is supplied in the successive data words with each other be compared cyclically for agreement. The  absolute knowledge of the transmitted data word is without Matter.

With a closed transmission path, the received one can Data word compared directly with the transmitted data word However, a cyclical comparison can also be made here successive data words are carried out. The clock signal of the received signal can either be directly from the incoming Signal can be derived or it can be missing Clock signal, e.g. B. when using certain transmission codes, or disturbed clock signal a receive clock from the transmission side clock signal used are derived.

In the case of unidirectional transmission links, is on the receiving side a PLL frequency synthesizer is provided, the off frequency remains until the possibility arises a clock alignment with the clock of the received signal results. In this case there is also the possibility of a Wide range of clock frequencies with a wide variety Use data words and data word lengths.

During a measurement, a random happens in the transmitter part of the device or specifically generated data word of certain length and speed via a subsequent encoder and suitable Given drivers on the transmission path to be evaluated and constantly repeated. The signal is received in the receiving section after passing through an input stage and a clock recovery one Decoder supplied, followed by a comparison stage is. Here the data words arriving one after the other are linked together compared. There will be discrepancies between the data words registered by a counter and on the number of transmitted Related data words. This can directly affect the bit error rate of the transmission link to be checked.

The invention is illustrated below by means of an embodiment explained in more detail. It shows:  

Fig. 1 is a block diagram of the device A according to the invention,

Fig. 2 is an illustration for generating a clock signal on the transmission side and

Fig. 3 is an illustration for the regeneration of the clock signal on the receiving side.

The device according to the invention shown in FIG. 1 has a computer 1 which serves to control the device, to specify the line code to be selected, the type and length of the data words used and the evaluation of the error signals.

A PLL frequency synthesizer 2 is provided, the frequency of which can be adjusted over a wide range. The frequency synthesizer 2 is a switchable divider 3 downstream, in which the frequency generated by the PLL frequency synthesizer can be divided down to the desired value. By using the PLL frequency synthesizer 2 and the downstream divider 3 , a frequency range of, for example, 100 Hz - 50 MHz can be covered without the need for different oscillator circuits. The bit rate used is determined by the selected frequency.

A measurement word is generated in a pattern generator 4 by the computer using a randomly generated data word or a test data word deliberately chosen by the user. The length of the data word can be freely selected. For better comparison with existing bit error measuring devices, data word lengths of 8, 10, 15 or 23 bits are preferred. The preferred word length depends on the desired clock frequency. The selected data word is clocked at the frequency derived from the divider 3 . The data word is repeated continuously, for example over several minutes up to 24 hours.

In the subsequent line encoder 5 , the pulse sequence generated is converted into the desired line code, e.g. B. an NRZ, AMI or HDB-3 code. This line code can be freely selected depending on the transmission path.

The line encoder 5 is followed by an output stage 6 , which may also consist of several parallel output stages, for example, and which contains adaptation devices, drivers and filters for the transmission link to be tested.

The signal given on the transmission link is switched back before preferably in a remote receiving station so that it can be returned to the bit error measuring device via a parallel transmission channel. The receiving part consists of an input stage 8 , in which the signal is additionally inverted. In the downstream pulse preparation stage 9 , a pulse of defined length is generated for each change of state of the data stream from "0" to "1". This pulse leads to a clock acquisition circuit 10 . The clock obtained from the received signal can be used directly for clock control of the downstream devices. However, since the number of the maximum permitted, depending on the following identical states, depends on the line coding used, it is not guaranteed in every case that a clock signal can be derived from the received signal. The invention therefore provides that the PLL frequency synthesizer used on the transmit side is additionally followed by a programmable divider 7 , which is triggered on the one hand by the clock signal output from the clock acquisition circuit 10 or the pulse processing stage 9 , but on the other hand, in the absence of this clock signal itself is retriggerable. In this case, the output signal of the programmable divider 7 is used to determine the subsequent reception stages. This means that a clock pulse is also available if there is no change of state in the data stream.

In the decoder 11 , the line coding made in the transmitting part is canceled. Furthermore, the signal is monitored for exceeding the maximum number of consecutive identical states. Every exceeding (AIS) is registered by the computer and displayed. If it is exceeded, the transmission channel is considered to be inoperative and the bit error rate measurement is interrupted for the time the AIS signal is present. Since it is generally not possible in this case for a clock signal to be obtained from the received signal, the device according to the invention nevertheless allows a clock signal to be made available and the possibility to generate a clear AIS signal. The decoder 11 is followed by a comparator 12 , which is designed in particular as a feedback shift register. Herein the two or more successive words are compared and checked for errors. The errors that occur are summed up in the subsequent counter 13 and transmitted to the computer 1 . The evaluation of the measurement result is preferably carried out in the computer 1 with a connected display unit. A power supply unit 14 is also shown, which is used to power the device.

The circuit arrangement shown in FIG. 2 shows the PLL frequency synthesizer 2 with a switchable divider 3 connected downstream. The PLL frequency synthesizer has a PLL control IC 18 which is quartz controlled. The control IC is followed by a variable frequency oscillator 19 , the output signal of which is given via a coupling stage 20 to the switchable divider 3 , which is designed as an 8-bit binary meter. After reaching the maximum count value, a pulse is given to the pattern generator 4 . The division rate of the divider 3 and the frequency of the PLL frequency synthesizer can be specified or set by the computer 1 used .

Fig. 3 shows the circuit arrangement for the regeneration of the clock signal on the receiving side. In the input stage 8 an invented signal is additionally formed from the received signal, the edges of which are slightly apart in time. If both signals are routed to the NOR gate 15 a, a pulse sequence arises at the output of this NOR which is determined by the time difference between the directly received and the inverted received signal. The clock frequency does not change. The pulse length depends on the gates used and the clock frequency. Is to compensate for this pulse length shift, the on off of the NORs gear 15 b applied pulse train also has two NOR gates 16 a and b delayed sixteenth Delayed and undelayed pulse trains are given to the NAND 16 c, at the output of which the pulse train that appears has approximately the same pulse length even at different clock frequencies.

At the PLL frequency synthesizer 2 , not only the switchable divider 3 of the transmission stage, but also a programmable divider 7 for the reception stage is connected. This consists in particular of a 2-stage counter with a division ratio of 1: 2 to 1: 16 in each case. A NOR 15 c is provided, through which the counter 17 a and 17 b are reset when the second counter 17 b overflows . The division ratio of the divider can be set by the computer 1 and depends essentially on the frequency of the PLL synthesizer used, which is, for example, 90-180 MHz.

The output of the first counter 17 a also leads to the input of the second counter 17 b. The output of the second counter 17 b leads to the NOR 15 c, on the other input of which the pulse sequence derived from the NAND 16 c of the input signal is applied. At the output of the NORs 15 c thus a pulse train arises, which can be determined both by the overflow pulses of the counter 17 b and by the pulses of the input signal. For example, if a pulse of the input signal at the output of the NORs 15 c generates a pulse, the counters are reset so that the pulse train running out of the counter 17 b is then synchronized with the pulse train of the output of the NAND 16 c, provided that the clock frequencies of the Divider 17 b originating pulse train and the clock frequency of the input signal essentially agree.

If no clock pulses are present in the received input signal due to the type of code or data word used, the pulse train at the output of NOR 15 c is determined solely by the clocks of counter 17 b until clock pulses are again present from the input signal.

The pulse sequence present at the output of NOR 15 c is fed to the subsequent receiver stages of the input part after inverting, for example to effect the decoding of the line code there or to determine the occurrence of inadmissible code length exceedances (AIS).

Instead of a 2-stage divider 7 , a multi-stage divider can also be used. The division rate determines the possible work area.

Since the frequency derived from the PLL synthesizer 2 is supplied to both the transmitting stage and the receiving stage, there are no clock frequency shifts between the clock frequency of the divider 7 and the clock frequency of the received pulse sequence, provided the division ratios of the divider 3 and the divider 7 are identical. In the event that the transmission frequency cannot be used, for example if a bit error rate is to be determined on a transmission link which is directed only on one side, the synthesizer frequency to be used is to be adapted to the clock frequency of the input pulses. It can be provided that the input pulse train controls the frequency of the PLL synthesizer. Since the frequency of the synthesizer remains fixed at a certain value until the clock frequency can be taken from the input signal again.

The entire circuit arrangement according to the invention can in EPLD technology can be manufactured, so that the circuitry build to a large extent in a manufacturer-related chip can be integrated. In addition to the economic advantage miniaturization can also be achieved in this way.

Reference symbol list

1 microcomputer
2 PLL frequency synthesizers
3 switchable dividers
4 pattern generator
5 line encoders
6 output stage
7 programmable dividers
8 input stage
9 pulse processing stage
10 clock recovery level
11 decoders
12 comparators
13 error counters
14 power supply
15 fast NOR
16 fast NAND
17 2-step programmable counter
18 PLL control IC
19 variable frequency oscillator
20 coupling stage
21 8-bit binary counter
22 8-bit digital multiplexers

Claims (4)

1. Bit error measuring device for determining the bit error rate of digital signal transmission links, with a PLL frequency synthesizer ( 2 ), with its output frequency after frequency division ( 3 ), the clock frequency of a measurement signal is determined, the measurement signal having a selectable data word, which repeats given on the transmission link is, and the signal received at the end of the transmission link is checked for agreement with the transmitted signal or correctness, characterized in that the clock of the received signal is regenerated by evaluating the signal transitions of the received signal and that in time ranges with missing signal transitions in the received signal the clock is obtained from the divided frequency or one of the further PLL frequency synthesizers ( 2 ) controlled by the clock frequency of the measurement signal, and that the data signal received at the end of the transmission path after the clock regeneration has a feedback shift register ( 12 ) is supplied, whereby successive data words can be compared with each other for agreement. 2. Bit error measuring device according to claim 1, characterized in that the output signal of the PLL frequency synthesizer ( 2 ) is supplied to a first switchable divider ( 3 ), the output signal of which determines the clock frequency of the measurement signal, and that the output signal of the PLL frequency synthesizer is also a second programmable Divider ( 7 ) is supplied, the phase position of which is determined by the phase of the clock frequency derived from the received signal at the end of the transmission path. 3. Bit error measuring device according to claim 1 or 2, characterized indicates that the selectable data word is optionally in the NRZ, AMI or HDB-3 line code on the transmission link becomes. 4. Bit error measuring device according to one or more of the preceding claims, characterized in that a device ( 11 ) for recognizing a signal sequence with a larger number of logical states in the received data signal than is permitted for a selected line code is provided, and that when such occurs Signal sequence the measurement of the bit error rate is interrupted.