DE3938153C2 - - Google Patents

Description

The invention relates to a circuit arrangement for testing of memory areas in a microprocessor, in particular an error bit check for a memory that has an area in which an ECC code (error checking and correction code) stored to correct a data error.

Fig. 1 shows schematically the structure of a conventional memory with error bit check function, as z. B. is described in JP-OS 62-1 20 699. A between a data input part 1 and a data output part 2 storage part comprises an information storage area 3 a and an ECC code storage area 3 b, in which the ECC code for the information previously written is stored. When information is written, it is stored in the information storage area 3 a, and also an ECC code is processed by an encoder 4 on the basis of the information registered, this ECC code then being stored in the ECC code storage area 3 b. When information is read out, a decoder 5 determines whether there is an error in the information, on the basis of this information and the ECC code, which are respectively read out from the information storage area 3 a and the ECC code storage area 3 b, and the decoder 5 generates a correction code in the event of an error. An error correction element 6 reverses an incorrect bit of this information in accordance with the correction code if there is an error in the information and outputs the information so reversed. Switches S 1- S 7 are each arranged between the above-mentioned units, so that the following individual operating modes are obtained when these switches are actuated:

• 1) In normal operation, in which
  S 1 = ON, S 2 = ON, S 3 = 1, S 4 = ON, S 5 = ON, S 6 = ON and S 7 = 1,
  the error correction member operates normally so that the corrected information is output.
• 2) When only the information storage area is used, where
  S 1 = OFF, S 2 = ON, S 3 = 1, S 4 = OFF, S 5 = OFF, S 6 = OFF and S 7 = 1,
  Since no error correction is carried out, a bit check (hardware function check) of the information storage area can be carried out.
• 3) When only the ECC code storage area is used, where
  S 1 = OFF, S 2 = OFF, S 3 = 2, S 4 = OFF, S 5 = OFF, S 6 = OFF and S 7 = 2,
  a bit check of the ECC code memory area can be carried out since no error correction is carried out.

The states of the aforementioned switches are preferred determined by being in an element before viewed information in a register (not shown) is written. To perform a normal operation too , the design must be such that the one shown in 1) Condition is realized.

From the publication DE-PS 36 03 926 is an ECC code correction a semiconductor memory element known. The peculiarity of this system is that it is possible Function tests of the data bit memory cell matrix and the Control bit memory cell matrix using a Perform error correction function. For this error correction however, it is necessary that the central processor unit (CPU) generates the test data bit pattern itself, what a time burden for performing peripheral Functions of the microcomputer represents.

If so far an error bit check for each memory area in the conventional microprocessor constructed in this way with error lerbit check function is performed, check data from a CPU (not shown) after linking different Data processed. Therefore, during the error bit check the CPU is used exclusively for this test. Furthermore, the error bit check for the ECC code must be saved range in addition to the normal tests performed error bit checking for the information store heritage rich and the error bit check for the freely designed Logic can be performed so that the total test time increases gets long, and the CPU must be overly heavy for these checks be used exclusively for a long time. Since further Test data must be repeatedly written to the memory, the storage life of the memory is shortened, what especially for memories with limited lifespan, such as such as non-volatile memory.  

In an article from IEEE Transactions on Computers, 10/86, pp. 862-870 addresses the problem of testing a RAM described and theoretically examined. Here too is spoken of an ECC code checking scheme, to whose Carrying out a check bit pattern generator with memory needed becomes.

In the document DE 36 34 352 A1 a method for Testing memory modules with any test pattern presented that the test time within a certain Cell group shortened by any bit pattern. A Another aspect of this document is the conversion of serial data information into parallel data information and the comparison of the parallel data information thus obtained with the data information in the memory.

In further training of the above-mentioned state of the art the invention has for its object a circuit arrangement to provide in a microcomputer which is the central Processor unit (CPU) relieved when an error bit check for a store is performed.

This object is achieved by a circuit arrangement to test a control unit Microcomputer containing (CPU) with a first device, which, controlled by signals supplied by the CPU, a plurality of predetermined types of test data patterns, the all bit configurations occurring in the memory area include, generated and cached, and a second device for determining whether the cached Test data samples with those after registered mail test data samples read out again in the memory area match and to detect an error bit at Mismatch.

The microcomputer according to the invention has an error bit check unit, the four due to a clock and a test signal Generates types of test data patterns that cover all bit configurations  include that occur in the storage area and in the error bit check can be used.

With the circuit arrangement according to the invention, the efficiency improved the error bit check of the memory be required to complete the test the time required is reduced and the CPU load at the time of the error bit check is significantly reduced. In addition, the registered life, in particular extended to a microcomputer with non-volatile memory will.

Further advantageous refinements of the present invention are specified in the subclaims.

Using the drawing, the invention is for example explained in more detail. Show it:

Fig. 1 is a block diagram showing the structure of a conventional memory with Fehlerbitprüffunktion;

Fig. 2 is a block diagram showing a Fehlerbitprüfschaltung for an ECC code storage area showing a microprocessor according to an embodiment of the invention;

FIGS. 3A-3D test pattern that are generated in the Fehlerbitprüfschaltung of FIG. 2.

The block diagram of Fig. 2 shows an error bit check circuit for checking bits in an ECC code memory area which is provided in a microprocessor. Although the description specifically refers to the error bit check for the ECC code memory area of the memory, a similar check can be provided for all areas in the memory including the information memory area. According to FIG. 2 (/ W R) temporarily stores check information 11 in a parallel in formations holding member 10 Ge b in an ECC code memory area 3 is written or read out therefrom due to a write / read control signal. In synchronism with a second clock signal (CK 2 ) 13 , a binary counter 12 supplies an address for an ECC code to be stored in the ECC code memory area 3 b. Flip-flops 15 a- 15 n are provided for the corresponding data signal lines connected to the ECC code memory area 3 b, and these flip-flops 15 a- 15 n operate synchronously with a first clock signal (CK 1 ) 14 . The outputs of these flip-flops 15 a- 15 n are sequentially connected to the D inputs of the following flip-flops. The output of a test data control circuit 16 is connected to the D input of the flip-flop 15 a. In this test data control circuit 16 , a first test signal (ST 1 ) 160 , which is normally fixed at an L or H level, is reversed as a result of the control performed by the first and second logic elements 162 and 163 and on the basis of a second test signal (ST 2 ) 161 . Coincidence determination elements 17 a- 17 n, the exclusive-OR elements and each provided for the signal lines, determine whether the output signals transmitted by the respective flip-flops match the signal read from the ECC code memory area 3 b. An error bit detection circuit 18 , which forms the OR stage, determines whether all of the output signals transmitted by the coincidence determination elements 17 a- 17 n are "0", and brings an error bit detection signal 18 a into a specific state when an error is detected. The number of flip-flops 15 a- 15 n and the coincidence determination elements 17 a- 17 n must of course be seen in accordance with the number of bits per line of the memory area. The control of the first and second test signals 160 and 161 and the write / read control signal 11 is carried out by a CPU (not shown), which serves as a control unit. In this state, the CPU does not generate a test data pattern for the error bit test. That is, the CPU only initializes the test conditions.

The memory bit check is a functional check of the memory as hardware, whereby it is checked whether each bit works correctly and whether the data entered is correctly saved. The bit status can change due to the influence of the surrounding bits. It is therefore necessary that the bit check be carried out in such a way that all possible bit configurations are checked. Test data according to four sample types corresponding to FIGS . 3A-3D are entered when the respective error bit test is carried out. The four types of test data patterns take into account all bit configurations that can occur. . The pattern of Figure 3A is designed such that arranged "1" and "0" alternately in succession in the row direction; in the pattern of Fig. 3B, "1" and "0" are alternately arranged in sequence in the row direction, and the order of "1" and "0" is set for each step; in the pattern of Fig. 3C, all bits are "0"; and in the pattern of Fig. 3D, all bits are "1".

If according to FIG. 2, the first clock signal is supplied to 14 and the levels of the first and second test signal 160 and 161 are fixed to "H", the Paralleldaten- holding member 10 are a- of the flip-flops 15 15 n, which are sequentially connected to each other , Test data "1010101 ..." or "0101010" supplied. The parallel data latch 10 stores the input signal of the flip-flops 15 a- 15 n temporarily. The binary counter 12 provides an address for write test data, so that test data stored in the parallel data holding element 10 are successively written into the ECC code memory area 3 b corresponding to the second clock signal 13 . If e.g. B. the relationship between the first clock signal 14 and the second clock signal 13 is seen before that the second clock signal 13 goes one step further when the first clock signal 14 goes from 15 a to 15 n, the configuration of the pattern is inscribed Check information as shown in Fig. 3A. In this state, the write / read control signal 11 of the parallel data latch 10 has a write mode.

If the control signal 11 for the parallel data holding element 10 after writing the test data in all areas in the ECC code memory area 3 b in the read mode R ge and then the second clock signal 13 is counted by the binary counter 12 , are in the ECC code memory area 3 b read out the written test data one after the other, starting with the initial write test information via the parallel data holding element 10 . The coincidence determination elements 17 a- 17 n determine whether the output signals coming from the flip-flops which are connected to one another and the read signal from the ECC code memory area 3 b match. If the two signals are not coincident, the output signal of the corresponding coincidence determiner takes the "1" level. Of an OR circuit bil Dende Fehlerbiterfassungskreis 18 detects the presence of abnormal bits on the basis of the presence of the input signal "1" and brings the Fehlerbiterfassungssi gnal 18 a in a certain state, if an error is detected.

If the arrangement is made so that the second clock signal continues after the first clock signal 14 has gone from 15 a to 15 n + 1, a bit check for the test data pattern according to FIG. 3B can be carried out. If the second clock signal 13 is allowed to continue after the change "H" / "L" of the first clock signal 14 and the second test signal 161 has been synchronized and entered, a bit test for the test data pattern can only consist of "0" or "1" according to FIGS . be performed 3C or 3D.

The above description was made specifically at Reference to the error bit check of the ECC code memory area in the memory of the two exemplary embodiments; but a similar error bit check for an informa  tion memory area or the total area of the memory including the two types of storage area mentioned be performed.

The microprocessor according to the invention is on a Ge provided housing or a chip and z. B. as an IC card or the like.

So even if a separate test data line for a Error bit checking is provided, an extension that is too large of the data bus can be avoided by only one serial test data line is provided.

Claims (6)

1. Circuit arrangement for testing the memory of a microcomputer containing a control unit (CPU)

• - a first device ( 16 , 15 ) which, controlled by signals supplied by the CPU (CK 1 , ST 1 , ST 2 ), generates and buffers a plurality of predetermined types of test data patterns which include all the bit configurations occurring in the memory area; and
• - A second device ( 17 , 18 ) for determining whether the temporarily stored test data patterns match the test data patterns read out again after being written into the memory area and for detecting an error bit if they do not match.

2. Circuit arrangement according to claim 1, characterized in that memory areas ( 3 b) are checked in which an ECC code is stored. 3. A circuit arrangement according to claim 1, characterized in that the first device for generating the test data pattern has a test data control circuit ( 16 ), the output of which is connected to the input (D) of a first flip-flop ( 15 a), the test data circuit ( 16 ) being a first supplied from the CPU signal (ST 1) further as a function of delivered signals (ST 2, CK 1) inverted. 4. Circuit arrangement according to claim 1, characterized in that the first device for temporarily storing the test data pattern has a plurality of flip-flops ( 15 a- 15 n), the outputs () of which are sequentially connected to the inputs (D) of the following flip-flops. 5. Circuit arrangement according to claim 1, characterized by a unit ( 10 ) for temporarily storing the generated test data pattern and for successively writing the test data pattern thus stored one line in the memory in the write mode and for successively reading out the test data pattern thus written from the line in the memory in the read mode . 6. Circuit arrangement according to one of claims 1 to 5, characterized, that the microcomputer is provided on an IC card is.