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DE3855274D1 - Botschafts-Fifo-Puffersteuergerät - Google Patents

Botschafts-Fifo-Puffersteuergerät

Info

Publication number
DE3855274D1
DE3855274D1 DE3855274T DE3855274T DE3855274D1 DE 3855274 D1 DE3855274 D1 DE 3855274D1 DE 3855274 T DE3855274 T DE 3855274T DE 3855274 T DE3855274 T DE 3855274T DE 3855274 D1 DE3855274 D1 DE 3855274D1
Authority
DE
Germany
Prior art keywords
control device
buffer control
fifo buffer
message fifo
message
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3855274T
Other languages
English (en)
Other versions
DE3855274T2 (de
Inventor
Martin Claude Lefebvre
Carmine Antonio Ciancibello
Youssef Alfred Geadah
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nortel Networks Ltd
Original Assignee
Northern Telecom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Northern Telecom Ltd filed Critical Northern Telecom Ltd
Application granted granted Critical
Publication of DE3855274D1 publication Critical patent/DE3855274D1/de
Publication of DE3855274T2 publication Critical patent/DE3855274T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • G06F5/14—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations for overflow or underflow handling, e.g. full or empty flags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/06—Indexing scheme relating to groups G06F5/06 - G06F5/16
    • G06F2205/062—Allowing rewriting or rereading data to or from the buffer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Multi Processors (AREA)
  • Time-Division Multiplex Systems (AREA)
DE3855274T 1987-10-14 1988-10-05 Botschafts-Fifo-Puffersteuergerät Expired - Fee Related DE3855274T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA000549274A CA1286421C (en) 1987-10-14 1987-10-14 Message fifo buffer controller

Publications (2)

Publication Number Publication Date
DE3855274D1 true DE3855274D1 (de) 1996-06-13
DE3855274T2 DE3855274T2 (de) 1996-09-19

Family

ID=4136650

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3855274T Expired - Fee Related DE3855274T2 (de) 1987-10-14 1988-10-05 Botschafts-Fifo-Puffersteuergerät

Country Status (7)

Country Link
US (1) US4873666A (de)
EP (1) EP0312239B1 (de)
JP (1) JP2702181B2 (de)
KR (1) KR890007284A (de)
CN (1) CN1012396B (de)
CA (1) CA1286421C (de)
DE (1) DE3855274T2 (de)

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US5551054A (en) * 1991-11-19 1996-08-27 Adaptec, Inc. Page mode buffer controller for transferring Nb byte pages between a host and buffer memory without interruption except for refresh
JP3049343B2 (ja) * 1991-11-25 2000-06-05 安藤電気株式会社 メモリ試験装置
US5323272A (en) * 1992-07-01 1994-06-21 Ampex Systems Corporation Time delay control for serial digital video interface audio receiver buffer
JP3057591B2 (ja) * 1992-12-22 2000-06-26 富士通株式会社 マルチプロセッサシステム
JP3229066B2 (ja) * 1993-04-21 2001-11-12 セイコーインスツルメンツ株式会社 半導体集積回路
US5487049A (en) * 1994-11-23 1996-01-23 Samsung Semiconductor, Inc. Page-in, burst-out FIFO
US5809268A (en) * 1995-06-29 1998-09-15 International Business Machines Corporation Method and system for tracking resource allocation within a processor
DE19529966A1 (de) * 1995-08-14 1997-02-20 Thomson Brandt Gmbh Verfahren und Schaltungsanordnung zur Resynchronisation einer Speicherverwaltung
US5717954A (en) * 1995-10-13 1998-02-10 Compaq Computer Corporation Locked exchange FIFO
US5555214A (en) * 1995-11-08 1996-09-10 Altera Corporation Apparatus for serial reading and writing of random access memory arrays
US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
US5887003A (en) * 1996-09-10 1999-03-23 Hewlett-Packard Company Apparatus and method for comparing a group of binary fields with an expected pattern to generate match results
US6003107A (en) * 1996-09-10 1999-12-14 Hewlett-Packard Company Circuitry for providing external access to signals that are internal to an integrated circuit chip package
US5881224A (en) * 1996-09-10 1999-03-09 Hewlett-Packard Company Apparatus and method for tracking events in a microprocessor that can retire more than one instruction during a clock cycle
US5867644A (en) * 1996-09-10 1999-02-02 Hewlett Packard Company System and method for on-chip debug support and performance monitoring in a microprocessor
US5974482A (en) * 1996-09-20 1999-10-26 Honeywell Inc. Single port first-in-first-out (FIFO) device having overwrite protection and diagnostic capabilities
US5956476A (en) * 1996-10-31 1999-09-21 Hewlett Packard Company Circuitry and method for detecting signal patterns on a bus using dynamically changing expected patterns
US5956477A (en) * 1996-11-25 1999-09-21 Hewlett-Packard Company Method for processing information in a microprocessor to facilitate debug and performance monitoring
US5881217A (en) * 1996-11-27 1999-03-09 Hewlett-Packard Company Input comparison circuitry and method for a programmable state machine
US6009539A (en) * 1996-11-27 1999-12-28 Hewlett-Packard Company Cross-triggering CPUs for enhanced test operations in a multi-CPU computer system
DE19654595A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US8686549B2 (en) * 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
DE19861088A1 (de) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
KR100301653B1 (ko) * 1998-08-14 2001-09-06 김영환 고속 엠티 플래그 발생기
US6374370B1 (en) 1998-10-30 2002-04-16 Hewlett-Packard Company Method and system for flexible control of BIST registers based upon on-chip events
JP2003505753A (ja) 1999-06-10 2003-02-12 ペーアーツェーテー インフォルマツィオーンステヒノロギー ゲゼルシャフト ミット ベシュレンクテル ハフツング セル構造におけるシーケンス分割方法
DE50115584D1 (de) 2000-06-13 2010-09-16 Krass Maren Pipeline ct-protokolle und -kommunikation
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) * 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
WO2003042811A1 (en) * 2001-11-13 2003-05-22 Koninklijke Philips Electronics N.V. Efficient fifo communication using semaphores
AU2003208266A1 (en) 2002-01-19 2003-07-30 Pact Xpp Technologies Ag Reconfigurable processor
DE10390689D2 (de) 2002-02-18 2005-02-10 Pact Xpp Technologies Ag Bussysteme und Rekonfigurationsverfahren
US20110161977A1 (en) * 2002-03-21 2011-06-30 Martin Vorbach Method and device for data processing
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
DE60304468T2 (de) * 2002-06-07 2007-03-15 Koninklijke Philips Electronics N.V. Spacecake coprozessor kommunikation
US7477649B2 (en) * 2002-07-17 2009-01-13 Lsi Corporation Active FIFO threshold adjustment
WO2004021176A2 (de) 2002-08-07 2004-03-11 Pact Xpp Technologies Ag Verfahren und vorrichtung zur datenverarbeitung
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
US7394284B2 (en) 2002-09-06 2008-07-01 Pact Xpp Technologies Ag Reconfigurable sequencer structure
JP2004246979A (ja) * 2003-02-14 2004-09-02 Fujitsu Ltd 半導体試験回路、半導体記憶装置および半導体試験方法
JP4700611B2 (ja) 2003-08-28 2011-06-15 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト データ処理装置およびデータ処理方法
CN100396052C (zh) * 2004-03-12 2008-06-18 华为技术有限公司 高可靠性的先入先出存储器及其实现方法
US7447812B1 (en) 2004-03-23 2008-11-04 Integrated Device Technology, Inc. Multi-queue FIFO memory devices that support flow-through of write and read counter updates using multi-port flag counter register files
US7870310B2 (en) * 2004-07-26 2011-01-11 Integrated Device Technology, Inc. Multiple counters to relieve flag restriction in a multi-queue first-in first-out memory system
US7523232B2 (en) * 2004-07-26 2009-04-21 Integrated Device Technology, Inc. Mark/re-read and mark/re-write operations in a multi-queue first-in first-out memory system
US7805552B2 (en) 2004-07-26 2010-09-28 Integrated Device Technology, Inc. Partial packet write and write data filtering in a multi-queue first-in first-out memory system
US8230174B2 (en) * 2004-07-26 2012-07-24 Integrated Device Technology, Inc. Multi-queue address generator for start and end addresses in a multi-queue first-in first-out memory system
US20060155940A1 (en) 2005-01-10 2006-07-13 Mario Au Multi-queue FIFO memory systems that utilize read chip select and device identification codes to control one-at-a-time bus access between selected FIFO memory chips
US20100180095A1 (en) * 2005-12-02 2010-07-15 Matsushita Electric Industrial Co., Ltd. Buffer control device and buffer memory device
WO2007082730A1 (de) 2006-01-18 2007-07-26 Pact Xpp Technologies Ag Hardwaredefinitionsverfahren
JP2011503733A (ja) * 2007-11-17 2011-01-27 トーマス リヒター リコンフィギュラブルな浮動小数点レベルおよびビットレベルのデータ処理ユニット
DE112008003670A5 (de) * 2007-11-28 2010-10-28 Pact Xpp Technologies Ag Über Datenverarbeitung
US8681526B2 (en) * 2008-07-02 2014-03-25 Cradle Ip, Llc Size and retry programmable multi-synchronous FIFO
CN116107795B (zh) * 2023-04-14 2023-07-14 苏州萨沙迈半导体有限公司 报错电路及芯片设备

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JPS58191043A (ja) * 1982-04-30 1983-11-08 Nec Home Electronics Ltd フア−ストイン・フア−ストアウトレジスタ制御回路
US4507760A (en) * 1982-08-13 1985-03-26 At&T Bell Laboratories First-in, first-out (FIFO) memory configuration for queue storage
FR2536200B1 (fr) * 1982-11-15 1987-01-16 Helen Andre Unite de stockage temporaire de donnees organisee en file d'attente
US4592019A (en) * 1983-08-31 1986-05-27 At&T Bell Laboratories Bus oriented LIFO/FIFO memory
JPS60262242A (ja) * 1984-06-08 1985-12-25 Matsushita Electric Ind Co Ltd Ｆｉｆｏ回路
US4694426A (en) * 1985-12-20 1987-09-15 Ncr Corporation Asynchronous FIFO status circuit

Also Published As

Publication number Publication date
EP0312239A3 (de) 1991-02-13
JP2702181B2 (ja) 1998-01-21
CA1286421C (en) 1991-07-16
KR890007284A (ko) 1989-06-19
JPH01129323A (ja) 1989-05-22
EP0312239A2 (de) 1989-04-19
CN1035382A (zh) 1989-09-06
DE3855274T2 (de) 1996-09-19
EP0312239B1 (de) 1996-05-08
CN1012396B (zh) 1991-04-17
US4873666A (en) 1989-10-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee