DE3814813C1 - Method and circuit arrangement for analog/digital conversion - Google Patents

Abstract

In a method for analog/digital conversion, in which the measurement quantity to be converted and a reference quantity with opposite polarity are supplied to an integrator, an integration cycle is formed by the fact that the measurement quantity is first applied to the integrator, the reference quantity is added at a controllable first time and, after a second time, the supply of the measurement quantity to the integrator is disconnected. The integration cycle is ended at a following zero crossing of the integrator output signal.

Description

The invention relates to a method and a Circuit arrangement for analog / digital conversion, the Measured variable to be converted and a reference variable with opposite polarity fed to an integrator an integration cycle is formed by that the measured variable is first applied to the integrator the reference quantity at a later first time switched on and the feed after a second point in time the measurand to the integrator is switched off, and wherein further at a subsequent zero crossing of the Integrator output signal of the integration cycle ended becomes.

In addition to a variety of other processes Analog / digital conversion, the so-called dual slope method known, in which the measured variable and a reference variable one after the other with opposite polarity Integrator are fed. From the time of Zero crossing that at the end of the integration of the If the reference variable is used, the measured variable can be concluded  will. Such analog / digital converters are common quite high demands regarding the resolution, the Conversion error, the conversion time and the Interference signal suppression set. An area of application for are very precise analog / digital converters for example weighing devices.

The dual slope method is often used, points out however some drawbacks. For example, the Time range in which the zero crossing can take place, relatively large, so that to achieve sufficient Quantization accuracy processing a large Value range is required. This also means a high clock frequency in relation to the repetition frequency of the Measurement. In addition, the measuring cycle is not constant, but rather depending on the measured variable. After all, there is only one relative small part of the entire measuring cycle as the actual measuring time available, so that statistical disturbances of the measurand (Noise, interference pulses) cannot be averaged sufficiently.

In a known analog / digital converter of this type (US 42 68 820) the reference variable is switched on in Depends on whether a given threshold of the Output voltage of the integrator is exceeded. Thereby will be the time range in which the zero crossing can be done, somewhat limited, but the measurement time is still dependent on the measured variable. It also affects number of switching operations dependent on the measured variable Accuracy, as recharging effects with every switching operation occur. Furthermore, in the known Analog / digital converter additional circuitry for a second comparator and the generation of the Threshold voltage required.

The object of the present invention is to provide a method for Analog / digital conversion and a circuit arrangement for performing this method indicate which of the aforementioned Do not have disadvantages if possible.

The method according to the invention is characterized in that that the first point in time is regulated in such a way that the Zero crossing a predetermined time after the Measured variable takes place. With regard to the circuitry, the task solved by the measures characterized in claim 5.

The method according to the invention enables in a simple manner a constant sampling rate. That is, the ratio of The number of parts and measuring time is almost optimal, what a digital signal processing of the measurement result is important. In addition, the method according to the invention can also advantageously be used a signal processor designed as a control unit and few additional components are carried out. Here are only three for the additional components Connections of the signal processor occupied. After all it is not necessary in the method according to the invention Integrator to zero after one integration cycle put.

There is a further development of the method according to the invention in that the value of the measurand from the last specified first time and the time of the last Zero crossing is calculated as soon as the zero crossing within a specified deviation from the specified Time. This will result in a quick output of the Measurement result enables, even if the control process is still is not fully completed.

Another development of the invention contributes to Reduction of quantization errors in that on At the end of the integration cycle, the supply of the reference variable to the integrator and then the existing one Output signal of the integrator until the beginning of the following  Integration cycle is maintained.

By those listed in the further subclaims Measures are further advantageous developments and Improvements to the invention specified in the main claim and circuit arrangements for performing the method according to the invention possible.

Embodiments of the invention are in the drawing represented with several figures and in the following Description explained in more detail. It shows

Fig. 1 is a block diagram of a circuit arrangement for implementing the method according to the invention,

Fig. 2 shows the course of the output voltage of the integrator in the known dual-slope method and in the inventive method,

Fig. 3 shows the profile of the output voltage of the integrator in the inventive method,

Fig. 4 is a Petri net, which describes the time and conditions of the conversion process,

Fig. 5 is a structural diagram of the essential technical control elements,

Fig. 6 shows the output voltage of the integrator as a function of the measured variable and

Fig. 7 shows a detail from FIG. 3.

Identical parts are given the same reference symbols in the figures Mistake.  

In the circuit arrangement according to FIG. 1, inputs 1 , 2 are provided for a measured variable and a reference variable. Since both quantities are usually present as a voltage, they are referred to below as measuring voltage Um and reference voltage Ur . The inputs 1 , 2 can each be connected to the input of an integrator 5 via a controllable switch 3 , 4 . Since integrator circuits are well known, no further description is given.

The output of the integrator 5 is connected to an input of a comparator 6 , the other input of which is supplied with ground potential which corresponds to the reference potential of the integrator. To control the switches 3 , 4 and to evaluate the output voltage of the comparator 6 , a digital control unit 7 is provided, the elements of which are known per se and which is programmed in a suitable manner to carry out the method according to the invention.

Fig. 2 shows the time course of the output voltage Ui of the integrator in the known dual slope method (dashed) and in the inventive method (solid). In the known method, the measuring voltage Um is integrated during a time period Tn starting at time t 0 . During this time the switch 3 ( Fig. 1) is closed. At time t 2 , switch 3 is opened and switch 4 is closed. Since the reference voltage Ur has an opposite polarity, the direction of integration changes. When the voltage Ui passes zero at the time t 4 , the integration process is ended, the switch 4 is opened and the magnitude of the measurement voltage Um is calculated from the time t 4 .

In the method according to the invention, the reference voltage Ur is already applied during the supply of the measuring voltage Um - for example at time t 1 . The result of this is that the difference between the two voltages is integrated between t 1 and t 2 , which results in a smaller voltage Ui than in the known method at time t 2 . As a result, the output value for the subsequent integration of the reference voltage Ur is significantly smaller, as a result of which the zero crossing takes place much earlier, namely at time t 3 .

In the method according to the invention, a new integration cycle can therefore begin immediately after time t 3 . Compared to the known method, it is obvious that the measuring time Tn , during which the magnitude of the measuring voltage is included in the measuring result, takes up a much larger part of a measuring period.

FIG. 3 shows the curve of the output voltage of the integrator in the method according to the invention, already shown in FIG. 2, on a larger scale, several times and time segments serving to explain the method according to the invention being designated as follows:

t 0 = start of integration of the measuring voltage Um (closing of switch 3 ),
t 1 = start of integration of the reference voltage Ur (closing of switch 4 ),
t 2 = end of integration of measuring voltage Um (opening of switch 3 ),
t 3 = actual value for the end of the integration of the reference voltage Ur ,
t 4 = setpoint for the end of integration of the reference voltage Ur ,
Tstell = actuating time of the controller,
Tn = integration time of the measuring voltage (fixed),
Tref = integration time of the reference voltage , which is dependent on the measured value,
Tist = actual time for an integration cycle ,
Tsoll = target time for an integration cycle and
deltaT = control deviation.

The measurement result is then:

Um = (Tref / Tn) * Ur

The Petri network shown in FIG. 4 describes the time conditions of the conversion process. The transitions at times t 0 to t 3 are time-critical, that is, the times are included in the measurement result. Of these transitions, however, only that which takes place at time t 3 is not determined by outputs from the digital control unit, but is dependent on the measuring voltage and on the respective time Tstell . A prerequisite for the accuracy of the measuring principle is that all transitions take place synchronously. This also applies to the interrupt triggered by the comparator at a zero crossing. However, the zero crossing itself is not isochronous, which results in a quantization error that will be returned to later.

After switching on the measuring voltage at t 0 , the switching on of the reference voltage is waited until Tstell has expired (time t 1 ). Thereafter, it is again waited until Tn has elapsed, whereupon the supply of the measuring voltage is switched off at time t 2 . At this time the comparator is also released, which triggers an interrupt at time t 3 when the output voltage of the integrator falls below the comparator threshold. A new value for Tstell is then defined, after which the next cycle can be started by applying the measuring voltage.

The structure diagram according to FIG. 5 illustrates the determination of the time Tstell by a control circuit. At 11 , the time T actual between the start of the integration and the zero crossing (t 3 ) is subtracted from the time T set . The control deviation deltaT obtained in this way is fed to an estimator 12 , which determines the value Tstell (n + 1 ) for the following integration cycle . This is fed to a quantizer 13 , at whose output Tstell (n + 1 ) is present in a relatively roughly quantized form. As a result of the following integration cycle, the value Tref (n + 1 ) is added to the value Tstell (n + 1 ) at 14 , so that a new actual value Tist is created. When carrying out the method according to the invention, the control loop need not be run through so often that Tist and Tset agree exactly. Rather, it is sufficient if Tist is within a predetermined range near Tsoll . For the subsequent determination of the measurement result, the time of the actual zero crossing is then used in addition to the times output by the digital control unit.

To illustrate the advantages of the method according to the invention, time diagrams of output voltages of the integrator for various measurement signals are shown in FIG. 6. The size of the respective measurement signal can be estimated at the initial slopes. The order of the reference numerals 21 to 30 was chosen with increasing size of the measuring voltage. While at low measuring voltages (especially curves 21 , 22 ) the reference voltage is switched on very late, so that - if at all - there is only a slight overlap between the two integration processes, the time t 1 is at large measuring voltages shortly after the start of the integration of the Measuring voltage. In the method according to the invention, it may even happen that the reference voltage is switched on simultaneously with the measuring voltage.

From Fig. 6 it can also be seen that largely independent of the measuring voltage, the zero crossing takes place in a narrow time window. In addition, the slope of the integrator output voltage during the zero crossing is large in relation to that in the dual-slope method, so that amplitude errors of the comparator are only insignificantly incorporated into measurement errors.

As already mentioned, the zero crossing is not isochronous. This results in a quantization error, which is illustrated with reference to FIG. 7. For this purpose, FIG. 7 shows an enlarged detail in the area of the zero crossing of the integrator output voltage. Tx is measured as the integration time, although the zero crossing is later by the quantization error qi , namely in the clock period following Tx . In known analog / digital converters using the dual slope method, the integrator is short-circuited in the following cycle, so that its output voltage goes to zero. This is intended to create initial conditions for the following integration cycle that are independent of the previous cycle. However, this is not entirely possible due to the dielectric absorption of the integration capacitor. This has the effect that, despite a short circuit, charges stored in the capacitor become noticeable in the next integration cycle.

According to a development of the invention, the Capacitor not short-circuited. It is just for that worried that until the beginning of the next integration cycle the capacitor's charge is retained. So that succeeds a carryover of the quantization residue to the following Integration cycle, with the quantization residue of Integration cycle integrated up to integration cycle and  accuracy of the measurement is increased by averaging becomes.

The invention is not restricted to the exemplary embodiment, but can also be implemented in another form by the person skilled in the art. For example, the control circuit shown in FIG. 5 can have PID or PD behavior according to the circumstances.

Claims (5)

1. A method for analog / digital conversion, wherein the measured variable to be converted and a reference variable with opposite polarity are fed to an integrator, an integration cycle being formed by first applying the measured variable to the integrator and connecting the reference variable at a later first time and after a second point in time the supply of the measured variable to the integrator is switched off, and furthermore the integration cycle is terminated on a subsequent zero crossing of the integrator output signal, characterized in that the first point in time is regulated in such a way that the zero crossing is a predetermined time after the measured variable has been switched on he follows. 2. The method according to claim 1, characterized in that the value of the measurand from the last specified first Time and time of the last zero crossing is calculated as soon as the zero crossing within a predetermined deviation from the predetermined time.   3. The method according to claim 2, characterized in that rougher when determining the first point in time Quantization levels are applied as to the determination of the measured value. 4. The method according to any one of the preceding claims, characterized in that at the end of the integration cycle the supply of the reference variable to the integrator is interrupted and the then existing output signal of the integrator received until the beginning of the following integration cycle remains. 5. Circuit arrangement for carrying out the method according to the invention, characterized in that the measured variable and the reference variable can be fed to an integrator ( 5 ) via two switches ( 3, 4 ) which can be controlled independently of one another, the output of which is connected to an input of a comparator ( 6 ), and that an output of the comparator ( 6 ) and control inputs of the switches ( 3, 4 ) are connected to a digital control unit ( 7 ).