DE3782279T2 - ELECTRICALLY CHANGEABLE, NON-VOLATILE STORAGE ARRANGEMENT OF THE FLOATING GATE TYPE, WITH A LESS TUNNEL EFFECT AREA AND MANUFACTURE THEREOF. - Google Patents

Description

The present invention relates generally to semiconductor memory devices and more particularly to electrically changeable floating gate type read only memory devices used in microprocessor based systems, dedicated non-volatile memories, television channel selectors and other similar systems.

Microprocessor-based systems and related devices increasingly require read-only memory elements that can be altered by electrical means, i.e. memory elements that, while designed to retain data written therein for relatively long periods of time (several years), nevertheless offer the possibility of erasing and rewriting (reprogramming) all or part of the data contained therein by electrical means, essentially without the need to remove the microcircuitry containing them from the device in order to carry out the irradiation erasure treatments (which precede any total reprogramming that may be required), as was required for read-only memory devices of the FAMOS type, the latter standing for "Floating Gate Avalanche Metal Oxide Semiconductor".

Recently, the art has reached a point where a number of electrically alterable, non-volatile memory devices have been successfully manufactured. Microprocessors or systems incorporating such memory devices, also known as EE-PROM for "Electrically Erasable- Programmable Read-Only Memory" or EA-PROM for "Electrically Alterable - Programmable Read-Only Memory", offer the great advantage over prior art devices of allowing both the erasure and rewriting of individual bytes and the erasure of all stored data.

The memory cell, i.e. the basic integrated semiconductor structure of such devices, is the so-called FLOTOX cell, which is derived from "Floating Gate Tunnel Oxide" and is described in an article entitled "16-J-EE-PROM Relies on Tunnelling for Byte-Erasable Program Storage" by WS Johson et al in "Electronics" of February 28, 1980, pages 113-117. In this article, the author describes a FLOTOX structure in which a cell using a floating gate polycrystalline silicon structure has such a structure charged with electrons (or holes) through a suitable "window", creating a thin oxide layer between the floating gate structure and the monocrystalline silicon corresponding to the drain region by a Fowler-Nordheim tunneling mechanism. That is, the mechanism used to confine the charge in a floating gate electrode is conduction by a tunneling effect of electrons (or holes) through a thin oxide dielectric layer caused by sufficiently high electric fields, generally of at least 10 MV/cm.

Similar prior art devices corresponding to the preamble of claim 1 are known from Electronics, Volume 53, No. 5 (1980); W.S. Johnson et al: "16-K EE-PROM relies on tunnelling for byte-erasable program storage" and from EP-A-0 164 605.

The understanding of the prior art and its disadvantages as well as the description of the object of the present invention directed to a FLOTOX cell are facilitated by reference to the accompanying drawings, in which:

Fig. 1 is a schematic sectional view of the structure of a FLOTOX memory cell of the conventional type;

Fig. 2 is a diagram of the relevant capacitive couplings of the FLOTOX structure of Fig. 1;

Fig. 3 is a schematic plan view of an elementary FLOTOX memory cell as it is formed in practice on a semiconductor chip according to a known manufacturing process;

Fig. 4 is a schematic plan view of an elementary FLOTOX memory cell manufactured according to another known method different from Fig. 3;

Fig. 5 is a schematic plan view of an elementary FLOTOX memory cell formed according to the present invention;

Fig. 6 is a schematic sectional view of the elementary FLOTOX memory cell of the present invention.

As shown schematically in Fig. 1, a typical configuration of a FLOTOX cell comprises a first level or layer of polycrystalline silicon 1 which is completely insulated and forms the floating gate electrode. This layer is insulated from the monocrystalline silicon 2 by the gate oxide layer 3 and extends across a channel region 9 in the MOS device formed between a source region 10 and a drain region 7 and over a certain distance across this drain region 7. An insulating layer 4 of silicon oxide or an equivalent dielectric, grown under the influence of heat or deposited by chemical vapor deposition (CVD), insulates the first level of polycrystalline silicon 1 from a second level of polycrystalline silicon 5 which forms the so-called control gate electrode. A suitable write/erase "window" 6 is provided in the gate oxide layer 3 to transfer electrical charges corresponding to the drain region 7 of the MOS device to the floating gate 1 through a tunneling mechanism. According to this window, the insulation between the floating gate and the silicon is formed by an extremely thin layer of silicon oxide 8, called tunnel oxide, the thickness of which is greater than the normal thickness of the gate oxide 3, which is typically more than 25 nm (250 ), and compared to the thickness of the insulating layer 4, which is typically more than 20 nm (200 ), normally less than 10 nm (100 ).

Furthermore, Fig. 1 shows the line selection or select transistor, which is formed in series with the actual memory cell and whose gate is also referred to as "transfer gate".

The working principle of this memory cell is well known: electrons can be injected into the floating gate by applying a suitable electric field between this floating gate and the drain of the memory device; such an electric field is applied by a capacitive coupling through the control gate, whereby access to the floating gate is not possible. Electrons can be removed from the floating gate by applying an electric field of opposite sign again between the floating gate and the drain; this is achieved by connecting the control gate to ground and by applying a positive voltage to the drain of the memory element via the transfer gate.

One of the most important technical problems encountered in the realization of such memory cells concerns the definition of the tunnel region, i.e. the thin oxide "window" for the transfer of electrical charges to and from the floating gate. In reality, it is necessary to make this region as small as possible for two reasons.

The memory element can be represented schematically as a capacitor network, as shown in Fig. 2. Essentially, the memory element, i.e. the floating gate (FG), is capacitively coupled to the control gate (CG) 5 by the capacitance C1 of the dielectric layer 4, to the semiconductor material of the drain zone (D), the source zone (S) and the channel zone (Ch), i.e. to the zones 7, 10 and 9, by the capacitance C2 of the gate oxide 3, and to the drain zone (D) 7 by the capacitance C3 of the tunnel oxide 8. The potential that the floating gate of the memory device can reach obviously depends on the values of the voltages applied between the control gate and the drain of the device, on its capacitive coupling and on the stored electrical charge. By appropriate considerations, one arrives at the conclusion that the potential that can be reached by the floating gate is determined by:

VFG = αVCG, where α = C₁/C₁ + C2; + C3;

In order to minimize the voltages to be applied to the device to modify its state, i.e. to trigger the "write" and "erase" operations, it is advantageous that the value of C3 is as low as possible: given that the tunnel oxide must necessarily be extremely thin in order to be able to receive extremely intense electric fields (of the order of 10 MV/cm) through its thickness so that the electric charges can overcome the energy barrier through the tunnel mechanism, this tunnel region must be reduced as much as possible in order to keep the value of C3 low and thereby maximize the constant α.

The reduction of the tunnel area is also advantageous for other reasons. The extremely thin dielectric layer of tunnel oxide, exposed to extremely high electric fields in the manner mentioned, is subject to a well-known wear phenomenon, i.e. the oxide has a tendency to deteriorate after a certain number of write and erase cycles. This phenomenon arises due to the fact that even when using the most precise techniques for forming such a thin layer of dielectric, it is impossible for its surface to remain completely free of lattice defects which become a cause of the wear phenomenon. Reducing the size of the tunnel area therefore means, on the other hand, increasing the probability that such a small area will remain free of defects.

According to the known techniques, the definition of the tunnel oxide region and its formation generally take place in the manner shown schematically in Figs. 3 and 4.

Figures 3 and 4 show plan views of a FLOTOX memory cell as schematically shown in Figure 1, the reference numerals of which are also used in Figures 3 and 4 to designate the same parts. The "T"-shaped outline shown by the thick lines 12 defines the active area of an elementary memory cell, i.e. the area not covered by the field oxide. In both Figures 3 and 4, an area 13 is shown which serves for the electrical "column" connection of the elementary FLOTOX cell in a conventional memory matrix, which is made up of a large number of cells arranged in an array of rows and columns.

According to the manufacturing process of the elementary memory cell of Fig. 3, the tunnel oxide region 6 is defined by the crossing of two masks; i.e. the mask used to define the first level of polycrystalline silicon 1 (floating gate) and a mask used to "open" the gate oxide in a region shown in dashed lines 14 over which tunnel oxide is grown.

According to another technology, as shown in Fig. 4, the tunnel region 6 is defined by a suitable mask which determines the window through which the gate oxide is etched until the underlying silicon is exposed, before the tunnel oxide is then grown over this region.

Both the techniques shown in Figs. 3 and 4, as well as other similar techniques, have the disadvantage of being limited by the definition and alignment characteristics of the particular photolithographic technique used or available. On the other hand, the need to reduce the tunnel area as much as possible requires working at the definition limit, with the result that serious problems of control and reproducibility are imposed on the manufacturing process without obtaining decisively satisfactory results in terms of minimizing the tunnel area.

This has led to a tendency to use photolithographic technologies to define the tunnel region that are more advanced than those normally used for all other layers of the integrated circuit, thereby creating even more complex problems of compatibility between the various devices used in the manufacturing process.

There is therefore a clear need or benefit in using a FLOTOX cell for EEPROM memories, which has minimal dimensions in terms of the tunnel area and can be easily manufactured without the need for particularly complicated photolithographic technologies.

Such objects and advantages are achieved by the floating gate type non-volatile semiconductor memory device (also known as a FLOTOX cell) having a novel configuration and structure as defined in the appended claims. The structure of the FLOTOX cell of the present invention is such that it enables the tunnel region to be minimized regardless of the limitations of the particular photolithographic technology used to define the regions, and it enables the extent of the tunnel region to be defined by controlling substantially non-critical parameters of the manufacturing process.

In contrast to the FLOTOX cells of known type, the cell according to the invention no longer provides for a tunnel region which is located within a much larger, superimposed zone of the floating gate above the Drain region of the MOS device, but instead is defined according to the edge of the floating gate lying towards the drain region of the device, wherein after removal of the gate oxide, and after formation of a layer of tunnel oxide over a sufficiently extensive area containing at least a portion of said edge, an appendage (or seam-like edge) of polycrystalline silicon is formed which is electrically connected to the floating gate in a suitable manner. The lower base of such a seam-like edge of polycrystalline silicon results in being insulated from the monocrystalline silicon by the layer of tunnel oxide. Such an appendage or seam formed along the edge of the floating gate may advantageously be formed by a so-called "self-aligned" process in which no critical mask is required and in which the "width" of the base of such seam defining the tunnel area or region may be easily determined by controlling the conditions under which an anisotopic etch is carried out of an appropriate layer or layers of polycrystalline matrix silicon previously deposited on the surface of the wafer being processed.

A further advantage of the special configuration of the cell according to the object of the present invention is due to the fact that, by eliminating the need to create a sufficiently large overlay region between the polycrystalline silicon of the first level (floating gate) and the drain region of the device, it is possible to achieve the high throughput of a single memory cell to reduce the total area occupied, i.e. to create more compact cells.

The FLOTOX cell according to the invention and the method for producing the same are explained in more detail by the presentation of a particularly preferred embodiment of the invention with reference to Figs. 5 and 6.

Referring now to Figures 5 and 6, wherein the same reference numerals are used to designate corresponding or similar parts shown in the preceding figures described in connection with the prior art, the FLOTOX cell according to the invention comprises, similarly to the prior art cells, a first level of polycrystalline silicon (referred to as polysilicon 1 for short), which is shown in the figures by a special hatching and is insulated from the surface of the semiconductor material by the dielectric layer of gate oxide and forms the storage element, i.e. the floating gate of the device.

Such a first layer or level of polysilicon is arranged above a channel zone 9 of the semiconductor material chip 2 and extends laterally beyond a certain distance of the surrounding field oxide, which defines the active region of the elementary cell and is indicated in Fig. 5 by the thick lines 12.

The MOS device is preferably an N-channel, ie the channel region 9 is formed on the surface of a semiconducting monocrystal, e.g. made of silicon with p-conductivity, ie made of silicon doped with acceptor dopants (e.g. boron).

The source region 10 and the drain region 7 of the device are formed in a conventional manner by strong implantation and diffusion of donor dopants (e.g. phosphorus or arsenic).

By means of a suitable non-critical mask, the outline of which can have the outline shown in a dashed line 15 in Fig. 5, the gate oxide previously formed on the surface of the silicon before the application and definition of the first level of polysilicon 1 is removed until the silicon within the area lying in this outline 15, which is not covered by the first layer or the first level of polysilicon 1, is exposed again. The thin layer of tunnel oxide 8 is then formed by thermal oxidation under particularly strict conditions with regard to the absence of impurities, whereby this naturally also forms over the upper surface and over the vertical edges of the first layer of polysilicon 1.

By means of a further mask (which is also of a non-critical nature), which can have the outline shown by the dash-dotted line 16 in Fig. 5, preferably after the application of a first matrix layer of polycrystalline silicon with a thickness of approximately 50 nm (500 ), both the matrix layer of polysilicon and the previously formed layer of tunnel oxide are removed within the area defined by the mask.

A second matrix layer of polycrystalline silicon of uniform thickness, preferably between 400 and 500 nm (4000 and 5000 ), is deposited over the entire surface of the device, this second layer being deposited directly on the surface of the first level of polysilicon 1 within those regions where the tunnel oxide has previously been removed, and thus being in a state of electrical continuity with respect to it.

As in a so-called self-aligned manufacturing process, a highly anisotropic etching process, e.g. a reaction ion etching process, carried out until the entire thickness of the layer or layers of polycrystalline matrix silicon (50 + 400 or 500 nm) (500 + 4000 or 5000 ) is completely removed, determines the formation of an appendage or a seam-like edge (which may also be referred to as a "spacer" analogously to such seam-like edges or spacers of dielectric materials formed in the so-called self-aligned process) 1a and 1b of polycrystalline silicon along the edges of the first level polysilicon 1.

Such a seam-like edge (1a and 1b in the drawings) is continuous, but it is separated from the first level polysilicon 1 by the layer of tunnel oxide 8 (which provides further insulation of it from the silicon, as can be seen in Fig. 6) corresponding to the edge of the floating gate 1 adjacent to the drain region 7 of the device; however, corresponding to the edge of the floating gate 1 adjacent to the source region 10, the same A seam-like edge of polysilicon is formed directly above the edge of the already existing first level of polysilicon 1 after the thin layer of tunnel oxide has been removed from the area defined by the mask 16 in the manner described above (Fig. 5).

In this way, the result is that the length of the seam-like edge 1b formed above the edge of the floating gate 1 adjacent to the drain zone 7, the base area, i.e. the width of which determines the extent of the tunnel region, is also in electrical connection with the previously formed region of the floating gate, which is formed by the first level of polysilicon 1. At least within the overlay zone of the polysilicon above the field oxide on the right-hand side of Fig. 5, it is actually the case that the seam-like edge of polysilicon 1b is in direct contact with the polysilicon 1 of the first level, at least along the length designated by the reference numeral 17.

Obviously, other methods can also be used to ensure electrical continuity between the two regions forming the floating gate of the device, i.e. between the first polysilicon 1, which constitutes the true floating gate of the device and lies substantially above the channel region 9, and the appendix 1a, 1b formed along the edges of the first layer of polysilicon 1, which, corresponding to the region overlying the drain region 7 (length 1b), forms the necessary tunnel region for the transfer of electrical charges to and from the composite structure of the floating gate.

By using modern deposition techniques for depositing polycrystalline silicon to form the first and second matrix layers and a reaction ion etching process for removing them under conditions of a highly anisotropic etching process, the width of the base of the seam-like edge 1a, 1b between 0.2 and 0.5 µm can be easily achieved and if the base width of the seam-like edge is chosen to be 0.3 µm, for example, a tunnel region of 0.3·1.5 = 0.45 µm² can be easily achieved (if the width of the active area occupied by the memory element is 1.5 µm, as is common practice).

According to the known structures of the FLOTOX cell, a similar result would require a 0.7 µm technology; i.e. a technology with a definable minimum width of 0.7 µm, and thus an extremely complicated photolithographic technology using X-rays instead of UV light would be necessary.

The advantages and optimization possibilities available through the cell or storage device according to the present invention are multifaceted, due to the fact that such a reduction in the surface area and hence the capacity of the tunnel oxide, in addition to the improved withstand properties with respect to repeated write/erase cycles of the stored data, is also accompanied by other positive results, as will be readily apparent to those skilled in the art.

For example, the original configuration of the cell according to the invention allows for a strong Reduction also of the capacitance C₂ (Fig. 2) in that the entire floating gate becomes more compact and no longer needs to extend over a reasonably large area above the drain region; the dimensions (in the "column" direction) and/or the overlying area of the control gate and the floating gate over the surrounding field oxide to increase the capacitance C₁ can be reduced, thus enabling a higher level of integration.

The reduced criticality of the surface definition operations (i.e. the masks) also leads to an increase in the "yield" of the manufacturing process.

The arrangement and connection of the individual storage device, i.e. the individual FLOTOX cells and the associated selection transistor to form a memory row, are carried out in the usual way, according to which the source zones of all elementary cells are connected to ground, the control gates of all cells are connected to a "program line", the gates of the selection transistors are connected to a so-called "select line" and each drain connection of the various selection transistors forms the connection of each "column" of the memory row.

To discharge the charge from all unit cells, the program lines and the select lines are polarized with a sufficiently high voltage, while the column terminals are connected to ground.

To write a data byte, the program line is connected to ground, while the Columns relative to the selected byte may be polarized to a high voltage or grounded according to the data pattern, with the select line maintained at a high voltage.

The preferred manufacturing process for forming the novel memory devices of the present invention can be described by a series of essential process steps, which are set out below.

A layer of silicon nitride is applied over a semiconducting material of a first conductivity type (typically a wafer of monocrystalline, p-doped silicon) that has been pre-oxidized on its surface.

The active areas are then masked with photoresist to etch the nitride, followed by the so-called field implantation; i.e. the implantation of acceptor dopants in areas where the insulating structure (thick layer of field oxide) is formed to separate the individual elementary devices to be formed on the surface of the monocrystalline silicon.

After removing the masking material, field oxidation is performed to grow the thick layer of silicon oxide in areas that were not previously covered by the silicon nitride layer. At the same time, the implanted dopant diffuses into the silicon in an area immediately beneath the field oxide, thus completing the formation of the insulating structure.

After removing the silicon nitride layer and the thin layer of surface oxide that was previously grown over the surface of the silicon single crystal, a new layer of silicon oxide is grown under particularly strict conditions with regard to the absence of impurities in order to form the so-called gate oxide.

The first layer or level of polycrystalline silicon is then deposited and finally doped to increase its bulk electrical conductivity. The thickness of the first polysilicon is preferably between 4000 and 5000 μm.

A new masking process is performed and the layer of polycrystalline silicon is etched, defining the edges of the first polysilicon 1, i.e. the floating gate of the memory device, along one direction.

A new photoresist mask is formed for the so-called FLOTOX implantation, and dopants of a second conductivity type (n-type conductivity in the illustrated embodiment) are implanted into the silicon to form the n+ doped regions which form the drain region and the source region of the MOS devices, respectively.

After removing the masking material used for the n+ implantation, a new photoresist mask (the outline of which is shown in Fig. 5 with the reference numeral 15) is formed, and through this mask the gate silicon oxide is formed in the region not covered by the first level of polysilicon. area is etched until the underlying silicon crystal is exposed.

After removing the remaining masking material, a thin layer of silicon oxide with a thickness of approximately 10 nm (100 ) (tunnel oxide) is grown under heat under particularly strict conditions with regard to the absence of impurities.

A first thin matrix layer of polycrystalline silicon with a thickness of approximately 50 nm (500 ) is applied over this thin layer of tunnel oxide.

A new photoresist mask, the outline of which is shown in Fig. 5 with the reference number 16, allows removal of both the polycrystalline silicon of the first thin matrix layer and the underlying thin layer of tunnel oxide within such a defined area.

After removing the masking material, a second matrix layer of polycrystalline silicon is applied with a thickness preferably between 300 and 400 nm (3000 and 4000 ).

The polycrystalline silicon matrix layer is then subjected to an anisotropic etching process by reaction ion etching, and the polycrystalline silicon is removed until a thickness corresponding to the deposited thickness has been removed. As is well known to those skilled in the art and corresponds to the so-called self-aligned manufacturing processes, according to the properties created by the presence of the underlying layer of polycrystalline silicon of the first Levels (floating gate 1) certain steps by the anisotropic etching process a remaining seam-like edge (1b and 1a) in Fig. 5 and 6) of polycrystalline silicon is left, which belongs to the matrix layer previously applied uniformly over the entire surface.

At this point, it is possible to remove the previously formed gate silicon oxide layer from the active regions of the device that are not covered by the composite structure (1 + 1a + 1b) of the floating gate of the fabricated memory device.

After defining the edges of the composite floating gate structure along a direction perpendicular to the direction of extension of the previously defined edges by means of a suitable mask, a new layer of gate silicon oxide can be formed again over the active area not covered by the composite floating gate structure under particularly strict conditions regarding the absence of impurities. At the same time, the insulating dielectric layer 4 can advantageously be formed over the floating gate for insulation. Alternatively, such an upper insulating layer of the floating gate structure can be formed separately by chemical vapor deposition of silicon oxide or an equivalent oxide.

The second level of polycrystalline silicon is deposited and preferably doped to increase its electrical volume conductivity.

The manufacturing process then involves growing a layer of oxide over such a second layer or second level of polycrystalline silicon, defining the geometries of the second level of polycrystalline silicon (the circuit arrangement and the memory cells) using suitable masks, and etching the second level of polycrystalline silicon.

The manufacturing process then continues in a conventional manner like any other polysilicon gate CMOS or NMOS process.

The semiconductor material 2 over which the individual elementary memory devices are formed can also be a "well" zone of a certain conductivity type (in the illustrated embodiment, p-doped silicon) which is formed in a substrate made of a semiconductor material of a different conductivity type (e.g. n-doped silicon).

Claims (14)

1. Electrically alterable non-volatile memory device of the floating gate type, comprising a substrate (2) of semiconductor material, with a channel region (9) of a first conductivity type extending between a first (10) and a second region (7) of a second conductivity type formed on the surface of the semiconductor substrate, the channel region forming a region in the semiconductor capable of allowing an electric current to flow between the first and second regions, a patterned layer of a first level of conductive material forming the floating gate (1) extending substantially between the first (10) and the second region (7) above the channel region (9) and separated by a first layer (3) of dielectric material from the semiconductor substrate and by a second layer (4) of dielectric material from a patterned layer of a second level of a conductive material which forms a control gate (5) overlying the floating gate (1), and which further comprises: a tunnel region formed on the surface of the first zone (10) or the second zone (7) of the semiconductor surface, the tunnel region being covered by a third layer (8) of dielectric material which is thinner than the first layer (3) of dielectric material; characterized in that the tunnel region is delimited on one side by the lower part of a side wall of the floating gate (1) extending in the direction perpendicular to the extension of the channel zone, and in that a tapered lateral seam-like appendage (1b) made of a conductive material is juxtaposed along the part of the side wall of the floating gate (1), the base of the juxtaposed tapered lateral seam-like appendage (1b) made of conductive material abutting the surface of the third layer (8) of dielectric material covering the tunnel region, wherein the seam-like appendage (1b) is connected to the patterned first level layer of conductive material forming the floating gate (1). 2. A memory device according to claim 1, wherein the channel region (9) consists of p-doped silicon, the first region (10) and the second region (7) consist of n+ -doped silicon and the appendix (1b) is superimposed on a drain region of the device. 3. A memory device according to claim 1, wherein the patterned layer (1) of the first level and the patterned layer (5) of the second level of conductive material and the seam-like tapered appendage (1b) of conductive material consist of doped polycrystalline silicon. 4. A memory device according to claim 1, wherein the first or gate layer (3) is made of dielectric Material is a layer of silicon oxide with a thickness between 30 and 50 nm. 5. A memory device according to claim 1, wherein the third or tunnel layer (8) of dielectric material is a layer of silicon oxide with a thickness of less than 10 nm. 6. A memory device according to claim 1, wherein the appendix (1b) is made of polycrystalline silicon and is formed by anisotropic etching of a conformally deposited layer of polycrystalline silicon of uniform thickness. 7. A memory device according to claim 1, wherein the channel region (9) and the first region (10) and the second region (7) are all contained in a "well" region of a first conductivity type formed in a substrate of semiconducting material of a second conductivity type. 8. A memory device comprising a number of memory devices according to claim 1 arranged in an addressable array of rows and columns on the semiconductor substrate. 9. A memory device according to claim 8, wherein each of the devices is associated with a MOS selection transistor functionally connected in series therewith. 10. A memory device according to claim 9, wherein the control gate of each of the floating gate type memory devices associated with belonging to each row is connected to a single program line and all gates of the associated select transistors are connected to a single select line. 11. A memory device according to claim 1, wherein the seam-like appendage (1b) is juxtaposed along the sidewall of the floating gate (1) and insulated therefrom by an insulating layer (8) over a length of the sidewall equal to the part of the length of the sidewall of the floating gate (1), the seam-like appendage (1b) continuing without interruption around the entire circumference of the patterned conductive material forming the floating gate (1) and directly abutting the sidewall thereof in electrical continuity along portions of the circumference outside the part of the length of the sidewall. 12. A method of forming an electrically changeable non-volatile memory device according to any one of the preceding claims in a substrate of semiconductor material with a channel zone (9) formed in the substrate between a drain zone (7) and a source zone (10) and with a floating gate (1, 1b) of a conductive layer of a first level on the channel zone, insulated from the substrate by a dielectric gate layer (3, 8), and with an extension projecting over the drain zone into a tunnel region, where the insulation (8) between the extended floating gate and the drain zone is formed by a dielectric tunnel layer which is thinner than the gate dielectric layer. layer, which includes the following steps: (a) forming a gate dielectric layer (3) over the substrate; (b) depositing and patterning a first layer (1) of a conductive material over the channel region; (c) masking (15) and removing the gate dielectric layer in a first region comprising at least a portion of the perimeter of the patterned first layer of conductive material, substantially overlapping an edge portion of the drain region; (d) forming a layer of a dielectric tunnel layer (8) over the first region and over the patterned first layer of conductive material; (e) depositing a second level layer of conductive material over all said layers; (f) masking (1b) and removing the second level layer of conductive material and the tunnel dielectric layer in a second region including at least another part of the perimeter of the patterned first layer of conductive material that does not overlap with the edge part of the drain region; (g) depositing a third level layer of conductive material over all said patterned layers; (h) anisotropically etching the third level conductive material layer and the second level conductive material layer, leaving a seam-like residue (1b) of conductive material of the third conductive material layer and the second conductive material layer along the periphery of the patterned first conductive material layer electrically connected thereto along the other part of the periphery of the patterned first conductive material layer to form the floating gate extension projecting beyond the drain region; (i) removing the gate dielectric layer in areas not covered by the patterned layer of the first level of conductive material and by the seam-like residue; (l) Forming a new gate dielectric layer over the uncovered areas. 13. The method of claim 12, further comprising, after step 1, applying and patterning a further layer of conductive material over the patterned first layer of conductive material provided by the first patterned layer of conductive material. 14. The method of claim 13, wherein an insulating dielectric layer separating the further layer of conductive material from the patterned first layer of conductive material is formed simultaneously with the new gate dielectric layer by thermal oxidation.