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DE3777313D1 - Herstellungsmethode fuer kontaktoeffnungen mit abgeschraegten waenden. - Google Patents

Herstellungsmethode fuer kontaktoeffnungen mit abgeschraegten waenden.

Info

Publication number
DE3777313D1
DE3777313D1 DE8787113322T DE3777313T DE3777313D1 DE 3777313 D1 DE3777313 D1 DE 3777313D1 DE 8787113322 T DE8787113322 T DE 8787113322T DE 3777313 T DE3777313 T DE 3777313T DE 3777313 D1 DE3777313 D1 DE 3777313D1
Authority
DE
Germany
Prior art keywords
manufacturing
contact openings
sloped walls
sloped
walls
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8787113322T
Other languages
English (en)
Inventor
Ronald Stephen Horwath
Rohn Richard Susko
Robin Anne Susko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3777313D1 publication Critical patent/DE3777313D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
DE8787113322T 1986-10-06 1987-09-11 Herstellungsmethode fuer kontaktoeffnungen mit abgeschraegten waenden. Expired - Lifetime DE3777313D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/915,462 US4830706A (en) 1986-10-06 1986-10-06 Method of making sloped vias

Publications (1)

Publication Number Publication Date
DE3777313D1 true DE3777313D1 (de) 1992-04-16

Family

ID=25435787

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787113322T Expired - Lifetime DE3777313D1 (de) 1986-10-06 1987-09-11 Herstellungsmethode fuer kontaktoeffnungen mit abgeschraegten waenden.

Country Status (4)

Country Link
US (1) US4830706A (de)
EP (1) EP0263322B1 (de)
JP (1) JP2553079B2 (de)
DE (1) DE3777313D1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0770525B2 (ja) * 1987-09-11 1995-07-31 株式会社日立製作所 絶縁膜への接続窓形成方法
US5108785A (en) * 1989-09-15 1992-04-28 Microlithics Corporation Via formation method for multilayer interconnect board
US5382315A (en) * 1991-02-11 1995-01-17 Microelectronics And Computer Technology Corporation Method of forming etch mask using particle beam deposition
US5244538A (en) * 1991-07-26 1993-09-14 Microelectronics And Computer Technology Corporation Method of patterning metal on a substrate using direct-write deposition of a mask
US5227013A (en) * 1991-07-25 1993-07-13 Microelectronics And Computer Technology Corporation Forming via holes in a multilevel substrate in a single step
US5242864A (en) * 1992-06-05 1993-09-07 Intel Corporation Polyimide process for protecting integrated circuits
US5840402A (en) * 1994-06-24 1998-11-24 Sheldahl, Inc. Metallized laminate material having ordered distribution of conductive through holes
JP2000500618A (ja) * 1995-11-22 2000-01-18 オリン コーポレイション 接地または電源リングを有する半導体パッケージ
US6259148B1 (en) 1998-08-13 2001-07-10 International Business Machines Corporation Modular high frequency integrated circuit structure
US7060624B2 (en) * 2003-08-13 2006-06-13 International Business Machines Corporation Deep filled vias
US7390740B2 (en) * 2004-09-02 2008-06-24 Micron Technology, Inc. Sloped vias in a substrate, spring-like contacts, and methods of making
JP2011243790A (ja) * 2010-05-19 2011-12-01 Panasonic Electric Works Co Ltd 配線方法、並びに、表面に配線が設けられた構造物、半導体装置、配線基板、メモリカード、電気デバイス、モジュール及び多層回路基板
TWI548587B (zh) * 2015-01-26 2016-09-11 國立臺灣大學 奈米金屬線圖案化之方法，使用該方法製備而成之圖案化奈米金屬線電極以及包含該圖案化奈米金屬線電極做為材料之電晶體元件
KR102611325B1 (ko) * 2015-03-31 2023-12-08 하마마츠 포토닉스 가부시키가이샤 반도체 장치

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4998189A (de) * 1973-01-19 1974-09-17
JPS52141592A (en) * 1976-05-20 1977-11-25 Fujitsu Ltd Process of semiconductor device
JPS5621332A (en) * 1979-07-31 1981-02-27 Fujitsu Ltd Manufacture of semiconductor device
JPS5850417B2 (ja) * 1979-07-31 1983-11-10 富士通株式会社 半導体装置の製造方法
US4353778A (en) * 1981-09-04 1982-10-12 International Business Machines Corporation Method of etching polyimide
JPS59214240A (ja) * 1983-05-09 1984-12-04 Fujitsu Ltd 半導体装置の製造方法
US4495220A (en) * 1983-10-07 1985-01-22 Trw Inc. Polyimide inter-metal dielectric process
US4590258A (en) * 1983-12-30 1986-05-20 International Business Machines Corporation Polyamic acid copolymer system for improved semiconductor manufacturing
US4482427A (en) * 1984-05-21 1984-11-13 International Business Machines Corporation Process for forming via holes having sloped walls
US4601915A (en) * 1984-09-24 1986-07-22 Motorola, Inc. Method of fabricating air supported crossovers
US4670297A (en) * 1985-06-21 1987-06-02 Raytheon Company Evaporated thick metal and airbridge interconnects and method of manufacture
GB8523373D0 (en) * 1985-09-21 1985-10-23 Stc Plc Via profiling in integrated circuits
US4661204A (en) * 1985-10-25 1987-04-28 Tandem Computers Inc. Method for forming vertical interconnects in polyimide insulating layers

Also Published As

Publication number Publication date
EP0263322A2 (de) 1988-04-13
JPS6396923A (ja) 1988-04-27
EP0263322A3 (en) 1988-09-21
JP2553079B2 (ja) 1996-11-13
US4830706A (en) 1989-05-16
EP0263322B1 (de) 1992-03-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee