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DE3751159D1 - Adressierungsverfahren für gleichzeitige Lese-, Änderungs- und Schreib-Operationen mit schlangenförmiger RAM-Konfiguration. - Google Patents

Adressierungsverfahren für gleichzeitige Lese-, Änderungs- und Schreib-Operationen mit schlangenförmiger RAM-Konfiguration.

Info

Publication number
DE3751159D1
DE3751159D1 DE3751159T DE3751159T DE3751159D1 DE 3751159 D1 DE3751159 D1 DE 3751159D1 DE 3751159 T DE3751159 T DE 3751159T DE 3751159 T DE3751159 T DE 3751159T DE 3751159 D1 DE3751159 D1 DE 3751159D1
Authority
DE
Germany
Prior art keywords
serpentine
change
write operations
addressing method
simultaneous read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3751159T
Other languages
English (en)
Other versions
DE3751159T2 (de
Inventor
Charles D Thompson
Joseph P Gergen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of DE3751159D1 publication Critical patent/DE3751159D1/de
Application granted granted Critical
Publication of DE3751159T2 publication Critical patent/DE3751159T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System (AREA)
DE3751159T 1986-06-26 1987-04-13 Adressierungsverfahren für gleichzeitige Lese-, Änderungs- und Schreib-Operationen mit schlangenförmiger RAM-Konfiguration. Expired - Fee Related DE3751159T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/878,926 US5001665A (en) 1986-06-26 1986-06-26 Addressing technique for providing read, modify and write operations in a single data processing cycle with serpentine configured RAMs

Publications (2)

Publication Number Publication Date
DE3751159D1 true DE3751159D1 (de) 1995-04-20
DE3751159T2 DE3751159T2 (de) 1995-10-19

Family

ID=25373099

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3751159T Expired - Fee Related DE3751159T2 (de) 1986-06-26 1987-04-13 Adressierungsverfahren für gleichzeitige Lese-, Änderungs- und Schreib-Operationen mit schlangenförmiger RAM-Konfiguration.

Country Status (4)

Country Link
US (1) US5001665A (de)
EP (1) EP0253956B1 (de)
JP (1) JPS638952A (de)
DE (1) DE3751159T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5212780A (en) * 1988-05-09 1993-05-18 Microchip Technology Incorporated System for single cycle transfer of unmodified data to a next sequentially higher address in a semiconductor memory
EP0411633B1 (de) * 1989-08-02 1995-08-16 Fujitsu Limited Abtastwandlerregelkreis mit Speichern und Adressengenerator zur Erzeugung eines den Speichern zugeführten Zickzackadressensignals
US5420997A (en) * 1992-01-02 1995-05-30 Browning; Gary A. Memory having concurrent read and writing from different addresses
JPH0612107A (ja) * 1992-06-02 1994-01-21 Mitsubishi Electric Corp シーケンス演算プロセッサおよびシーケンス演算処理装置
JPH1064257A (ja) * 1996-08-20 1998-03-06 Sony Corp 半導体記憶装置
US5960454A (en) * 1996-12-19 1999-09-28 International Business Machines Corporation Avoiding cache collisions between frequently accessed, pinned routines or data structures
KR101305490B1 (ko) * 2005-10-01 2013-09-06 삼성전자주식회사 메모리 맵핑 방법 및 장치
US7684257B1 (en) * 2006-12-15 2010-03-23 Cypress Semiconductor Corporation Area efficient and fast static random access memory circuit and method
US20080168331A1 (en) * 2007-01-05 2008-07-10 Thomas Vogelsang Memory including error correction code circuit
KR101239767B1 (ko) * 2007-11-12 2013-03-06 삼성전자주식회사 화상형성장치 및 그 제어방법
CN101478785B (zh) * 2009-01-21 2010-08-04 华为技术有限公司 资源池管理系统及信号处理方法
US10423215B2 (en) 2017-05-15 2019-09-24 Cavium, Llc Methods and apparatus for adaptive power profiling in a baseband processing system

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3875391A (en) * 1973-11-02 1975-04-01 Raytheon Co Pipeline signal processor
JPS52153714A (en) * 1976-06-16 1977-12-21 Matsushita Electric Ind Co Ltd Filing device
US4169284A (en) * 1978-03-07 1979-09-25 International Business Machines Corporation Cache control for concurrent access
FR2461301A1 (fr) * 1978-04-25 1981-01-30 Cii Honeywell Bull Microprocesseur autoprogrammable
US4217639A (en) * 1978-10-02 1980-08-12 Honeywell Information Systems Inc. Logic for generating multiple clock pulses within a single clock cycle
US4245304A (en) * 1978-12-11 1981-01-13 Honeywell Information Systems Inc. Cache arrangement utilizing a split cycle mode of operation
US4317168A (en) * 1979-11-23 1982-02-23 International Business Machines Corporation Cache organization enabling concurrent line castout and line fetch transfers with main storage
DE3177219D1 (de) * 1980-01-08 1990-11-15 Honeywell Inf Systems Speichersystem.
US4724518A (en) * 1983-07-29 1988-02-09 Hewlett-Packard Company Odd/even storage in cache memory
GB8401807D0 (en) * 1984-01-24 1984-02-29 Int Computers Ltd Pipelined data processing apparatus

Also Published As

Publication number Publication date
EP0253956A2 (de) 1988-01-27
EP0253956A3 (en) 1990-09-05
DE3751159T2 (de) 1995-10-19
JPS638952A (ja) 1988-01-14
US5001665A (en) 1991-03-19
EP0253956B1 (de) 1995-03-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee