DE3743774A1 - Stackable semiconductor components - Google Patents

Abstract

The invention relates to semiconductor components, especially bipolar transistors and diodes, which are arranged one above another. The component layers and the corresponding contact layers are produced in an epitaxial method. Contact with the component layers is achieved via metal semiconductor layers, which are grown epitaxially between the component layers, and via polycrystalline semiconductor layers bordering on the component layer at the sides.

Description

The invention relates to stackable semiconductor components according to the preamble of claim 1.

Stackable semiconductor components, in particular bipolar oil sistors and diodes are used to build VLSI (very large scale integration) circuits or three-dimensional len circuits used.

With conventional production, especially of bipolar transistors become the emitter, base and collector layers either contacted directly via metal contacts or contact wells become perpendicular to the component layered implants or diffuses the  corresponding active component layer with on the top surface of the semiconductor attached metal contacts ver tie. Such contacting of multilayer half conductor components is not pre-published in the German patent application P 37 24 012.9.

Direct contacting has a disadvantage Component layers over metal contacts the difference Lichen, lateral dimensions of the component layers. Unwanted parasitic resistances and capacitances arise would do. In the manufacture of contact troughs in the components elements by implantation or diffusion is disadvantageous, that the semiconductor layers in their crystalline structure be so disturbed that the quality of the herge posed components is impaired.

The invention is based, stackable the task Specify semiconductor devices that are three-dimensional are organized and their electrical leads save space can be integrated so that a high packing density of Semiconductor components is achieved.

This problem is solved by the in the characterizing part of claim 1 specified features. Beneficial Refinements and / or further training are the Unteran sayings.

The invention has the advantage that some of the contacting of semiconductor components via highly conductive, poly and monocrystalline silicide layers that occur between the Device layers have grown epitaxially.  

It is also advantageous that in the polycrystalline Be rich in the semiconductor layer sequence semi-insulating, poly crystalline semiconductor layers can be produced in such a way that the contact layers, which is a space-saving side Allow contacting of the component layers, elec are separable.

The invention is illustrated below with the aid of an embodiment game described with reference to schematic drawing mentions.

Fig. 1 shows two stacked bipolar transistors T _1, T _2.

FIG. 2 and FIG. 3 show a method for producing stacked semiconductor components.

Referring to FIG. 2, an about 50 nm thick amorphous oxide layer 2 is deposited on a high-resistivity substrate 1. In the oxide layer 2 is an oxide window 2 a with a diameter of z. B. 1 to 10 microns etched. With an epitaxy method, preferably MBE (Molecular Beam Epitaxy), a sequence of, for example, 10 nm thick metal and semiconductor layers is alternately deposited and then subjected to an annealing process, so that a highly conductive metal-semiconductor layer of approximately 40 nm results therefrom forms. On the substrate 1, the metal oxide semiconductor layer 3 has a polycrystalline metal-semiconductor layer 3 a growing single crystalline forms and on the oxide film 2 itself. At the boundary between single and polycrystalline growth, a step is created corresponding to the layer thickness of the oxide layer 2 . Then a sequence of semiconductor layers ( 4, 4 a , 5, 5 a , 6, 6 a) is grown with the MBE.

The layer growth is monocrystalline within a region 10 above the exposed substrate 1 and polycrystalline regions 11 form above the oxide layer 2 . If the doping is sufficiently low (<10 ¹⁸ charge carriers per cm ³ ), the polycrystalline semiconductor layers are semi-insulating with a specific resistance which is more than 6 orders of magnitude higher than with appropriately doped single-crystalline semiconductor layers. If the semiconductor layers are highly doped (<10 ¹⁸ charge carriers per cm ³ ), the polycrystalline semiconductor layers are electrically conductive. For example, if the semiconductor layer 4, 4 a low doped, the corresponding device layer 4 may be contacted via the metal oxide semiconductor layer 3, 3 a. The polycrystalline semiconductor layer 4 a is semi-insulating due to the low doping. Has the semiconductor layer 5, 5 a high doping, the device layer 5 is layered over the polycrystalline semiconductor 5a contacted. The semi-insulating, polycrystalline semiconductor layer 4 a acts as an insulating layer between the highly conductive, polycrystalline metal semiconductor layer 3 a and the conductive polycrystalline semiconductor layer 5 a . Is the conductivity of the polycrystalline semiconductor layer 5 a is too small, the conductivity of the polycrystalline semiconductor layer 5 can be a increased by interrupting the epitaxial process and by an additional ion-implantation method. A highly doped, polycrystalline semiconductor layer 5 b is formed ( FIG. 3).

In a further process step one reaches an insulation of the conductive polycrystalline semiconductor layer 5 b from any subsequent contact layers characterized in that the single crystal device layer 6 by a 0.5 to 1 micron thick layer 7, for example. B. of lacquer or oxide, is covered and an insulating semiconductor layer 8 is formed from the polycrystalline semiconductor layer 6 a by ion implantation ( Fig. 3).

A semiconductor structure according to FIG. 1 can be produced by repeating the corresponding process steps.

In the exemplary embodiment according to FIG. 1, two bipolar or heterobipolar transistors T ₁ , T ₂ are arranged one above the other.

An amorphous oxide layer 2 made of SiO ₂ or Si ₃ N ₄ with a layer thickness of approximately 50 nm is applied to an Si substrate 1 with a specific resistance of more than 1000 Qcm. In the oxide layer 2 is an oxide window 2 a is etched with a diameter of about 10 microns. A metal-semiconductor layer 3, 3 a made of NiSi ₂ or CoSi ₂ with a layer thickness of approximately 50 nm and a specific resistance of approximately 4 · 10 ^-5 Qcm has grown epitaxially on the substrate 1 and on the amorphous oxide layer 2 . It builds up a crystalline metal-semiconductor layer 3 above the Si substrate 1 and a polycrystalline metal oxide semiconductor layer 3 a of the amorphous oxide layer on the second A component layer sequence is formed on the metal-semiconductor layer 3

• an n ^- -doped single-crystalline collector layer 4 made of Si or Si _x Ge _{1 - x} with a layer thickness of 0.1 to 0.5 µm and a charge carrier concentration of 10 ¹⁵ to 10 ¹⁶ cm ^-3 ,
• a p⁺-doped, single-crystalline base layer 5 made of Si or Si _x Ge _{1 - x} with a layer thickness of 0.05 to 0.2 µm and a charge carrier concentration of 10 ¹⁷ to 5 · 10 ¹⁸ cm ^-3 ,
• - An n⁺-doped, single-crystal emitter layer 6 made of Si with a layer thickness of 0.1 to 0.5 µm and a charge carrier concentration of 10 ¹⁸ to 10 ²¹ cm ^-3 , and
• - A metal semiconductor layer 9, 9 a corresponding to the metal semiconductor layer 3, 3 a

for a first bipolar or heterobipolar transistor upset.

The collector layer 4 can be contacted via the metal-semiconductor layer 3, 3 a . The base layer 5 borders laterally on a p ⁺⁺ -doped base contact layer 5 b , which consists of polycrystalline Si or Si _x Ge _{1 - x} with a layer thickness of 0.05 to 0.2 μm and a charge carrier concentration of more than 10 ¹⁸ cm ^-3 . The metal-semiconductor layer 9, 9 a is formed as an emitter contact for the emitter layer 6 . The polycrystalline emitter and base contact layers 9 a , 9 b are separated by a semi-insulating semiconductor layer 8 . The semi-insulating semiconductor layer 8 consists of an O⁺ ions implanted, polycrystalline Si layer with a layer thickness of 0.1 to 0.5 microns. The O⁺ ions are implanted with a dose of 10 ¹⁶ to 10 ¹⁸ cm ^-2 and with energies of 20 to 150 keV.

An n ^- -doped semiconductor layer 4 a made of polycrystalline Si or Si _x Ge _{1 - x} with a layer thickness of 0.1 to 0.5 μm acts as an insulator layer between the polycrystalline base and collector contact layers 5 b , 3 a .

On the metal-semiconductor layer 9, 9 a z. B. the analog transistor structure as described above, wherein according to FIG. 1 the transistors T ₁ , T ₂ are arranged emitter-coupled.

If only one transistor T _{1 is} produced, the surface contact layer can be produced by conventional metal vapor deposition or a sputtering process. This surface contact layer is quasi-planar in that the single-crystalline region 10 is only about the thickness of the oxide layer 2 deeper than the polycrystalline region 11 ( FIG. 2).

Do the transistors T ₁ , T _{2 have} a heterostructure?

• - a Si _x Ge _{1 - x} collector layer,
• - a Si _x Ge _{1 - x} base layer and
• - a Si emitter layer

or a double heterostructure with

• - a Si collector layer,
• - a Si _x Ge _{1 - x} base layer and
• - a Si emitter layer,

so the emitter efficiency can be increased by utilizing the emitter / base potential barrier. As a result, the doping of the semiconductor layer 6, 6 a ( FIG. 2), which forms the emitter layer, can be chosen so small (<10 ¹⁸ charge carriers per cm ³ ) that the polycrystalline semiconductor layer 6 a has a high specific resistance and as an insulator layer works. The 0⁺ ion implantation shown in FIG. 3 for producing the semi-insulating semiconductor layer 8 is omitted.

The invention is not limited to the embodiment described, for example, but it is also possible to produce stackable diodes, which in turn can be arranged three-dimensionally with bipolar transistors. The manufacturing process is simplified for the diodes, e.g. B. in the semiconductor structure shown in Fig. 1, the semiconductor layers 6, 8 are omitted.

In addition to Si and SiGe, there are other semiconductor materials rialien, z. B. III / V compound semiconductors, for production suitable stackable semiconductor components can be used.

Claims (10)

1. Stackable semiconductor components, formed in a semiconductor layer sequence epitaxially grown on a substrate, with single-crystal and polycrystalline regions, characterized in that

• - That the single-crystalline regions ( 10 ) of the semiconductor layer sequence contain the component layers ( 4, 5, 6 ), and
• -that a lateral contacting (A) of the component layers ( 4, 5, 6 ) via contact layers takes place in such a way that the contact layers on the one hand between the component layers ( 4, 5, 6 ) have been grown and from be richly monocrystalline and polycrystalline metal semiconductor layers ( 3, 3 a , 9, 9 a) exist and on the other hand adjoin the component layers ( 4, 5, 6 ) laterally and consist of conductive polycrystalline semiconductor layers ( 5 b) ( Fig. 1).

2. Stackable semiconductor components according to claim 1, characterized in that

• - that an oxide layer (2) on the substrate (1) over the entire surface, the appropriate oxide window contains (2 a), so that the substrate (1) window in the oxide is (2 a) is free, and
• - That the subsequently applied semiconductor layers and metal semiconductor layers on the substrate ( 1 ) grow single-crystal and on the oxide layer ( 2 ) polycrystalline lin, such that result in sharply delimited single-crystal regions ( 10 ) and polycrystalline regions ( 11 ) in the semiconductor layers.

3. Stackable semiconductor components according to one of the preceding claims, characterized in that the contact layers in the polycrystalline region ( 11 ) by semi-insulating, polycrystalline semiconductor layers ( 4 a , 8 ) are separated ( Fig. 1). 4. Stackable semiconductor components according to one of the preceding claims, characterized in that the component layers ( 4, 5, 6 ) have the same lateral dimensions. 5. Stackable semiconductor components according to one of the preceding claims, characterized in that the component layers ( 4, 5, 6 ) are structured such that bipolar and / or heterobipolar transistors and / or diodes can be produced. 6. Stackable semiconductor components according to one of the preceding claims, characterized in that

• that at least two bipolar and / or heterobipolar transistors are arranged in an emitter-coupled manner vertically to the semiconductor layer sequence,
• - That the contacting of the emitter layers ( 6 ) and the collector layers ( 4 ) via metal semiconductor layers ( 3, 3 a , 9, 9 a) , and
• - That the base layers ( 5 ) can be contacted laterally via conductive, polycrystalline semiconductor layers ( 5 b) .

7. Stackable semiconductor devices according to one of the above forthcoming claims, characterized in that the Bipolar transistors and / or diodes made of Si layers are building. 8. Stackable semiconductor devices according to one of the before forthcoming claims, characterized in that the Heterobipolar transistors made of Si and SiGe layers are built. 9. Stackable semiconductor components according to one of the preceding claims, characterized in that the metal semiconductor layers ( 3, 3 a , 9, 9 a) consist of NiSi₂, or CoSi ₂ . 10. Stackable semiconductor devices according to one of the previously outgoing claims, characterized in that from the stackable semiconductor devices three-dimensional scarf are producible.