DE3740762A1 - DATA PROCESSING SYSTEM WITH AN EXTERNAL INTERFACE - Google Patents

Abstract

A method for monitoring the sequence of instructions executed by a central processing unit. When a branch instruction is executed, the central processing unit generates a representative interface signal. When a jump instruction is executed or an exception occurs, the central processing unit displays representative information on the external memory interface. <IMAGE>

Description

The present invention relates to a Data processing system and in particular a method for Monitoring of those carried out by a microprocessor Command sequences without hindering operation.

A microprocessor is only useful if System developers have the ability to use the microprocessor too used for troubleshooting. The system developer must be in the Be able to operate the system under development to observe differences between system operation and the determine the defined functional description and the system then change according to the functional description.

An important aspect when monitoring operations of a system is the observance of command sequences, which by the Microprocessor can be performed. The system developer must be in be able to observe the sequence of commands executed without that the system slows down or the order of the normal System flow differs.

Microprocessors are usually designed so that the Control transfer from one command to the next by both Location and type of command executed as well is determined by whether there is an exception.

Exceptions are events, errors and special conditions such as trying to get an invalid command or one by one To execute the interrupt request reported to the peripheral device, that are recognized by the microprocessor.

Instructions executed by a microprocessor can be in divide into three groups: branch instructions, branch instructions and "other" commands.

"Jump" commands are the commands that the controller possibly passed on a command with a destination address, by adding a shift value that is currently in a current command was encoded with the address of the current one running command is calculated. Jump commands can have "unconditional" or "conditional" character; with the latter conducted a test to determine if a specific Condition regarding the state of the microprocessor is true.

A jump command is "recorded" if it is unconditional or is conditioned and the specific condition is true.

"Branch instructions" are the instructions that the controller possibly passed on a command with a destination address, their calculation generally from the definition of the particular Command depends. Examples of common branch instructions are "RETURN" - Transfer of control to one of the top of the stack Memory read address - and "CASE" - transfer of control to an address that is created by using an operand value Indexing to an address table in memory is determined. Like branch instructions, branch instructions can be "unconditional" or have "conditional" character and will be "picked up" if they are unconditional or conditional and the specific condition is true is.

A jump instruction differs from the branch instruction the fact that it is possible for jump commands, the destination address to calculate, even if only the coding and the space of the Command while the destination address is known Branch instructions usually depends on some data values, which can change like the content of a register or Storage space.

For microprocessors that do not have an integrated cache Memory or an on-chip memory management unit are the virtual addresses of all command and Data references in the external interface of the microprocessor contain. It is therefore an easy thing to do through the Sequence of microprocessors executed to track externally.

The National Semiconductor's NS 32032 microprocessor Corporation, for example, will be the next command after the Execution of a recorded jump or branch instruction with the help of a special status code from the destination address in the Read memory. The microprocessor also generates an Program run state interface signal when it is with the Execution of a new command begins. Therefore it is with Microprocessor NS 32032 possible, the sequence of executed commands monitor as follows:

• 1. For each jump or branch instruction recorded the destination address is available in the external interface Disposal;
• 2. After the execution of the recorded jump or Branch instruction is the program execution state Interface signal monitors to the command sequence determine the up to the consecutive memory addresses to execute the next recorded jump or the branch was executed; and
• 3. Read data from the memory locations that contain the addresses of the Exception utilities are stored in the external interface detected to determine if an exception has occurred.

In a microprocessor on which this invention is based, with integrated cache memory and circuit integrated Memory management unit are used to monitor the sequence executed commands to solve two problems. The first is in that since commands or data requested are in one circuit-integrated cache memory can be found not all memory references in the external interface of the Microprocessor are observable. This is on it due to the fact that there are memory references that are in the internal Cache of the microprocessor are located without reference to the external Memory to be performed. The second is based on that memory references that are in the external interface of the Microprocessors are observable, more virtual than physical Addresses are. The reason for this is that the integrated Memory management unit by an execution program converts generated virtual addresses into physical addresses, which are required for memory access. In some cases no 1: 1 conversion is carried out; d. i.e., more than one virtual address can be in a single physical address be implemented. In these cases it is impossible to virtual addresses of the memory references for an execution program only by observing the physical addresses of the Determine memory references in the external interface.

The method of the present invention for solving the im The problem described above involves two aspects. To the one indicates an additional interface signal, whether a with executing the command sequentially or not- is sequential. Second, additional information about the interface signals created for the external Memory references are used.

The additional of that in the description below The interface signal used for the explained microprocessor is that So called "Internal Sequential Fetch" (internal sequential On Demand (ISF). The microprocessor activates the ISF signal together with a "Program Flow Status" signal (PFS) as soon as a jump or branch instruction is recorded is performed. It is thus possible to increase the tax flow monitor when a jump or branch instruction is executed becomes. If the command is picked up, what by activating of the ISF signal, the control is switched to a Transfer target command. If the command is not included, what is indicated by the deactivation of the ISF signal, then control to the next sequential command in memory transfer.

More information on monitoring tax flow will be provided delivered in the external interface if an exception occurs or a recorded branch instruction is executed becomes. If an exception occurs, the microprocessor shows both a code that shows the type of exception, as well as the virtual address of the exception utility. If a recorded branch instruction is executed, the Microprocessor the virtual address of the destination of the branch.

The solution offered by the present invention Control flow control problem is extraordinary effective. Because only a new interface signal is required is, the cost is low. Since the interface signals for the Memory references are rarely used, are malfunctions with the external references of the microprocessor are unlikely, and the Performance is only marginally affected. Recorded Branch instructions typically take less than 10% of the executed commands. As a rule, exceptions occur with a Frequency of less than 1 per 100 commands. Therefore, the Use of interface signals to create additional ones Control flow monitoring information little Impact on microprocessor performance.

Exemplary embodiments are shown in the drawing:

Fig. 1 shows a schematic block diagram to illustrate the general architecture of a microprocessor which uses the control flow monitoring method on which this invention is based.

Fig. 2 shows a schematic diagram to illustrate the interface signal of the microprocessor described herein.

Fig. 3 shows a schematic block diagram to illustrate the important functional units and link buses of the microprocessor described herein.

Fig. 4 shows a schematic block diagram illustrating the structure of the instruction cache of the microprocessor described herein.

Fig. 5 shows a schematic block diagram to illustrate the structure of the data cache of the microprocessor described herein.

Fig. 6 shows a timing diagram illustrating a time sequence for access to the data cache of the microprocessor described herein.

Figure 7 is a timing diagram showing the relationship between the CLK input and BUSCLK outputs of the microprocessor described herein.

Figure 8 shows a timing diagram illustrating the simple read cycle of the microprocessor described herein.

Figure 9 shows a timing diagram illustrating the simple write cycle of the microprocessor described herein.

Fig. 10 shows a timing diagram to illustrate a read cycle of the microprocessor described herein, which has been extended by two wait cycles.

Figure 11 shows a timing diagram illustrating a sequence of three-transfer read cycles that is terminated by the microprocessor described herein.

Fig. 12 shows a timing diagram showing a sequence of read cycles ended by the system, the cycle comprising two transfers, the second of which has been extended by a wait status.

Figure 13 shows a schematic diagram illustrating the general structure of the 4-stage instruction pipeline of the microprocessor described herein.

Fig. 14 shows a timing diagram to show the timing in a pipeline for a hit in the internal data cache.

Fig. 15 shows a timing diagram to show the timing in a pipeline in the event of a mistake in the internal data cache.

Fig. 16 shows a timing diagram to show the effect of locking the address register on the timing of the command pipeline.

Figure 17 shows a timing diagram illustrating the effect of correctly predicting a jump instruction to be taken in the operation of the microprocessor described herein.

Fig. 18 shows a timing diagram to show the effect of an incorrect prediction of a resolution of a jump instruction to be taken in the operation of the microprocessor described herein.

Figure 1 shows the configuration of a microprocessor (CPU) 10 that includes a method for monitoring control flow in accordance with the present invention.

The central unit 10 initiates bus cycles in order to enter into dialogue with an external memory and with other devices in a computer group, to call up commands, to read and write data, to carry out floating point operations and to respond to exception requests.

The central processing unit 10 comprises a 4-stage instruction pipeline 12 , which is capable of executing up to 10 MIPS (millions of instructions per second) with a clock rate of 20 MHz. In addition, three memory buffers are integrated with the instruction pipeline 12 to support the high demand of the pipeline 12 for instructions and data. The memory buffers include a 512-byte instruction cache 14 , a 1024-byte data cache 16, and a 64-input conversion buffer that resides in an integrated memory management unit (MMU) 18 . The main functions of the MMU 18 lie in the decision about requirements for memory references and in the conversion of virtual into physical addresses. Central unit 10 also includes an integrated bus interface unit (BIU) 220 that controls the bus cycles of the external references.

Placing cache memory and memory management functions on the same chip with instruction pipeline 12 is an inexpensive and powerful technique by improving memory access time and bandwidth for any microprocessor application.

The central processing unit 10 is also compatible with the existing peripheral devices, such as an interrupt control unit (ICU) 24 (eg NS 32202). The ICU interface to the central unit 10 is completely asynchronous, so that the ICU 24 can be operated at lower frequencies than the central unit 10 .

The central processing unit 10 contains its own timer. Time control is therefore not necessary.

The central processing unit 10 supports both the external cache memory 25 and a "bus monitoring" circuit 26 which, as described below, supports the coherence of the internal cache memory.

As shown in Fig. 2, the CPU 10 114 has interface signals for bus timing and control, cache control, exception request, and other functions. The following list summarizes the interface signal functions of the central unit 10 :

Input signals

Bundled confirmation (bottom active signal).
When enabled to respond to a requested multiple data transfer, this signal indicates that the memory supports multiple data transfer cycles.

Bus error (signal active below).
Reports the central unit 10 that an error was detected during the current bus cycle.

Bus repetition (signal active below).
Reports the central unit 10 that the current bus cycle is to be repeated.

BW0-BW1 bus width (2 coded lines).
These lines determine the bus width (8, 16 or 32 bits) for each data transfer.
(See table 1)

Plate 1

• 1. Wenn der Mikroprozessor eine Ausnahme wahrnimmt, wird die Steuerung auf den ersten Befehl des entsprechenden Dienstprogramms für diese Art der Ausnahme übertragen. Abhängig von der Definition der Operation des Mikroprozessors sind Adresse und Speicher des Ausnahmedienstprogramms entweder festgelegt oder werden in einer Tabelle mit den Adressen solcher Dienstprogramme gefunden;
• 2. Führt der Mikroprozessor einen aufgenommenen Sprungbefehl aus, dann wird die Steuerung auf den Befehl übertragen, dessen Adresse im Speicher durch Addition des Versetzwertes im Sprungbefehl und der Adresse des Sprungbefehls berechnet wird;
• 3. Führt der Mikroprozessor einen aufgenommenen Verzweigungsbefehl aus, dann wird die Steuerung auf den Befehl übertragen, dessen Adresse im Speicher grundsätzlich entsprechend der Definition dieses einzelnen Befehls berechnet wird, und
• 4. Wenn der Mikroprozessor einen Befehl ausführt und keine der oben beschriebenen Regeln zutrifft, wird die Steuerung auf den Befehl übertragen, dessen Adresse im Speicher unmittelbar der des ausgeführten Befehls folgt.

Die Zentraleinheit 10 hat fünf Operationszustände zur Ausführung von Befehlen und Verarbeitung von Ausnahmen: Rückstellen, Ausführen des Befehls, Verarbeitung von Ausnahmen, Warten auf eine Unterbrechung und Anhalten. Während der Ausführung eines Befehls, sichert die Zentraleinheit, wenn sie eine Ausnahme erkennt, den Inhalt der entsprechenden Register, begint dann mit der Ausführung eines Ausnahmedienstprogramm. Ausnahmen sind Bedingungen, Ereignisse und Fehler, die zur Änderung einer Folge von Befehlsausführungen führen. Die Zentraleinheit 10 erkennt vier Ausnahmearten: Rückstellen, Bus-Fehler, Unterbrechungen und Traps. Eine Rückstell-Ausnahme tritt auf, wenn das -Signal aktiviert ist; wird zur Initialisierung der Zentraleinheit 10 eingesetzt. Eine Bus- Fehlerausnahme tritt auf, wenn das BER-Signal als Reaktion auf einen Befehlsabruf oder eine Datenübertragung aktiviert wird, die von der Zentraleinheit 10 zur Ausführung eines Befehls angefordert wurde. Eine Unterbrechung tritt auf als Reaktion auf ein durch die Aktivierung des NMI- oder INT-Signals gemeldetes Ereignis; Unterbrechungen werden in der Regel durch Peripheriegeräte angefordert, die den Abruf der Zentraleinheit 10 anfordern. Ein Trap tritt auf, wenn bestimmte Bedingungen, wie ein Teiler von 0, von der Zentraleinheit 10 während der Ausführung eines Befehls gefunden werden. Sobald das -Signal aktiviert ist, geht die Zentraleinheit 10 in den Rücksetzstatus über, in dem sie bleibt, bis inaktiv gemacht wird, worauf sie in den Zustand der Befehlsausführung übergeht. Während sich die Zentraleinheit 10 im Rücksetzzustand befindet, werden die Inhalte bestimmter eigener Register initialisiert. Solange sich die Zentraleinheit 10 im Zustand der Befehlsausführung befindet, setzt sie mit der Ausführung von Befehlen fort, bis eine Ausnahme erkannt oder ein "Warte"-Befehl ausgeführt wird. Wird eine Ausnahme, nicht aber eine Rücksetzung, erkant, geht die Zentraleinheit 10 in den Zustand der Verarbeitung einer Ausnahme über. Nach Ausführung des "Warte"- Befehls geht die Zentraleinheit 10 in den Wartezustand auf eine Unterbrechung über. Solange sich die Zentraleinheit 10 im Verarbeitungszustand einer Ausnahme befindet, speichert sie den Inhalt des entsprechenden Registers und liest den Befehlszähler und die Modulverbindungswerte, um mit der Ausführung des Ausnahmedienstprogramms zu beginnen. Zur Verarbeitung einer Unterbrechung liest die Zentraleinheit 10 zusätzlich ein oder zwei Vektorwerte von der ICU 24. Nach erfolgreicher Beendigung aller Datenbezüge, die zur Verarbeitung einer Ausnahme angefordert wurden, geht die Zentraleinheit 10 in den Zustand der Befehlsausführung über. Wenn jedoch ein Bus-Fehler oder ein Abbruch auf während die Zentraleinheit 10 eine Ausnahme verarbeitet, geht sie in den Haltezustand über. Während des Wartens auf eine Unterbrechung befindet sich die Zentraleinheit 10 im Ruhezustand. Ein eigener Status, der diesen Zustand identifiziert, wird auf der Systemschnittstelle dargestellt. Wenn eine Unterbrechung oder ein Fehlerbeseitigungszustand wahrgenommen wird, wechselt die Zentraleinheit 10 in den Zustand der Ausnahmeverarbeitung. In den Haltezustand wechselt die Zentraleinheit 10 dann, wenn ein Bus-Fehler oder ein Abbruch wahrgenommen wird, während sie eine Ausnahme verarbeitet und verhindert dadurch den Übergang der Steuerung an ein entsprechendes Ausnahmedienstprogramm. Ein eigener Status zur Kennzeichnung dieses Zustands wird an der Systemschnittstelle dargestellt. Die Zentraleinheit 10 führt die folgenden Operationen zur Ausführung eines Befehls aus: Abrufen des Befehls;
Lesen der Quelloperanden, falls vorhanden;
Berechnen der Ergebnisse;
Schreiben der Ergebnisoperanden, falls vorhanden;
Änderung der Fehlermarkierungen, falls erforderlich; und
Aktualisierung des Befehlszählers. In den meisten Fällen führt die Zentraleinheit 10 Befehle durch Abarbeitung der oben aufgeführten Operationen in einer strikten Folge zunächst für einen Befehl aus, um erst dann mit dem nächsten Befehl zu beginnen. Wie oben beschrieben, können jedoch Ausnahmen die Folge von Operationen zur Ausführung eines Befehls oder zum Übergang von einem Befehl auf den nächsten ändern. Ebenso, bei einer erweiterten Leistung, überlappt die Zentraleinheit 10 die Operationen zur Ausführung einiger Befehle in Parallelbearbeitung. Die folgenden Ausführungen erläutern die Auswirkungen von Ausnahmen in der Pipeline 12 auf die Befehlsausführung. Im folgenden werden abgelesene Adressen aus dem Speicher zur Berechnung der effektiven Adressen für speicherbezogene und externe Adressierarten als Quelloperanden angesehen, auch wenn die effektive Adresse für einen Operanden mit schreibfähigem Zugriff (with access class of write) berechnet wird. Die Zentraleinheit 10 prüft an verschiedenen Stellen während der Befehlsausführung auf Ausnahmen. Wird eine Ausnahme wahrgenommen, dann endet der in der Ausführung befindliche Befehl auf eine von vier möglichen Arten: er wird abgeschlossen, angehalten, beendet oder teilweise beendet. Jede der vier Ausnahmearten führt zu einer eigenen Beendigung. Wird eine Ausnahme nach abgeschlossener Durchführung eines Befehls wahrgenommen, hat die Zentraleinheit 10 alle Operationen für diesen Befehl und für alle anderen nach dem Auftreten der letzten Ausnahme ausgeführten Befehle ausgeführt. Ergebnisoperanden wurden geschrieben, Fehlermarkierungen wurden geändert und der auf dem Unterbrechungsstapel gespeicherte Befehlszählerwert enthält die Adresse des nächsten auszuführenden Befehls. Das Ausnahmedienstprogramm kann bei seinem Abschluß einen entsprechenden Rücksprungbefehl ausführen, worauf die Zentraleinheit 10 mit der Ausführung des dem abgeschlossenen Befehl folgenden Befehls beginnt. Ein Befehl wird angehalten, wenn während der Ausführung des Befehls einer der unterschiedlichen Trap-Zustände oder ein wiederanlauffähiger Bus-Fehler wahrgenommen wird. Ein ausgesetzter Befehl wurde nicht abgeschlossen, jedoch wurden alle anderen nach dem Auftritt der letzten Ausnahme ausgeführten Befehle abgeschlossen. Die Ergebnis-Operanden und durch den Befehl auszuführenden Markierungen können geändert worden sein, jedoch können nur solche Änderungen auftreten, die die erneute Ausführung und den Abschluß des Befehls ermöglichen. Bei bestimmten Ausnahmen (z. B. Bus-Fehlern und Abbrüchen, nichtdefinierter Befehl und unzulässige Operationsmarkierungen) hebt die Zentraleinheit 10 die entsprechende Steuermarkierung im Programmstatusregister auf, bevor die Kopie sichergestellt wird, die auf den Unterbrechungsstapel geschoben wird. Der auf dem Unterbrechungsstapel sichergestellte Befehlszählerwert enthält die Adresse des ausgesetzten Befehls. Ein RESTORE-Befehl zum Beispiel nimmt bis zu acht allgemeine Register vom Stapel. Wird auf einem der Bezüge auf dem Stapel eine ungültige Seitentabellen-Eingabe wahrgenommen, wird der Befehl ausgesetzt. Die allgemeinen Register, die durch den Befehl geladen werden sollen, können geändert worden sein, aber der Stapelzeiger zeigt immer noch den Wert, den er hatte, als dieser Befehl begann. Zum Abschluß eines ausgesetzten Befehls geht das Ausnahmedienstprogramm nach einem von zwei möglichen Vorgängen vor:

• 1. Das Dienstprogramm kann die Ausführung der ausgesetzten Befehle simulieren. Nach der Berechnung und dem Schreiben der Befehlsergebnisse werden die auf dem Unterbrechungsstapel gespeicherte Markierungen in der Kopie des Programmstatusregisters geändert, und der auf dem Unterbrechungsstapel gespeicherte Befehlszählerwert wird aktualisiert, um auf den nächsten auszuführenden Befehl zu zeigen. Das Dienstprogramm führt dann einen entsprechenden Rücksprungbefehl aus, und die Zentraleinheit 10 beginnt mit der Ausführung des dem ausgesetzten Befehl folgenden Befehls. Dieser Vorgang findet dann statt, wenn die Gleitpunktbefehle durch die Software solcher Systeme simuliert werden, die keine Hardware-Gleitpunkteinheit haben.
• 2. Ein ausgesetzter Befehl kann erneut ausgeführt werden, nachdem das Dienstprogramm den Trap-Zustand beseitigt hat, der zur Aussetzung des Befehls führte. Das Dienstprogramm führt bei seiner Beendigung einen entsprechenden Rücksprungbefehl aus. Hiernach beginnt die Zentraleinheit 10 erneut mit der Ausführung des ausgesetzten Befehls.

Obwohl die Zentraleinheit 10 eine erneute Ausführung und Beendigung eines ausgesetzten Befehls ermöglicht, kann sie einen Quelloperanden oder den Befehl von einem speicherzugeordneten Peripheriekanal gelesen haben, bevor die Ausnahme wahrgenommen wurde. In einem solchen Fall kann die Kennlinie des Peripheriegeräts eine korrekte erneute Ausführung des Befehls verhindern. Ein in der Ausführung befindlicher Befehl ist beendet, wenn er zurückgesetzt wird oder wenn ein nicht wiederanlauffähiger Bus- Fehler auftritt. Alle durch den Befehl auszuführenden Ergebnisoperanden und Markierungen sind undefiniert wie der Inhalt des Befehlszählers. Die Ergebnisoperanden anderer seit der letzten Serienoperation ausgeführten Befehle sind möglicherweise nicht in den Speicher geschrieben worden. Ein beendeter Befehl kann nicht abgeschlossen werden. Wird ein wiederanlauffähiger Busfehler, eine Unterbrechung, ein Abbruch oder ein Test-Zustand während der Ausführung eines Kettenbefehls wahrgenommen, soll der Befehl teilweise abgeschlossen werden. Ein teilweise abgeschlossener Befehl wurde nicht abgeschlossen, jedoch wurden alle anderen seit der letzten Ausnahme ausgeführten Befehle abgeschlossen. Durch den Befehl auszuführende Ergebnisoperanden und Markierungen können geändert worden sein, aber der in den Stream-Zeigern und anderen während der Befehlsausführung benutzten allgemeinen Registern gespeicherte Wert ermöglicht die erneute Ausführung und den Abschluß des Befehls. Der im Unterbrechungsstapel gespeicherte Befehlszählerwert enthält die Adresse des teilweise abgeschlossenen Befehls. Bei der Beendigung kann das Ausnahmedienstprogramm den entsprechenden Rücksetzbefehl einfach ausführen, und die Zentraleinheit 10 setzt mit der Ausführung des teilweise abgeschlossenen Befehls fort. Wie bereits beschrieben, überlappt die Zentraleinheit 10 die Operationen zur gleichzeitigen Ausführung mehrerer Befehle in der 4stufigen Pipeline 12. Die allgemeine Struktur der Pipeline 12 wird in der Abb. 13 gezeigt. Während die Ausführungseinheit 32 die Ergebnisse für einen Befehl berechnet, kann die Adresseneinheit 30 die effektiven Adressen berechnen und die Quelloperanden für den folgenden Befehl lesen, während der Programmlader 28 einen dritten Befehl entschlüsseln und einen vierten in seine 8-Byte- Schlange vorausholen kann. In bestimmten Fällen können die Auswirkungen überlappter Befehlsausführung von denen der Ausführung eines Befehls in streng sequentieller Folge abweichen. Genauer noch, die von der Zentraleinheit 10 ausgeführte Reihenfolge von Speicherbezügen kann scheinbar differieren. Während der Ausführung eines Befehls kann die Zentraleinheit 10 einige der Quelloperanden aus dem Speicher lesen bevor der Befehl vollständig abgerufen wird. Die Zentraleinheit 10 schließt das Abrufen eines Befehls und das Lesen der Quelloperanden jedoch immer ab, bevor ihre Ergebnisse geschrieben werden. Muß mehr als ein Quelloperand aus dem Speicher zur Ausführung eines Befehls gelesen werden, dann können diese Operanden in jeder beliebigen Reihenfolge gelesen werden. Operanden können auch in beliebiger Reihenfolge geschrieben werden, wenn mehr als ein Ergebnisoperand zur Ausführung eines Befehls in den Speicher gelesen werden soll. Die Zentraleinheit 10 beginnt mit dem Abrufen eines Befehls erst nachdem alle vorangegangenen Befehle vollständig abgerufen wurden. Die Zentraleinheit 10 kann jedoch mit dem Abrufen eines Befehls beginnen, bevor alle Quelloperanden gelesen und die Ergebnisse für vorangegangene Befehle geschrieben worden sind. Die Zentraleinheit 10 beginnt mit dem Lesen der Quelloperanden für einen Befehl erst nachdem alle vorangegangenen Befehle abgerufen wurden und ihre Quelloperanden gelesen wurden. Der Quelloperand für einen Befehl kann gelesen werden, bevor alle Ergebnisse des vorangegangenen Befehls geschrieben wurden, es sei denn, daß der Wert der Quelloperanden von dem noch nicht geschriebenen Ergebnis abhängig ist. Die Zentraleinheit 10 vergleicht die physikalische Adresse nach der Länge des Quelloperanden mit denen der noch nicht geschriebenen Ergebnisse und verzögert das Lesen des Quelloperanden bis alle Ergebnisse, von denen der Quelloperand abhängig ist, geschrieben wurden. Desweiteren identifiziert die Zentraleinheit 10 Quelloperanden, die sich in speicherzugeordneten Peripheriekanälen befinden und verzögert das Lesen dieser Operanden bis alle vorherigen Ergebnisse für die speicherzugeordneten Peripheriekanäle geschrieben wurden. Eigene Arbeitsprogramme stellen sicher, daß das Lese- und Schreib-Bezüge zu speicherzugeordneten E/A-Kanälen stets in der durch das Programm vorgegebenen Reihenfolge ausgeführt werden. Diese Abläufe werden in der gleichzeitig anhängigen und gemeinsam eingebrachten US Patentanmeldung Nr. 006.012 "Verfahren zur Wahrnehmung und Bearbeitung speicherzugeordneter E/A durch einen Pipeline- Mikroprozessor" von Levy et al. behandelt und auf die hier Bezug genommen wird. Die Zentraleinheit 10 beginnt mit dem Schreiben der Ergebnisoperanden für einen Befehl erst nachdem alle Ergebnisse der vorangegangenen Befehle geschrieben wurden. Aufgrund der Überlappung der Operationen für einige Befehle kann die Zentraleinheit 10 einen Befehl abrufen und seine Quelloperanden lesen, obwohl der Befehl nicht ausgeführt wird (z. B., wenn der vorangegangene Befehl einen Trap verursacht). Dennoch, wenn die Zentraleinheit 10 einen Quelloperand für einen Befehl in einem speicherzugeordneten Peripheriekanal wahrnimmt, liest sie den Quelloperanden nur, wenn der Befehl ausgeführt wird. Zu beachten ist, daß die Zentraleinheit 10 nicht auf Abhängigkeiten zwischen dem Abrufen eines Befehls und dem Schreiben vorangegangener Befehlsergebnisse prüft. Daher muß ein Selbständerungs-Code speziell zur geplanten Ausführung behandelt werden. Nach der Ausführung bestimmter Befehle oder nach der Bearbeitung einer Ausnahme bringt die Zentraleinheit 10 die Ausführung von Befehlen in eine serielle Form. Die Serialisierung der Ausführung von Befehlen bedeutet, daß die Zentraleinheit 10 das Schreiben aller Ergebnisse vorangegangene Befehle in den Speicher abschließt, dann mit dem Abruf und der Ausführung des nächsten Befehls beginnt. Wenn also ein neuer Wert in das Programmstatus-Register geladen wird, bestimmt der neue Wert des Programmstatus-Registers den Privilegstatus, der zum Abrufen und Ausführen des nächsten Befehls verwendet wird. Gemäß der hier vorliegenden Erfindung beinhaltet die Zentraleinheit 10 ein 2stufiges Programm zur Überwachung der Folge ausgeführter Befehle. Die erste Stufe bildet ein zusätzliches Schnittstellensignal, das anzeigt, ob ein Befehl, dessen Ausführung beginnt, sequentiell oder nicht-sequentiell ist. Zweitens wird auf den Schnittstellensignalen eine zusätzliche Information geliefert, die für externe Speicherbezüge benutzt wird. Das Schnittstellensignal wird "Internal Sequential Fetch" (ISF) (interner sequentieller Abruf) genannt. Die Zentraleinheit 10 aktiviert das ISF-Signal zusammen mit einem Programmablaufstatus-Signal, sobald ein aufgenommener Sprung- oder Verzweigungsbefehl ausgeführt wird. Im Zusammenhang mit der hier vorliegenden Erfindung muß nur die Zentraleinheit 10 das ISF- Signal für aufgenommene Sprungbefehle aktivieren. Es ist daher möglich, den Steuerfluß zu überwachen, wenn ein Sprungbefehl ausgeführt wird. Wenn der Sprungbefehl aufgenommen ist, was durch Aktivierung des ISF-Signals angezeigt wird, wird die Steuerung auf einen Zielbefehl übertragen, dessen Adresse berechnet werden kann, da die Kodierung und Adresse des Sprungbefehls bekannt sind. Wenn der Sprung nicht aufgenommen wird, was durch Inaktivierung des ISF-Signals angezeigt wird, wird die Steuerung auf den dem im Speicher befindlichen Sprungbefehl folgenden Befehl übertragen. Weitere Informationen zur Überwachung des Steuerflusses werden nur dann in der Schnittstelle des externen Speichers angezeigt, wenn ein aufgenommener Verzweigungsbefehl ausgeführt wird oder eine Ausnahme auftritt. Tritt eine Ausnahme auf, zeigt die Zentraleinheit 10 sowohl einen Kode, der die Art der Ausführung nennt, sowie die virtuelle Adresse des Ausnahmedienstprogramms an. Wenn ein aufgenommener Verzweigungsbefehl ausgeführt wird, zeigt die Zentraleinheit 10 die virtuelle Adresse des Sprungziels an. Die Zieladresse wird angezeigt, nachdem die Zentraleinheit 10 mit dem Abrufen des Befehls am Sprungziel begonnen hat. Die Speicherschnittstelle befindet sich zu diesem Zeitpunkt in der Regel im Ruhezustand, während die Zentraleinheit 10 dekodiert und die Ausführung eines Befehls am Verzweigungsziel vorbereitet. Über die Status-Informationen gibt die Zentraleinheit 10 an, wenn sie entweder den Kode für eine Ausnahme oder die Zieladresse für einen aufgenommenen Verzweigungsbefehl anzeigt, eher als daß ein Bezug zum Speicher hergestellt wird. Die Adresseinheit 30 und die Ausführungseinheit 32 können Befehle mit einer Höchstfrequenz von zwei Zyklen pro Befehl verarbeiten. Der Programmlader 28 verarbeitet Befehle mit einer Höchstfrequenz von einem Zyklus pro Befehl, so daß er die Adresseneinheit 30 und an die Ausführungseinheit 32 ständig mit Befehlen versorgt. Der Programmlader 28 unterbricht den Durchsatz der Pipeline 12 nur dann, wenn der Befehlsstrom durch einen Sprungbefehl oder eine Verfehlung des Befehls-Cache unterbrochen wird. Die Abb. 14 zeigt die Ausführung von zwei Speicher-an- Register Befehlen durch die Adresseinheit 30 und die Ausführungseinheit 32. Die Zentraleinheit 10 kann bei den meisten üblichen Befehlen eine Ausführungsrate von zwei Zyklen aufrechterhalten und zeigt Verzögerungen nur in folgenden Fällen:

• 1. Speicherverzögerungen durch Cache- und Übertragungspuffer- Verfehlungen und nicht-ausgerichtete Bezüge.
• 2. Ressourcen-Konkurrenz zwischen Zuständen der Befehls- Pipeline 12.
• 3. Sprünge oder andere nicht-sequentielle Befehlsabrufe.
• 4. Komplexe Adressier-Modi, wie skalierter Index und komplexe Operationen, wie Teilung.

Die Abb. 15 zeigt die Auswirkung einer Verfehlung des Daten- Cache 16 auf den Zeitablauf der Pipeline 12. Die Ausführungseinheit 32 wird um zwei Zyklen verzögert bis die BIU 20 den Buszyklus zum Lesen der Daten abgeschlossen hat. Abb. 16 zeigt die Auswirkung einer Adreß- Registerverriegelung auf den Zeitablauf der Pipeline 12: ein Befehl ändert ein Register, während der nächste Befehl dieses Register zur Berechnung einer Adresse benutzt. Die Adresseneinheit 30 wird um drei Zyklen verzögert bis die Ausführungseinheit 32 die Aktualisierung des Registers abschließt. Hier ist anzumerken, daß, wenn der zweite Befehl das Register nicht zur Adressenberechnung (z. B. ADDD R0, R1), sondern für einen Datenwert benutzen würde, dann würde der Umgehungsschaltkreis in der Ausführungseinheit 32 zur Verhinderung einer Verzögerung zur Pipeline 12 benutzt. Der Programmlader 28 umfaßt spezielle Schaltkreise zur Behandlung von Sprungbefehlen. Wird ein Sprungbefehl dekodiert, berechnet der Programmlader 28 die Zieladresse und wählt zwischen sequentiellen und nicht-sequentiellen Befehlsströmen aus. Die Auswahl basiert auf der Sprung-Bedingung und -Richtung. Wenn der Programmlader 28 voraussagt, daß ein Sprung aufgenommen wird, wird die Zieladresse auf dem JBUS auf den Befehls-Cache 14 übertragen. Ob die Aufnahme eines Sprungs vorausgesagt wird oder nicht, der Programmlader 28 speichert die Adresse des wechselnden Befehlsstroms. Danach erreicht der Sprungbefehl die Ausführungseinheit 32, in der die Bedingung aufgelöst wird. Die Ausführungseinheit 32 meldet dem Programmlader 28, ob eine Verzweigung aufgenommen wurde oder nicht. Wenn die Verzweigung unkorrekt vorausgesagt, wird die Pipeline 12 gelöscht, und der Befehls-Cache 14 beginnt mit der Vorholung von Befehlen aus dem richtigen Strom. Die Abb. 17 zeigt die Auswirkung der korrekten Vorhersage eines aufzunehmenden Sprungbefehls. Eine Lücke von zwei Zyklen tritt beim Dekodieren von Befehlen durch den Programmlader 28 auf. Diese Lücke an der Spitze der Pipeline 12 kann häufig geschlossen werden, da ein vollständig dekodierter Befehl zwischen Programmlader 28 und Adresseneinheit 30 gepuffert wird, und weil andere Verzögerungen gleichzeitig in späteren Stufen in der Pipeline 12 auftreten können. Die Abb. 18 zeigt die Auswirkung der unkorrekten Voraussage einer Auflösung eines Sprungbefehls. Eine Lücke von vier Zyklen tritt in der Ausführungseinheit 32 auf. Weitere Informationen zum Arbeitsablauf der Zentraleinheit 10 finden Sie in der gleichzeitig anhängigen und gemeinsam eingebrachten US-Patentanmeldung Nr. 006.016 "Hochleistungs- Mikroprozessor", die gleichzeitig von Alpert et al. eingereicht wurde und auf die hier bezug genommen wird. Es ist darauf hinzuweisen, daß auch alternative Formen zu der hier dargestellten Form zur Durchführung der hier vorliegenden Erfindung anwendbar sind. Dabei ist der allgemeine Grundgedanke des Verfahrens zur Überwachung der von einer Zentraleinheit ausgeführten Befehle: Wenn ein Sprungbefehl ausgeführt wird, erzeugt die Zentraleinheit ein kennzeichnendes Schnittstellensignal und wenn ein Verzweigungsbefehl ausgeführt wird, zeigt die Zentraleinheit eine kennzeichnende Information an der externen Speicherschnittstelle.CIA0-CIA6 cache invalid address (7 encoded Cables).
The cache invalidation address is on the CIA bus. Table 2 shows that for each of the internal cache memory of the central processing unit10th relevant CIA lines.
CIICache memory inhibition On (active above Signal).
Reports the central unit10th, that the Deduction of the current bus cycle not is concealable. Cache invalidation released.
Input that determines whether the external cache invalid or Test operation were triggered. CLK clock
Input clock to derive all Time sequences for the central unit10th. Troubleshooting request (falling Edge activated).
By transitioning this signal from high to The trap (DBG) is triggered low. Bracket (active signal) Asks the central unit10th on the bus for the direct memory access unit (DMA) or release the multiprocessor system. Interruption (signal active below)
Maskable interrupt request Invalidate a sentence (bottom active Signal).
Only one sentence in the bottom becomes active Integrated cache memory invalid; the whole cache becomes active Memory invalid. Invalidate a data cache (active signal below).
Below active an invalidation takes place in the Data cache instead. Invalidate an instruction cache (active signal below).
Below active an invalidation takes place in the Command cache instead. I / O decoding (bottom active signal).
Reports the central unit10th, the existence Peripheral device through the current bus cycle is addressed. Unmaskable interruption (falling Edge activated).
By moving the signal from the top to the top below will be an unmaskable Interruption requested. RDY Ready (top active signal).
As long as this signal is inactive, extended the central unit10th the current bus cycle to support slow memory or peripheral device. Reset (signal active below).
Resets exception exceptions Initialization of the central unit10th out. Secondary device finished (active signal below).
Reports the central unit10th, the existence Auxiliary processor executing a command has ended. Slacetrap (active signal below).
Reports the central unit10ththat a slave Processor while executing an instruction has detected a trap condition. Output signals A0-A31 Address bus (3-stage, 32 lines).
Transmits the 32-bit address during a Bus cycle. A0 transmits the least significant Bit. Trigger for address transfer (bottom active Signal, 3-stage).
Reports that the bus cycle has started and that a valid address on the address bus located. Byte enable (bottom active signal, 3 levels, 4 lines).
Signals to release transmission to everyone Bytes in the data bus, as in Table 3 shown. Table 3 Start of the save process (bottom active Signal, 3-stage).
Reports that the current bus cycle is valid, d. H. that the bus cycle has not been canceled; available in the bus cycle rather than a conditional program stop (bottom active Signal).
Reports that the central processing unit10th a Detected troubleshooting condition Request multiple data transfer (bottom active signal, 3 levels).
Reports that the central processing unit10th the Execution of a multiple data transfer requests. BUSCLKBus clock.
Output clock for the bus time sequence. CASECCache area (3 levels).
For concealable data reading bus cycles
Shows the area of the integrated circuit Data cache18th where the data is arranged will. CIOInhibition of the cache memory (top active Signal).
Information from the central unit10th, that the Memory reference of the current bus cycle is not is concealable; controlled by the CI bit in level 2 side panel entry. Confirmation of the bus cycle (bottom active Signal, 3-stage). Reports that a triggered by Bus cycle is valid; d. H. that the bus cycle was not deleted. Data direction On (bottom active signal, 3- staged).
Shows the direction of data transfer the data bus; down active during a Bus cycle indicates that the central processing unit10th Reads data, top active during a Bus cycle indicates that the central processing unit10th Writes data. Confirmation of the stop (bottom active signal).
Activated by the central unit10th as Answer to the 1 input to indicate that the central unit10th released the bus Has. Locked bus cycle (active signal below).
Reports that a sequence of bus cycles with Locking protection is running. I / O inhibition (bottom active signal).
Reports that the current bus cycle is ignored should be if a peripheral is addressed. Internal sequential polling. Simultaneously with the signal indicates that the command that begins execution sequential (ISF = bottom active) or non- is sequential (= top active). Program execution status (bottom active signal).
A pulse at this signal shows the beginning execution of each command. Slave processor control (bottom active Signal).
Data strobe for the slave processor Bus cycles. ST0-ST4 status (5 coded lines).
Bus cycle status code; STO is that least significant bit. The coding is in the Table 4 shown. U / user / control program (3-stage).
Shows user (U / = top active) or Control mode (U / = bottom active) on. Dialogue signals D0-D31 data bus (3-stage, 32 lines).
Transmits 8, 16 or 32 bits of data during of a bus cycle. D0 transmits that least significant bit. Table 4 The in theFig. 3 central unit shown10th is like internally eight main functional units organized to carry out the following operations to execute instructions in parallel operate; Prefetching, decoding, calculation more effectively Addressing and reading the source operands, calculating the results and save in the registers, save the results in the Storage. A loader28 fetches the commands beforehand and decodes them them for use by an address unit30th and a Execution unit32. The loader28 transfers the from the Instruction cache14 commands received on the IBUS bus in an 8- Bit command queue. The loader28 can occur in every cycle Query the command field, where with "field" either an operation code (1-3 bytes including the type of addressing), an adjustment value or a direct value is meant. The loader 28 decodes the operation code to generate the Initial microcode address sent to the LADR bus Execution unit32 is directed. The decoded general Addressing types become an address unit via the ADMS bus 30th headed. The adjustment values are routed via the DISP bus. Direct values are available on the GCBUS bus. The Loader28 also includes one Branch prediction facility, which in the further course of the Text is described. The addressing unit20th calculates the effective addresses Using its own 32-bit adder and reading source operands for the execution unit32. The addressing unit30th controls the Channel from a register block34 to the GCBUS, through the basic and Index values for the address adder and data values for the Execution unit32 be transmitted. Effective addresses for Operand references are on the GVA bus, bus for virtual Addresses, to the memory management unit MMU18th and for data Cache16 transmitted. The execution unit32 contains the data path as well as the microcoded control for executing commands and Processing exceptions. This data path comprises a 32 bit Arithmetic logic unit ALU, a 32-bit Multiposition shifter, an 8-bit priority encoder as well as a number of counters. Special in which Execution unit32 built-in hardware supports the Multiplication by withdrawing one bit per cycle by Optimization for multipliers with a low absolute value. The execution unit32 controls a channel to Register block34 from the GNA bus on which they get the results saves. The execution unit32 also uses the GNA bus for Read values from a number of certain registers, such as a Configuration register or an interrupt-based register that itself in a register block34 are located. Through the data buffer with 2 inputs is the execution unit32 able to Execution of a command with the saving of results in Overlap memory for previous commands. The GVA bus will from the execution unit32 used to store references for complex commands (e.g. chain operations) and for processing To make exceptions. The register block34 has two channels that have read access by the address unit30th on the GCBUS and a read / write Access by the execution unit32 possible on the GNA bus do. The register block34 contains general registers, registers for specific purposes and program counts for the address unit 30th and the execution unit32. The memory management unit MMU18th is with the Central unit memory management functions10th compatible. The instruction cache14, the address unit30th and the Execution unit32 address requirements to the Memory management unit MMU20th for memory references. The MMU18th organizes the requests and grants access to the Transfer of virtual addresses on the GVA bus. The MMU18th translates the virtual address it received on the GVA bus with the help of their internal 64-input transmission buffer corresponding physical address. It transmits the physical address on the MPA bus to either the instruction cache 14 or the data cache16, which depends on whether a command or a data reference is carried out. The physical address also becomes the BIU bus interface unit20th for an external Transfer bus cycle. The bus interface unit (BIU)20th controls the bus cycles for references through the instruction cache14, the address unit30th and the execution unit32. The BIU bus interface unit20th includes a buffer with 3 inputs for external references. Thereby can the BIU20th e.g. B. a bus cycle for calling commands the data for another bus cycle to Write can be kept in memory and at the same time the next read data can be transferred. The IndianFig. 4 instruction cache shown14 stores 512 Bytes in a direct overview management. The bits6 to8th a reference command address control 1 to 8 sets. Every set contains 16 bytes, i. H. 4 double words from code and protocol, the the address identifier with the 23 most significant bits of the physical address for the places saved in this set contains. A valid bit is assigned to each double word. The instruction cache14 also includes a 16 byte Command buffer, from which 32-bit codes per cycle on the IBUS to Loader28 can be transferred. If the one you want Command in the command cache14 is found ("hit"), the Command buffer from the driven set of the command cache14 loaded. In the event of a miss, the instruction cache transfers14 the Address of the missing double word via the GVA bus to the MMU18th, which is the address for the BIU20th translated. The BIU20th solve one Multiple read cycle to remove the command buffer from the external Load memory over the GBDI bus. The command buffer is then on one of the sets of the instruction cache14 written. The instruction cache14 includes counters for both virtual as well as for physical addresses, the next of which Double word of the command stream should be retrieved beforehand. Must the Instruction cache14 with the prefetch of a new command stream then the virtual address of the new stream will start from Loader28 transferred to the JBUS. When transitioning to a command cache transfers new page14 the virtual address on a GVA bus to the MMU18th and then receives the physical address on the MPA bus. The instruction cache14 supports an operation mode for Lock its content in designated places. this function is set by setting a lock instruction cache (LIC) bit in the Configuration register released. Allowed in real-time systems fast and integrated access to the most critical processes. The instruction cache14 is set an instruction cache enable (IC) bit in the configuration register Approved. The data cache16 stores 1024 bytes of data in one Two-way sub-associative organization, as in theFig. 5 shown. Each set has two inputs with 16 bytes and two Identifiers representing the 23 most significant bits of the physical address for the positions stored in the two inputs. A valid bit is assigned to each double word. The time control for the data cache access16 is in the Fig. 6 shown. Here are the virtual ones first Address bits4th to8th on the GVA bus to control the corresponding sets within the data cache16 and reading the both inputs used. The MMU also translates18th the virtual address and transfers the physical address to the Data cache16 and the BIU20th on the MPA bus. Then he compares Data cache16 the two address identifiers with the physical ones Addresses while the BIU20th an external bus cycle for reading which triggers data from external storage. Is the reference one Hits, then the selected data will be Cache16 aligned and on the GDATA bus to the execution unit 32 transferred, and the BIU20th removes the external bus cycle does not control the BMT and signals. Is the reference a misconduct, then the BIU completes20th the external Bus cycle and transfers data from external memory to Execution unit32 and the data cache16that its cache Input updated. In the case of references that meet, the data Cache16 a throughput of one double word per cycle with one Support latency of 1.5 cycles. The data cache16 is a carbonless cache. At The data cache checks memory write references16whether the reference is a Hit is. If so, the cache content is updated. At BIU will write a hit or a misconduct20th the Data through to external storage. Like the instruction cache14, supports the data cache16 an operation mode to lock its content fixed places. This function is activated by setting a data Cache lock bits (LDC) in the configuration register Approved. In real-time systems, this allows fast and Integrated circuit access to most critical Processes. The data cache16 by setting a data Cache enable bits (DC) enabled in the configuration register will. The central unit10th receives a single phase input Clock CLK, whose frequency is twice as high as that Operating frequency of the central unit10th. The frequency of the input Clock is z. B. at 40 MHz for a central unit10th, the works at 20 MHz. The central unit10th shares the CLK input by two to get an internal clock, it turns itself off is composed of two non-overlapping phases PHI1 and PHI2. The central unit10th directs PHI1 to the BUSCLK output signal. TheFig. 7 shows the relationship between the CLK input and BUSCLK output signals. Like in theFig. 8, defines each rising edge the BUSCLK output a transition in the timeout status ("T- Status ") of the central unit10th. Bus cycles occur during a T Status sequence T1, T2 and T2B in the associated Timing diagram on. Between the bus cycles it can be too Idle states (Ti) come. The relationship of the phases BUSCLK- Output to CLK input can be built up when resetting. The basic bus cycles by the central unit10th to read from and save to external storage and the Peripherals are performed occur during two bus Clock cycles, T1 and T2. The basic bus cycles can be off two reasons can be extended beyond the two clock cycles. First, additional T2 cycles can be added to slow down Maintain memory and peripherals. Second, you can Multiple cycles "T2B" when reading from external memory Transfer of multiple double words from consecutive places to be used. The timing of the simple read and write bus cycles without "Wait" state is in each of theFig. 8 and 9 respectively. in the The central unit controls the read and write cycle10th the Address strobe during the first half of T1, and thus signals the start of the bus cycle. From the beginning of the T1 cycle The central unit controls until the bus cycle ends10th the Address bus and the control signals for the signals for status (ST0-ST4), byte enable (BE0-BE3), data direction ON (), Cache inhibition (CI0), I / O inhibition () and cache area (CASEC). If the bus cycle is not cleared (i.e. if T2 follows the next Clock follows), the central unit confirms10th during T1 den Beginning of the saving process and "confirmation of the bus cycle" from the middle of T1 until the bus cycle is completed, where is negated. Termination of T2 probes the central unit10th whether RDY is active, indicating that the bus cycle has ended; d. H. that no further T2 states should be added. On T2 follow either T1 for the next bus cycle or Ti if the Central unit10th does not have to perform a bus cycle. Like in theFig. 10, can already described simple read and write bus cycles for Support for longer access times can be expanded. How described, the central unit10th RDY at the end of each T2 Condition. If RDY is not active, the bus cycle is activated Repetition of T2 extended for another cycle. The T1 following additional T2 states become "wait" states called. TheFig. 10 shows the expansion of a read bus cycle by adding two waiting states. Like in theFig. 11, the simple ones Read cycles to support multiple data transfers from up to four double words from consecutive memory locations be expanded. During a multicast read cycle the first double word, like a simple read cycle, transmitted during a sequence of T1 and T2 states. The following Double words become during the states labeled "T2B" transfer. Multiple data transfer cycles are for read only used from 32-bit memories. The number of transfers in a multiple transfer Read cycle is by acknowledgment between the output signal Multiple data transfer request and the input signal Multiple data transfer confirmation during a T2 or T2B state controlled to indicate that after a running Transfer another is requested. The memory controls to indicate that there is another transmission can support. TheFig. 11 shows a multiple transmission Read cycle with three transfers in which the central processing unit10th the sequence by negating after the second transmission completed. TheFig. 12 shows a multiple transmission cycle with two transfers that are ended by the system when was inactive during the second transmission. For each transfer that is the first one Multiple data transmission follows, the central unit increases the Address bits 2 and 3 to drive the next double word. How in theFig. 12 shown for the second transmission, the key Central unit10th RDY off at the end of each T2B state and extends the access time for multiple data transmission when RDY is inactive. The central unit10th involves a number of techniques for Maintaining data coherence between the two integrated cache memory and external memory. These techniques are summarized in Table 5. Table 5 The use of caches can be done through the CI bit in inhibited the level 2 page board entries for individual pages will. The coherence between the two integrated circuits Central unit cache10th and external storage can be achieved by using an external "bus monitoring"26 make sure that in theFig. 1 is shown. This circuit 26 forms the interface to the following buses: 1. Central unit address bus and CASEC edition for maintenance of information through which the internal cache Input (identifiers) to be changed and creation updated copies of the internal cache identifiers of Central unit10th; 2. System bus to perceive which internal Memory addresses have been changed; and 3. Central unit cache invalidation bus10th, the is composed of -, -, - and CIA0-CIA6- Signals. The bus monitoring26 receives identification copies of the command Cache14 and data cache16 Inputs. If the address is one Memory write cycle on the system bus to one of the identifiers the bus monitoring26 fits, gives the bus monitoring26 the Command to the central processing unit via the cache invalidation bus10th, the relevant entry in the corresponding internal cache memory to invalidate. The invalidation of the internal cache memory Entry by the central unit10th only takes one clock cycle Claim and does not interfere with the ongoing CPU bus cycle a. The data cache16 32 bytes are invalidated at the same time, during the instruction cache14 16 bytes invalidated at the same time will. These techniques to maintain coherence between the two integrated cache memories of the central unit10th and the external storage will be more detailed in the same time pending and filed US Patent Application No. 006,015 "Method of maintaining coherency between an instruction cache and an external memory of a microprocessor "from Shacham et al. treated and referred to here. The central unit fetches a command10th first the command ahead, its address in the command counter is contained and then performs the operations for the concerned Command by. After executing the command, the Command count in one of two ways updated to the address of the next command to be executed record: either the current command explicitly loads the Command counter (like JUMP) or the command counter jumps around the Length of the current command. The command sequence executed by the microprocessor becomes fast using the following four rules:

• 1. If the microprocessor encounters an exception, control is transferred to the first command from the appropriate utility for that type of exception. Depending on the definition of the operation of the microprocessor, the address and memory of the exception utility are either fixed or are found in a table with the addresses of such utilities;
• 2. If the microprocessor executes a recorded jump command, control is transferred to the command, the address of which is calculated in the memory by adding the offset value in the jump command and the address of the jump command;
• 3. If the microprocessor executes a branch instruction that has been recorded, control is transferred to the instruction whose address in the memory is generally calculated in accordance with the definition of this individual instruction, and
• 4. If the microprocessor executes a command and none of the rules described above apply, control is transferred to the command whose address in memory immediately follows that of the command being executed.

The central unit10th has five operating states Execution of commands and processing of exceptions: Resetting, executing the command, processing exceptions, Waiting for a break and stopping. During the execution of a command, the Central unit, if it detects an exception, the content of the appropriate register, then begins executing a Exception utility. Exceptions are conditions, events and errors that change a sequence of command executions to lead. The central unit10th recognizes four exception types: reset, Bus errors, interruptions and traps. A reset exception occurs when the signal is activated; is becoming Initialization of the central unit10th used. A bus Error exception occurs when the BER signal reacts a command fetch or data transmission is activated, the from the central unit10th requested to execute a command has been. An interrupt occurs in response to a activation of the NMI or INT signal reported event; Interruptions are usually caused by peripheral devices requested the polling of the central unit10th request. A Trap occurs when certain conditions, such as a divisor of 0, from the central unit10th while executing a command being found. As soon as the signal is activated, the central unit goes 10th in the reset status where it remains until inactive is done, after which it is in the state of command execution transforms. While the central processing unit10th in the reset state the contents of certain own registers initialized. As long as the central unit10th in the state of Command execution, it continues with the execution of Commands continue until an exception is detected or a "wait" command is performed. If an exception, but not a reset, the central unit goes10th in the state of Processing an exception over. After executing the "wait" - Command goes the central unit10th waiting for one Break over. As long as the central unit10th in processing condition an exception, it saves the content of the corresponding register and reads the command counter and the Module connection values to help with the execution of the Exception utility to begin. To process a The CPU reads the interruption10th additionally one or two Vector values from the ICU24th. After all successfully completed Data references requested to process an exception the central unit goes10th in the state of Command execution via. However, if a bus error or a Abort while the central unit10th an exception processed, it changes to the hold state. While waiting for an interruption, there is the Central unit10th at rest. A status of its own State identified is on the system interface shown. If an interruption or a Error correction status is perceived, the changes Central unit10th in the state of exception processing. The central unit changes to the hold state10th then, when a bus failure or abort is perceived while it is processes an exception and thereby prevents the transition of Control to a corresponding exception utility. A separate status to identify this status is displayed on the system interface. The central unit10th performs the following operations Execution of a command from: Getting the command;
Reading the source operands, if available;
Computing the results;
Writing the result operands, if available;
Change of error markings if necessary; and
Command counter update. In most cases, the central unit runs10th Commands by processing the operations listed above in one strict follow first for an order, only then with the next command to begin. As described above, however Exceptions are the sequence of operations to execute a command or to change from one command to the next. Likewise, with an expanded performance, the overlaps Central unit10th the operations to execute some commands in parallel processing. The following explanations explain the effects of Exceptions in the pipeline12 on the command execution. in the the following are read addresses from the memory Calculation of the effective addresses for memory-related and external addressing types are regarded as source operands, even if the effective address for an operand with writable access (with access class of write) is calculated. The central unit10th checks at various points during command execution on exceptions. Will be an exception perceived, then the command being executed ends in one of four possible ways: it is completed, stopped, ended or partially ended. Each of the four Exception types lead to their own termination. If an exception occurs after a Perceived command, the central unit10th all operations for this command and for all others after the appearance of the commands executed last exception. Result operands were written, error marks were made changed and the one saved on the interrupt stack Command counter value contains the address of the next to be executed Command. The exception utility may complete upon completion execute an appropriate return command, whereupon the Central unit10th with the execution of the completed Command following command begins. A command is paused if, while the Command one of the different trap states or a restartable bus error is perceived. A suspended command was not completed, however all were others executed after the last exception occurred Commands completed. The result operands and by the instruction Markings to be performed may have been changed, however only such changes can occur that the rerun and enable the completion of the command. With certain exceptions (e.g. bus errors and aborts, undefined command and illegal operation markings) the central unit lifts10th the corresponding tax mark in the program status register, before ensuring the copy that is on the Interrupt stack is pushed. The one on the Interrupt Stack Ensured Command Counter Value contains the Address of the suspended command. For example, a RESTORE command takes up to eight general ones Register from the stack. Will be on one of the covers on the stack invalid page table entry is detected, the command exposed. The general register by the command may have been changed, but the Stack pointer still shows the value it had than this Command began. At the end of a suspended command that works Exception utility after one of two possible operations in front:

• 1. The utility can simulate the execution of the suspended commands. After the computation and writing of the command results, the marks stored on the interrupt stack in the copy of the program status register are changed and the instruction counter value stored on the interrupt stack is updated to point to the next command to be executed. The utility then executes an appropriate return command and the CPU 10 begins executing the command following the command that was suspended. This process takes place when the floating point commands are simulated by the software of systems that do not have a hardware floating point unit.
• 2. A suspended command can be rerun after the utility clears the trap that caused the command to be suspended. The utility executes a return command upon termination. After this, the central unit 10 starts again to execute the suspended command.

Although the central unit10th a new execution and If a command that has been suspended can be ended, it can Source operands or the instruction from a memory-allocated Have read the peripheral channel before noticing the exception has been. In such a case, the characteristic curve of the Peripheral correctly executing the command again prevent. A command in progress is finished when it reset or if a non-restartable bus Error occurs. All to be executed by the command Result operands and markings are undefined like the content the command counter. The result operands of others since the last Commands running in series operation may not be in the memory has been written. A completed command cannot be completed. If a restartable bus error, an interruption, an abort or a test state while executing a Perceived chain command, the command should be partial be completed. A partially completed command was made not completed, however all others have been since the last Exception commands executed completed. By the command Result operands and markings to be executed can be changed have been, but that in the stream pointers and others during general registers used for command execution Value enables the execution and completion of the Command. The command counter value stored in the interrupt stack contains the address of the partially completed command. In the The exception utility may terminate the appropriate Simply execute the reset command and the central unit10th puts continue executing the partially completed command. As already described, the central unit overlaps10th the Operations to execute multiple commands simultaneously in the 4-stage pipeline12. The general structure of the pipeline12 is in theFig. 13 shown. While the execution unit32 the The address unit can calculate results for a command30th calculate the effective addresses and the source operands for the read the following command while the program loader28 one decrypt third command and a fourth into its 8-byte Can catch up with snake. In certain cases, the Effects of overlapped command execution from those of Execute a command in strictly sequential order. More specifically, that of the central unit10th executed Order of memory references can seem to differ. The central processing unit can execute a command 10th read some of the source operands from memory before the Command is fully retrieved. The central unit10th closes however, getting an instruction and reading the source operands always before their results are written. Must be more than a source operand from memory to execute an instruction then these operands can be read in any Order can be read. Operands can also be used in any Order can be written if more than one result operand to be read into memory to execute a command. The central unit10th starts getting a command only after all previous commands are fully retrieved were. The central unit10th can, however, get one Command begin before all source operands are read and the Results have been written for previous commands. The central unit10th starts reading the Source operands for an instruction only after all previous ones Commands have been retrieved and their source operands have been read. The source operand for an instruction can be read before all Results of the previous command were written to be because that the value of the source operands does not yet differ from that written result is dependent. The central unit10th compares the physical address according to the length of the Source operands with those of the results not yet written and delays reading the source operand until all results, on which the source operand depends. The central unit also identifies10th Source operands that are allocated in memory Peripheral channels are located and delays the reading of these Operands up to all previous results for the memory-assigned peripheral channels have been written. Own Work programs ensure that the read and write references to memory-assigned I / O channels always in the Program in the specified order. These processes are brought in and pending at the same time US Patent Application No. 006.012 "Methods of Perception and Processing memory-allocated I / O through a pipeline Microprocessor "by Levy et al. And referred to herein becomes. The central unit10th begins writing the Result operands for a command only after all results of the previous commands were written. Because of the overlap of operations for some commands can the central unit10th get a command and its Read source operands even though the instruction is not executed (e.g. if the previous command caused a trap). Still, if the central unit10th a source operand for one Perceives command in a memory-allocated peripheral channel, it only reads the source operand when the instruction is executed. It should be noted that the central unit10th not on Dependencies between getting a command and the Writing previous command results checks. Therefore a Self-renewal code specially treated for the planned execution will. After executing certain commands or after the The central unit handles an exception10th the Execution of commands in a serial form. The serialization the execution of instructions means that the central processing unit10th writing all the results of previous commands in the Memory completes, then with the retrieval and execution of the next command begins. So if a new value in that Program status register is loaded, determines the new value of the Program status register the privilege status that is available for polling and Executing the next command is used. According to the present invention, the Central unit10th a 2-step program for monitoring the Sequence of commands executed. The first stage is a additional interface signal that indicates whether a command, whose execution begins, is sequential or non-sequential. Second, there is an additional one on the interface signals Information supplied that is used for external memory references becomes. The interface signal becomes "Internal Sequential Fetch" (ISF) (internal sequential polling). The central unit 10th activates the ISF signal together with a Program execution status signal as soon as a recorded jump or Branch instruction is executed. In the context of this present invention only needs the central processing unit10th the ISF Activate signal for recorded jump commands. It is therefore possible to monitor the control flow when a jump command is performed. If the jump instruction is taken, what by Activation of the ISF signal is displayed, the controller transferred to a target command whose address is calculated can, since the coding and address of the jump instruction are known. If the jump is not recorded, this is due to inactivation of the ISF signal is displayed, the control is based on the im Transfer the following command to the memory jump command. More information on monitoring tax flow will be provided only displayed in the interface of the external memory, when a recorded branch instruction is executed or an exception occurs. If an exception occurs, the shows Central unit10th both a code that indicates the type of execution names, and the virtual address of the exception utility. When a recorded branch instruction is executed, shows the central unit10th the virtual address of the jump destination. The destination address is displayed after the central unit10th With started getting the command at the jump destination. The At this point, the memory interface is in the Usually at rest while the central processing unit10th decoded and prepared to execute an instruction at the branch destination. The central unit reports on the status information10th at if either the code for an exception or the destination address for indicates a taken branch instruction rather than that a Relation to the memory is established. The address unit30th and the execution unit32 can Commands with a maximum frequency of two cycles per command to process. The program loader28 processes commands with a Maximum frequency of one cycle per command, so that it the Address unit30th and to the execution unit32 constantly with Orders supplied. The program loader28 interrupts throughput the pipeline12 only if the command stream through one Jump instruction or missed instruction cache interrupted becomes. TheFig. 14 shows the execution of two memory displays. Command commands by the address unit30th and the Execution unit32. The central unit10th can with most usual instructions have an execution rate of two cycles maintains and shows delays only in the following cases:

• 1. Memory delays due to cache and transfer buffer misses and misaligned references.
• 2. Resource competition between states of the instruction pipeline 12 .
• 3. Jumps or other non-sequential instruction fetches.
• 4. Complex addressing modes like scaled index and complex operations like division.

TheFig. 15 shows the effect of missing the data Cache16 on the timing of the pipeline12. The Execution unit32 is delayed by two cycles until the BIU20th has completed the bus cycle for reading the data. Fig. 16 shows the effect of an address Register locking on the timing of the pipeline12: a Command changes a register while the next command changes it Register used to calculate an address. The address unit 30th is delayed by three cycles until the execution unit32 completes the update of the register. It should be noted here that if the second command fails to register Address calculation (e.g. ADDD R0, R1), but for a data value would use the bypass circuit in the Execution unit32 to prevent a delay pipeline12 used. The program loader28 includes special circuits for Handling jump commands. If a branch instruction is decoded, the program loader calculates28 the destination address and choose between sequential and non-sequential instruction streams. The Selection is based on the jump condition and direction. If the Program loader28 predicts that a jump will be recorded the destination address on the JBUS to the instruction cache14 transfer. Whether a jump is predicted or not, the Program loader28 stores the address of the changing Command stream. Then the jump command reaches the Execution unit32in which the condition is resolved. The Execution unit32 reports to the program loader28, if one Branch was added or not. If the branch The pipeline is incorrectly predicted12 deleted, and the Instruction cache14 begins by prefetching commands from the right current. TheFig. 17 shows the effect of correct prediction a jump instruction to be recorded. A gap of two cycles occurs when the program loader decodes commands28 on. This gap at the top of the pipeline12 can be closed frequently as a fully decoded instruction between Program loader28 and address unit30th is buffered and because other delays simultaneously in later stages in the pipeline12 may occur. TheFig. 18 shows the effect of incorrect prediction a resolution of a jump instruction. A gap of four cycles occurs in the execution unit32 on. Further information on the workflow of the central unit10th see the pending and common at the same time filed US Patent Application No. 006.016 "high performance Microprocessor ", filed simultaneously by Alpert et al and is referred to here. It should be noted that alternative forms to the form shown here for carrying out the present here Invention are applicable. The general idea behind the process is Monitoring the commands executed by a central unit: When a branch instruction is executed, the CPU generates a distinctive interface signal and if a Branch instruction is executed, the CPU shows one characteristic information on the external memory interface.

Claims (16)

1. Data processing system with an external interface characterized by a device for monitoring the sequence of commands executed by the data processing system, by which an interface signal is triggered, which indicates whether a command, the execution of which is sequential or non-sequential, and by the Information is displayed on the interface that indicates when a recorded jump or branch instruction is executed or an exception occurs. 2. Monitoring device according to claim 1, characterized characterized in that the interface signal is activated, when a recorded jump instruction is executed. 3. Monitoring device according to claim 2, characterized characterized in that the controller is on a target command is transmitted, whose address by the coding and the The address of the recorded jump instruction is calculated. 4. Monitoring device according to claim 1, characterized characterized in that the interface signal is inactive if a jump instruction is not accepted. 5. Monitoring device according to claim 4, characterized characterized in that the control on the jump instruction in Memory sequentially following command is transferred. 6. Monitoring device according to claim 1, characterized characterized in that when an exception occurs, a Encoding is displayed, which indicates the type of exception. 7. Monitoring device according to claim 6, characterized characterized in that the virtual address of a Exception Utility is displayed. 8. Monitoring device according to claim 1, characterized characterized that the virtual address of a jump destination is displayed when a recorded jump instruction is executed becomes. 9. Monitoring device according to claim 8, characterized marked that the destination address is displayed after the System started getting the command at the destination address Has. 10. A method for monitoring the sequence of commands executed by the central processing unit with an external interface, comprising the following functions: generating an interface signal which indicates whether a command whose execution is starting is sequential or non-sequential; and
Displays the information on the interface that indicates when a recorded branch instruction is being executed or when an exception occurs. 11. The method according to claim 10, characterized in that the Interface signal is activated when a recorded Jump instruction is executed. 12. The method according to claim 10, characterized in that the If an exception occurs, a coding is displayed that matches the Specifies the type of exception. 13. The method according to claim 12, characterized in that the virtual address of a corresponding exception utility is shown. 14. The method according to claim 10, characterized in that the virtual address of a jump destination when executing a recorded branch instruction is displayed. 15. The method according to claim 14, characterized in that the Destination address is displayed after the central unit with the The instruction at the branch destination started. 16. A method for monitoring the commands executed by the central unit equipped with an external interface, comprising the following functions:

• (a) generation of an interface signal for the execution of a jump instruction, the interface signal having a first status when a jump is recorded and a second status when a jump is not recorded, and,
  • (i) in the first status, the control of the central unit is transferred to a target command with an address calculated by decoding and the address information of the jump command and
  • (ii) in the second status, the control of the central unit is transferred to the next sequential command following a jump command and
• (b) Displaying the message in the interface for the execution of a branch instruction received or for the occurrence of an exception such that
  • (i) when an exception occurs, a code identifies the type of exception and the location of a corresponding exception utility; and
  • (ii) when executing a picked branch instruction, the location of the branch instruction is displayed.