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DE3737015C1 - Method and circuit arrangement for extracting a clock signal for a CMI signal - Google Patents

Method and circuit arrangement for extracting a clock signal for a CMI signal

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Publication number
DE3737015C1
DE3737015C1 DE19873737015 DE3737015A DE3737015C1 DE 3737015 C1 DE3737015 C1 DE 3737015C1 DE 19873737015 DE19873737015 DE 19873737015 DE 3737015 A DE3737015 A DE 3737015A DE 3737015 C1 DE3737015 C1 DE 3737015C1
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DE
Germany
Prior art keywords
signal
cmi
clock
flip
pulse
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Expired
Application number
DE19873737015
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German (de)
Inventor
Klaus Dipl-Ing Litkiewicz
Josef Ing Dichtl
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Robert Bosch GmbH
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ANT Nachrichtentechnik GmbH
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Priority to DE19873737015 priority Critical patent/DE3737015C1/en
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Publication of DE3737015C1 publication Critical patent/DE3737015C1/en
Expired legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0066—Detection of the synchronisation error by features other than the received signal transition detection of error based on transmission code rule
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M5/00—Conversion of the form of the representation of individual digits
    • H03M5/02—Conversion to or from representation by pulses
    • H03M5/04—Conversion to or from representation by pulses the pulses having two levels
    • H03M5/06—Code representation, e.g. transition, for a given bit cell depending only on the information in that bit cell
    • H03M5/12—Biphase level code, e.g. split phase code, Manchester code; Biphase space or mark code, e.g. double frequency code
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
    • H04L25/4908—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes
    • H04L25/491—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes using 1B2B codes
    • H04L25/4912—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes using 1B2B codes using CMI or 2-HDB-3 code
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

A method for extracting a clock signal, the clock period of which corresponds to the period of one bit interval (BI) of a CMI signal and which is phase-synchronous with the CMI signal, from another predetermined clock signal, the clock period of which corresponds to half the period of one bit interval (BI) of the CMI signal (CS), consists in that after each negative pulse edge of the CMI signal (CS, F1), a pulse with the period of half the bit interval (BI) of the CMI signal is generated, that from the pulses produced during this process, a periodic pulse sequence (F4), half the period of which corresponds to the pulse period of the previously generated pulses (IS), is extracted with the aid of the predetermined clock signal (T2) from the pulses produced during the former generating process, and that the pulse sequence (F4) which represents the desired clock signal, and the CMI signal (F3), are placed into such a phase relation with respect to one another that the pulse edges of the extracted clock signal (F4) are offset with respect to the pulse edges of the CMI signal (F3) (Fig.2). <IMAGE>

Description

Die vorliegende Erfindung betrifft ein Verfahren zum Ableiten eines Taktsignals, dessen Taktperiode der der Dauer eines Bitintervalls eines CMI-Signals entspricht und das phasensynchron mit dem CMI-Signal ist, aus einem anderen vorgegebenen Taktsignal, dessen Taktperiode der halben Dauer eines Bitintervalls des CMI-Signals entspricht.The present invention relates to a method for Deriving a clock signal whose clock period is that of the duration corresponds to a bit interval of a CMI signal and that is in phase with the CMI signal from another predetermined clock signal, the clock period of half the duration corresponds to a bit interval of the CMI signal.

Aus der DE 33 02 761 A1 ist ein CMI-Decoder bekannt, dem einerseits ein CMI-codiertes Signal und andererseits ein Taktsignal zugeführt wird, dessen Taktperiode der halben Dauer eines Bitintervalls des CMI-codierten Signals entspricht. In der DE 32 48 624 A1 ist eine Schaltungsanordnung beschrieben, die aus einem CMI-codierten Signal ein binäres Digitalsignal und ein zugehöriges Taktsignal ableitet.A CMI decoder is known from DE 33 02 761 A1 on the one hand a CMI-coded signal and on the other hand a Clock signal is supplied, the clock period of half Duration of a bit interval of the CMI-coded signal corresponds. DE 32 48 624 A1 is a Circuitry described that encoded from a CMI Signal a binary digital signal and an associated one Derives clock signal.

Ein Verfahren anzugeben, mit dem aus einem solchen eingangs erwähnten Taktsignal ein anderes Taktsignal abgeleitet werden kann, welches z. B. für die Dekodierung eines empfangenen CMI-Signals eine geeignete Taktperiode und Phasenlage hat, ist Aufgabe der hier zugrundeliegenden Erfindung.To specify a procedure from which such an input clock signal mentioned derived another clock signal can be, which z. B. for decoding a received CMI signal a suitable clock period and Phase is the task of the one here Invention.

Gelöst wird diese Aufgabe durch die Merkmale des Anspruchs 1. Eine zweckmäßige Ausführung des erfindungsgemäßen Verfahrens nach Anspruch 1 geht aus dem Anspruch 2 hervor, und eine vorteilhafte Schaltungsanordnung zum Durchführen des Verfahrens ist dem Anspruch 3 zu entnehmen.This problem is solved by the features of the claim 1. An expedient implementation of the invention Method according to claim 1 follows from claim 2, and an advantageous circuit arrangement for performing the method can be found in claim 3.

Anhand eines in der Zeichnung dargestellten Ausführungsbeispiels wird nun die Erfindung näher erläutert. Dabei zeigtUsing one shown in the drawing The invention will now be explained in more detail by way of example. It shows

Fig. 1 ein Blockschaltbild einer nach dem Verfahren der Erfindung arbeitenden Schaltung, und Fig. 1 is a block diagram of a circuit operating according to the method of the invention, and

Fig. 2 zeigt ein Impulsdiagramm der in der Schaltung auftretenden Signale. Fig. 2 shows a timing diagram of the signals appearing in the circuit.

An den Eingängen der in der Fig. 1 dargestellten Schaltungsanordnung liegen ein CMI(coded mark inversion)-Signal CS, dessen Struktur das Impulsdiagramm in Fig. 2 verdeutlicht, und ein Taktsignal T 2 an, dessen Taktperiode, wie der Fig. 2 zu entnehmen ist, der halben Dauer eines Bitintervalls BI des CMI-Signals CS entspricht. Ein derartiges Taktsignal T 2 ist zuvor aus dem empfangenen CMI-Signal CS abgeleitet worden, weil es für gewisse hier nicht erörterte Zwecke in der Empfängerschaltung benötigt wird. Dieses Taktsignal T 2 ist aber nicht geeignet, um in einem CMI-Decoder DC aus dem CMI-Signal die ursprüngliche binäre Information zurückzugewinnen. Nachfolgend wird beschrieben, nach welchem Verfahren aus dem vorgegebenen Taktsignal T 2 ein für die Decodierung geeigneter Takt abgeleitet werden kann.At the inputs of the circuit arrangement shown in FIG. 1, there is a CMI (coded mark inversion) signal CS , the structure of which illustrates the pulse diagram in FIG. 2, and a clock signal T 2 , whose clock period, as can be seen in FIG. 2 is half the duration of a bit interval BI of the CMI signal CS . Such a clock signal T 2 has previously been derived from the received CMI signal CS because it is required in the receiver circuit for certain purposes not discussed here. However, this clock signal T 2 is not suitable for recovering the original binary information from the CMI signal in a CMI decoder DC . The following describes the method by which a clock suitable for decoding can be derived from the predetermined clock signal T 2 .

Das empfangene CMI-Signal CS wird dem Signaleingang eines ersten D-Flip-Flop FF 1 und das gegebene Taktsignal T 2 dem Takteingang dieses ersten D-Flip-Flop FF 1 zugeführt. Am Ausgang des D-Flip-Flop FF 1 erschein das um eine halbe Taktperiode des Taktsignals T 2 verzögerte CMI-Signal F 1. Dieses verzögerte CMI-Signal F 1 wird zusammen mit dem Taktsignal T 2 auf ein zweites D-Flip-Flop FF 2 gegeben, wodurch das CMI-Signal nochmals eine Verzögerung um eine ganze Taktperiode des Taktsignals T 2 erfährt, so daß schließlich am Ausgang des zweiten D-Flip-Flop FF 2 ein gegenüber dem ursprünglichen CMI-Signal CS um eineinhalb Taktperioden verzögertes CMI-Signal F 2 zur Verfügung steht (vgl. Fig. 2). The received CMI signal CS is fed to the signal input of a first D- flip-flop FF 1 and the given clock signal T 2 to the clock input of this first D- flip-flop FF 1 . At the output of the D flip-flop FF 1 delayed by half a clock period of the clock signal T 2 CMI signal F 1 pops up. This delayed CMI signal F 1 is given together with the clock signal T 2 to a second D flip-flop FF 2 , whereby the CMI signal is again delayed by an entire clock period of the clock signal T 2 , so that finally at the output of the second D flip-flop FF 2, a CMI signal F 2 delayed by one and a half clock periods compared to the original CMI signal CS is available (cf. FIG. 2).

Einem dritten D-Flip-Flop FF 3 werden das um eineinhalb Taktperioden verzögerte CMI-Signal F 2 und das einen Inverter IV durchlaufene Taktsignal zugeführt. Schließlich gelangt das daraus hervorgehende um zwei ganze Taktperioden verzögerte CMI-Signal F 3 zum CMI-Decoder DC.A third D- flip-flop FF 3 is supplied with the CMI signal F 2 , which is delayed by one and a half clock periods, and the clock signal passed through an inverter IV. Finally, the resulting CMI signal F 3 , which is delayed by two complete clock periods, reaches the CMI decoder DC .

Das um eine halbe Taktperiode verzögerte CMI-Signal F 1 und das um eineinhalb Taktperioden verzögerte invertierte CMI-Signal werden in einem NOR-Gatter NOG miteinander verknüpft, woraus ein Signal IS resultiert, das immer dann einen Impuls hat, wenn gleichzeitig das CMI-Signal F 1 seine niedrigste Amplitudenstufe und das CMI-Signal F 2 seine höchste Amplitudenstufe aufweist. Es entsteht dabei also ein Signal IS, das nach jeder negativen Impulsflanke des CMI-Signals CS bzw. F 1 einen Impuls mit der Dauer des halben Bitintervalls BI des CMI-Signals hat.The CMI signal F 1 delayed by half a clock period and the inverted CMI signal delayed by one and a half clock periods are combined in a NOR gate NOG , resulting in a signal IS which always has a pulse when the CMI signal is present at the same time F 1 has its lowest amplitude level and the CMI signal F 2 has its highest amplitude level. This results in a signal IS that has a pulse with the duration of half the bit interval BI of the CMI signal after each negative pulse edge of the CMI signal CS or F 1 .

Dieses Ausgangssignal IS des NOR-Gatters NOG wird an einen Eingang eines OR-Gatters OG angelegt, und ein zweiter Eingang des OR-Gatters OG erhält das invertierte Ausgangssignal eines vierten D-Flip-Flop FF 4, dessen Signaleingang mit dem Ausgang des OR-Gatters OG verbunden ist und dessen Takteingang mit dem Taktsignal T 2 gespeist wird. Das nichtinvertierte in Fig. 2 dargestellte Ausgangssignal F 4 des vierten D-Flip-Flop FF 4 ist das für die Decodierung des CMI-Signals F 3 geeignete Taktsignal. Es stellt eine periodische Impulsfolge dar, deren halbe Periodendauer der Impulsdauer der im zuvor abgeleiteten Signal IS auftretenden Impulse entspricht.This output signal IS of the NOR gate NOG is applied to an input of an OR gate OG , and a second input of the OR gate OG receives the inverted output signal of a fourth D flip-flop FF 4 , the signal input of which is connected to the output of the OR Gate OG is connected and the clock input is fed with the clock signal T 2 . The non-inverted output signal F 4 of the fourth D- flip-flop FF 4 shown in FIG. 2 is the clock signal suitable for decoding the CMI signal F 3 . It represents a periodic pulse train whose half period corresponds to the pulse duration of the pulses occurring in the previously derived signal IS .

Das ermittelte Taktsignal F 4 und das am Ausgang des dritten D-Flip-Flop FF 3 zur Verfügung stehende CMI-Signal F 3 haben auch die für den CMI-Decoder DC erforderliche Phasenbeziehung; d. h. das Taktsignal F 4 ist mit seinen positiven Impulsflanken gegenüber den Bitintervall-Anfängen des CMI-Signals F 3 um etwa ein Viertel der Bitintervalldauer BI zeitlich versetzt.The clock signal F 4 determined and the CMI signal F 3 available at the output of the third D- flip-flop FF 3 also have the phase relationship required for the CMI decoder DC ; ie the clock signal F 4 is offset in time by approximately a quarter of the bit interval duration BI with its positive pulse edges compared to the beginning of the bit interval of the CMI signal F 3 .

Claims (3)

1. Verfahren zum Ableiten eines Taktsignals, dessen Taktperiode der Dauer eines Bitintervalls eines CMI-Signals entspricht und das phasensynchron mit dem CMI-Signal ist, aus einem anderen vorgegebenen Taktsignal, dessen Taktperiode der halben Dauer eines Bitintervalls der CMI-Signals entspricht, dadurch gekennzeichnet, daß nach jeder negativen Impulsflanke des CMI-Signals (CS, F 1) ein Impuls (IS) der Dauer des halben Bitintervalls (BI) des CMI-Signals erzeugt wird, daß aus den dabei entstehenden Impulsen mit Hilfe des vorgegebenen Taktsignals (T 2) eine periodische Impulsfolge (F 4) abgeleitet wird, deren halbe Periodendauer der Impulsdauer der zuvor erzeugten Impulse (IS) entspricht, und daß die Impulsfolge (F 4), die das gewünschte Taktsignal darstellt, und das CMI-Signal (F 3) in eine solche Phasenbeziehung zueinander gebracht werden, daß die Impulsflanken des abgeleiteten Taktsignals (F 4) gegenüber den Impulsflanken des CMI-Signals (F 3) versetzt sind. 1. A method for deriving a clock signal, the clock period of which corresponds to the duration of a bit interval of a CMI signal and which is in phase synchronization with the CMI signal, from another predetermined clock signal, the clock period of which corresponds to half the duration of a bit interval of the CMI signal, characterized in that that (1 CS, F) a pulse (iS) of the duration of half a bit interval (BI) of the CMI-signal is generated after each negative pulse edge of the CMI signal that from the resulting pulses by means of the predetermined clock signal (T 2 ) a periodic pulse train (F 4 ) is derived, the half period of which corresponds to the pulse duration of the previously generated pulses (IS) , and that the pulse train (F 4 ), which represents the desired clock signal, and the CMI signal (F 3 ) in such a phase relationship are brought together that the pulse edges of the derived clock signal (F 4 ) are offset from the pulse edges of the CMI signal (F 3 ). 2. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß aus dem um eine halbe Taktperiode verzögerten CMI-Signal (F 1) und dem um eineinhalb Taktperioden verzögerten CMI-Signal (F 2) ein Signal (IS) abgeleitet wird, das immer dann einen Impuls hat, wenn gleichzeitig das um eine halbe Taktperiode verzögerte CMI-Signal (F 1) seine niedrigste Amplitudenstufe und das um eineinhalb Taktperioden verzögerte CMI-Signal (F 2) seine höchste Amplitudenstufe aufweist, daß dieses Signal (IS), das aus nicht periodisch auftretenden Impulsen mit der Dauer des halben Bitintervalls (BI) des CMI-Signals besteht, in eine periodische Impulsfolge (F 4) umgeformt wird, deren halbe Periodendauer der Impulsdauer der Impulse des zuvor abgeleiteten Signals (IS) entspricht, und daß das um eineinhalb Taktperioden verzögerte CMI-Signal (F 2) nochmals um eine weitere halbe Taktperiode verzögert wird, so daß das schließlich um zwei ganze Taktperioden verzögerte CMI-Signal (F 3) und die periodische Impulsfolge (F 3), welche das gewünschte Taktsignal darstellt, in einer solchen Phasenbeziehung zueinander stehen, daß die positiven Impulsflanken der Impulsfolge (F 4) gegenüber den Bitintervall-Anfängern des CMI-Signals (F 3) um etwa ein Vierteil der Bitintervalldauer (BI) zeitlich versetzt sind.2. The method according to claim 1, characterized in that a signal (IS) is derived from the CMI signal (F 1 ) delayed by half a clock period and the CMI signal (F 2 ) delayed by one and a half clock periods, which is then always a Pulse has, if at the same time the CMI signal (F 1 ) delayed by half a clock period has its lowest amplitude level and the CMI signal (F 2 ) delayed by half a clock period has its highest amplitude level, that this signal (IS) , which is not periodic occurring pulses with the duration of half the bit interval (BI) of the CMI signal, is converted into a periodic pulse train (F 4 ), whose half period corresponds to the pulse duration of the pulses of the previously derived signal (IS) , and that by one and a half clock periods Delayed CMI signal (F 2 ) is delayed again by a further half clock period, so that the CMI signal (F 3 ) and the periodic impulse fol ge (F 3 ), which represents the desired clock signal, are in such a phase relationship that the positive pulse edges of the pulse train (F 4 ) compared to the bit interval beginners of the CMI signal (F 3 ) by about a fourth of the bit interval duration (BI ) are staggered in time. 3. Schaltungsanordnung zum Durchführen des Verfahrens nach Anspruch 1 oder 2, dadurch gekennzeichnet, daß ein erstes D-Flip-Flop (FF 1) vorhanden ist, dem das CMI-Signal (CS) zugeführt ist und an dessen Takteingang das vorgegebene Taktsignal (T 2), dessen Taktperiode der halben Dauer eines Bitintervalls (BI) des CMI-Signals (CS) entspricht, anliegt, daß ein zweites D-Flip-Flop (FF 2) vorhanden ist, dessen Signaleingang an den Signalausgang des ersten D-Flip-Flop (FF 1) angeschlossen ist und dessen Takteingang ebenfalls das vorgegebene Taktsignal erhält, daß ein drittes D-Flip-Flop (FF 3) vorhanden ist, dessen Signaleingang mit dem Signalausgang des zweiten D-Flip-Flop (FF 2) verbunden und dessen Takteingang das vorgegebenen Taktsignal (T 2) invertiert zugeführt ist, daß ein NOR-Gatter (NOG) das Ausgangssignal (F 1) des ersten D-Flip-Flop (FF 1) und das invertierte Ausgangssignal () des zweiten D-Flip-Flop (FF 2) miteinander verknüpft, und daß ein viertes D-Flip-Flop (FF 4) vorhanden ist, an dessen Takteingang das vorgegebene Taktsignal anliegt und dessen Signaleingang mit dem Ausgang eines OR-Gatters (OG) verbunden ist, dem sowohl das invertierte Ausgangssignal () des vierten D-Flip-Flop (FF 4) als auch das Ausgangssignal (IS) des NOR-Gatters (NOG) zugeführt ist, wobei das nichtinvertierte Ausgangssignal (F 4) des vierten D-Flip-Flips (FF 4) das gewünschte Taktsignal darstellt.3. Circuit arrangement for performing the method according to claim 1 or 2, characterized in that a first D- flip-flop (FF 1 ) is present, to which the CMI signal (CS) is supplied and at the clock input of the predetermined clock signal (T 2 ), whose clock period corresponds to half the duration of a bit interval (BI) of the CMI signal (CS) , there is a second D flip-flop (FF 2 ) whose signal input to the signal output of the first D flip-flop Flop (FF 1 ) is connected and its clock input also receives the predetermined clock signal that a third D flip flop (FF 3 ) is present, the signal input of which is connected to the signal output of the second D flip flop (FF 2 ) and the latter Clock input, the predetermined clock signal (T 2 ) is fed inverted, that a NOR gate (NOG), the output signal (F 1 ) of the first D flip-flop (FF 1 ) and the inverted output signal () of the second D flip-flop (FF 2 ) and that a fourth D flip flop ( FF 4 ) is present, at the clock input of which the predetermined clock signal is present and whose signal input is connected to the output of an OR gate (OG) , to which both the inverted output signal () of the fourth D flip-flop (FF 4 ) and that Output signal (IS) of the NOR gate (NOG) is supplied, wherein the non-inverted output signal (F 4 ) of the fourth D -flip-flip (FF 4 ) represents the desired clock signal.
DE19873737015 1987-10-31 1987-10-31 Method and circuit arrangement for extracting a clock signal for a CMI signal Expired DE3737015C1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0610798A1 (en) * 1993-02-08 1994-08-17 Siemens Aktiengesellschaft Self-aligning phase comparator for CMI coded signals

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3302761A1 (en) * 1983-01-27 1984-08-02 Siemens AG, 1000 Berlin und 8000 München CMI DECODER
DE3248624A1 (en) * 1982-12-30 1984-08-23 Hans Kolbe & Co, 3202 Bad Salzdetfurth Circuit arrangement for generating a digital binary data signal and an associated clock signal from a CMI-coded signal, the clock frequency of which is above 30 MHz

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3248624A1 (en) * 1982-12-30 1984-08-23 Hans Kolbe & Co, 3202 Bad Salzdetfurth Circuit arrangement for generating a digital binary data signal and an associated clock signal from a CMI-coded signal, the clock frequency of which is above 30 MHz
DE3302761A1 (en) * 1983-01-27 1984-08-02 Siemens AG, 1000 Berlin und 8000 München CMI DECODER

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0610798A1 (en) * 1993-02-08 1994-08-17 Siemens Aktiengesellschaft Self-aligning phase comparator for CMI coded signals

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