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DE3686709D1 - Gattermatrix. - Google Patents

Gattermatrix.

Info

Publication number
DE3686709D1
DE3686709D1 DE8686402558T DE3686709T DE3686709D1 DE 3686709 D1 DE3686709 D1 DE 3686709D1 DE 8686402558 T DE8686402558 T DE 8686402558T DE 3686709 T DE3686709 T DE 3686709T DE 3686709 D1 DE3686709 D1 DE 3686709D1
Authority
DE
Germany
Prior art keywords
gate matrix
matrix
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686402558T
Other languages
English (en)
Other versions
DE3686709T2 (de
Inventor
Tetsu Tanizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3686709D1 publication Critical patent/DE3686709D1/de
Publication of DE3686709T2 publication Critical patent/DE3686709T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90Masterslice integrated circuits
    • H10D84/903Masterslice integrated circuits comprising field effect technology
    • H10D84/907CMOS gate arrays
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/211Design considerations for internal polarisation
    • H10D89/311Design considerations for internal polarisation in bipolar devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
DE8686402558T 1985-11-19 1986-11-19 Gattermatrix. Expired - Fee Related DE3686709T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60259396A JPS62119936A (ja) 1985-11-19 1985-11-19 コンプリメンタリ−lsiチツプ

Publications (2)

Publication Number Publication Date
DE3686709D1 true DE3686709D1 (de) 1992-10-15
DE3686709T2 DE3686709T2 (de) 1993-01-14

Family

ID=17333549

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686402558T Expired - Fee Related DE3686709T2 (de) 1985-11-19 1986-11-19 Gattermatrix.

Country Status (5)

Country Link
US (1) US4928164A (de)
EP (1) EP0228320B1 (de)
JP (1) JPS62119936A (de)
KR (1) KR900003029B1 (de)
DE (1) DE3686709T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5047825A (en) * 1988-06-09 1991-09-10 Hitachi, Ltd. Semiconductor integrated circuit device having a decoder portion of complementary misfets employing multi-level conducting layer and a memory cell portion
US5247200A (en) * 1989-02-16 1993-09-21 Kabushiki Kaisha Toshiba MOSFET input type BiMOS IC device
USRE37424E1 (en) * 1989-06-14 2001-10-30 Stmicroelectronics S.R.L. Mixed technology integrated device comprising complementary LDMOS power transistors, CMOS and vertical PNP integrated structures having an enhanced ability to withstand a relatively high supply voltage
IT1235843B (it) * 1989-06-14 1992-11-03 Sgs Thomson Microelectronics Dispositivo integrato contenente strutture di potenza formate con transistori ldmos complementari, strutture cmos e pnp verticali con aumentata capacita' di supportare un'alta tensione di alimentazione.
US5057895A (en) * 1990-08-06 1991-10-15 Harris Corporation Trench conductor and crossunder architecture
US5196373A (en) * 1990-08-06 1993-03-23 Harris Corporation Method of making trench conductor and crossunder architecture
US5119160A (en) * 1990-11-19 1992-06-02 Hall John H Clocked CBICMOS integrated transistor structure
WO1995017007A1 (en) * 1993-12-14 1995-06-22 Oki America, Inc. Efficient routing method and resulting structure for integrated circuits
CN1186683C (zh) * 1999-09-08 2005-01-26 松下电器产业株式会社 显示装置及其制造方法
JP4497791B2 (ja) * 2002-05-09 2010-07-07 株式会社ルネサステクノロジ 半導体集積回路
US6983889B2 (en) * 2003-03-21 2006-01-10 Home Comfort Zones, Inc. Forced-air zone climate control system for existing residential houses
KR100532464B1 (ko) * 2003-08-28 2005-12-01 삼성전자주식회사 액티브를 이용한 반도체 셀의 전원선 레이아웃

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4471368A (en) * 1977-10-13 1984-09-11 Mohsen Amr M Dynamic RAM memory and vertical charge coupled dynamic storage cell therefor
US4353085A (en) * 1978-02-27 1982-10-05 Fujitsu Limited Integrated semiconductor device having insulated gate field effect transistors with a buried insulating film
US4246592A (en) * 1979-01-02 1981-01-20 Texas Instruments Incorporated High density static memory cell
NL8003612A (nl) * 1980-06-23 1982-01-18 Philips Nv Werkwijze ter vervaardiging van een halfgeleider- inrichting en halfgeleiderinrichting vervaardigd door toepassing van deze werkwijze.
JPS5944785A (ja) * 1982-09-06 1984-03-13 松下電工株式会社 発熱装置
EP0119059B1 (de) * 1983-03-09 1988-10-05 Kabushiki Kaisha Toshiba Integrierte Halbleiterschaltung mit Gattermatrixstruktur
JPS59163837A (ja) * 1983-03-09 1984-09-14 Toshiba Corp 半導体集積回路
JPS6035532A (ja) * 1983-07-29 1985-02-23 Fujitsu Ltd マスタスライス集積回路装置
JPS6047441A (ja) * 1983-08-26 1985-03-14 Fujitsu Ltd 半導体集積回路
US4649413A (en) * 1983-08-29 1987-03-10 Texas Instruments Incorporated MOS integrated circuit having a metal programmable matrix
JPH0828480B2 (ja) * 1983-09-30 1996-03-21 富士通株式会社 半導体集積回路装置
JPS60233838A (ja) * 1984-05-02 1985-11-20 Toshiba Corp 半導体集積回路装置
DE3586385T2 (de) * 1984-10-03 1993-01-07 Fujitsu Ltd Integrierte gate-matrixstruktur.
JP2845869B2 (ja) * 1985-03-25 1999-01-13 株式会社日立製作所 半導体集積回路装置

Also Published As

Publication number Publication date
EP0228320B1 (de) 1992-09-09
US4928164A (en) 1990-05-22
DE3686709T2 (de) 1993-01-14
JPS62119936A (ja) 1987-06-01
KR900003029B1 (ko) 1990-05-04
EP0228320A1 (de) 1987-07-08
KR870005463A (ko) 1987-06-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee