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DE3684309D1 - MULTI-PORT STORAGE AND SOURCE DEVICE FOR IMAGE POINT INFORMATION. - Google Patents

MULTI-PORT STORAGE AND SOURCE DEVICE FOR IMAGE POINT INFORMATION.

Info

Publication number
DE3684309D1
DE3684309D1 DE8686400976T DE3684309T DE3684309D1 DE 3684309 D1 DE3684309 D1 DE 3684309D1 DE 8686400976 T DE8686400976 T DE 8686400976T DE 3684309 T DE3684309 T DE 3684309T DE 3684309 D1 DE3684309 D1 DE 3684309D1
Authority
DE
Germany
Prior art keywords
memory
gating
register
information
masking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686400976T
Other languages
German (de)
Inventor
Thomas C Stockebrand
Joel D Kaufman
Vickery, Iii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of DE3684309D1 publication Critical patent/DE3684309D1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/34—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators for rolling or scrolling
    • G09G5/346—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators for rolling or scrolling for systems having a bit-mapped display memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Image Input (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Digital Computer Display Output (AREA)

Abstract

The chip includes a bit map memory and a control unit for enabling the intput and output of pixels and masking information to and from given addresses in the memory. A register for shifting stored pixel information is included. This register has data ports connected to data ports of the memory via a gating unit and a mask register is connected to the memory data ports via a second gating unit. The gating units are controlled by a second control unit.$The second control unit is capable of outputting a signal to the second gating unit to enable the transfer of masking information from the memory to the mask register and a second control signal to the first gating unit for enabling the transfer of pixel information from the memory to the shift register. The mask register is capable of transferring the masking information to the gating means for masking given bits of the pixel information. The memory pref. consists of a no. of units pack with a respective shift register.$
DE8686400976T 1986-05-06 1986-05-06 MULTI-PORT STORAGE AND SOURCE DEVICE FOR IMAGE POINT INFORMATION. Expired - Fee Related DE3684309D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP86400976A EP0245564B1 (en) 1986-05-06 1986-05-06 A multiport memory and source arrangement for pixel information

Publications (1)

Publication Number Publication Date
DE3684309D1 true DE3684309D1 (en) 1992-04-16

Family

ID=8196299

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686400976T Expired - Fee Related DE3684309D1 (en) 1986-05-06 1986-05-06 MULTI-PORT STORAGE AND SOURCE DEVICE FOR IMAGE POINT INFORMATION.

Country Status (3)

Country Link
EP (1) EP0245564B1 (en)
AT (1) ATE73566T1 (en)
DE (1) DE3684309D1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4953101A (en) * 1987-11-24 1990-08-28 Digital Equipment Corporation Software configurable memory architecture for data processing system having graphics capability
NL8801116A (en) * 1988-04-29 1989-11-16 Oce Nederland Bv METHOD AND APPARATUS FOR CONVERTING CONFIRMATION DATA TO GRID DATA
EP0410743B1 (en) * 1989-07-28 1996-02-21 Texas Instruments Incorporated Graphics display split-serial register system
JPH07501164A (en) * 1991-11-21 1995-02-02 イマジネイション テクノロジーズ リミテッド Video/graphics memory system
US5473566A (en) * 1994-09-12 1995-12-05 Cirrus Logic, Inc. Memory architecture and devices, systems and methods utilizing the same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4174536A (en) * 1977-01-21 1979-11-13 Massachusetts Institute Of Technology Digital communications controller with firmware control
US4546451A (en) * 1982-02-12 1985-10-08 Metheus Corporation Raster graphics display refresh memory architecture offering rapid access speed
JPS59180871A (en) * 1983-03-31 1984-10-15 Fujitsu Ltd semiconductor memory device

Also Published As

Publication number Publication date
ATE73566T1 (en) 1992-03-15
EP0245564A1 (en) 1987-11-19
EP0245564B1 (en) 1992-03-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee