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DE3684096D1 - Halbleiterspeichervorrichtung und -matrixanordnung. - Google Patents

Halbleiterspeichervorrichtung und -matrixanordnung.

Info

Publication number
DE3684096D1
DE3684096D1 DE8686113870T DE3684096T DE3684096D1 DE 3684096 D1 DE3684096 D1 DE 3684096D1 DE 8686113870 T DE8686113870 T DE 8686113870T DE 3684096 T DE3684096 T DE 3684096T DE 3684096 D1 DE3684096 D1 DE 3684096D1
Authority
DE
Germany
Prior art keywords
storage device
semiconductor storage
matrix arrangement
matrix
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686113870T
Other languages
English (en)
Inventor
Robert Chi-Foon Wong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3684096D1 publication Critical patent/DE3684096D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
    • G11C11/4113—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only with at least one cell access to base or collector of at least one of said transistors, e.g. via access diodes, access transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/10—SRAM devices comprising bipolar components
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
    • G11C11/4116—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only with at least one cell access via separately connected emittors of said transistors or via multiple emittors, e.g. T2L, ECL

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)
DE8686113870T 1985-10-28 1986-10-07 Halbleiterspeichervorrichtung und -matrixanordnung. Expired - Lifetime DE3684096D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/791,941 US4813017A (en) 1985-10-28 1985-10-28 Semiconductor memory device and array

Publications (1)

Publication Number Publication Date
DE3684096D1 true DE3684096D1 (de) 1992-04-09

Family

ID=25155303

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686113870T Expired - Lifetime DE3684096D1 (de) 1985-10-28 1986-10-07 Halbleiterspeichervorrichtung und -matrixanordnung.

Country Status (4)

Country Link
US (1) US4813017A (de)
EP (1) EP0222154B1 (de)
JP (1) JPS62102557A (de)
DE (1) DE3684096D1 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2585799B2 (ja) * 1989-06-30 1997-02-26 株式会社東芝 半導体メモリ装置及びそのバーンイン方法
US5377124A (en) * 1989-09-20 1994-12-27 Aptix Corporation Field programmable printed circuit board
US5400262A (en) * 1989-09-20 1995-03-21 Aptix Corporation Universal interconnect matrix array
US5040145A (en) * 1990-04-06 1991-08-13 International Business Machines Corporation Memory cell with active write load
US5020027A (en) * 1990-04-06 1991-05-28 International Business Machines Corporation Memory cell with active write load
US5300790A (en) * 1990-06-15 1994-04-05 Seiko Epson Corporation Semiconductor device
EP0481703B1 (de) * 1990-10-15 2003-09-17 Aptix Corporation Verbindungssubstrat mit integrierter Schaltung zur programmierbaren Verbindung und Probenuntersuchung
US5276638A (en) * 1991-07-31 1994-01-04 International Business Machines Corporation Bipolar memory cell with isolated PNP load
US5297089A (en) * 1992-02-27 1994-03-22 International Business Machines Corporation Balanced bit line pull up circuitry for random access memories
JPH11110969A (ja) * 1997-10-06 1999-04-23 Mitsubishi Electric Corp スタティック型半導体記憶装置
US10381068B2 (en) 2017-12-20 2019-08-13 International Business Machines Corporation Ultra dense and stable 4T SRAM cell design having NFETs and PFETs

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE65999C (de) * W. spielman in'Camden, Staat New-Jersey, V. St.A Eine für das Befahren des Hauptgleises selbstthätig wirkende Weiche
US3643235A (en) * 1968-12-30 1972-02-15 Ibm Monolithic semiconductor memory
NL7107040A (de) * 1971-05-22 1972-11-24
DE2165729C3 (de) * 1971-12-30 1975-02-13 Ibm Deutschland Gmbh, 7000 Stuttgart Monolithische, als Lese/Schreiboder als Festwertspeicher betreibbare Speicheranordnung
US3986178A (en) * 1975-07-28 1976-10-12 Texas Instruments Integrated injection logic random access memory
US4032902A (en) * 1975-10-30 1977-06-28 Fairchild Camera And Instrument Corporation An improved semiconductor memory cell circuit and structure
DE2700587A1 (de) * 1976-01-15 1977-07-21 Itt Ind Gmbh Deutsche Monolithisch integrierte i hoch 2 l-speicherzelle
DE2738678C3 (de) * 1977-08-27 1982-03-04 Ibm Deutschland Gmbh, 7000 Stuttgart Monolithisch integrierte Speicherzelle
US4112511A (en) * 1977-09-13 1978-09-05 Signetics Corporation Four transistor static bipolar memory cell using merged transistors
EP0005601B1 (de) * 1978-05-11 1983-03-02 Nippon Telegraph and Telephone Public Corporation Integrierte Halbleiterspeicherschaltung
US4366554A (en) * 1978-10-03 1982-12-28 Tokyo Shibaura Denki Kabushiki Kaisha I2 L Memory device
JPS6043024B2 (ja) * 1978-12-30 1985-09-26 富士通株式会社 半導体装置の製造方法
JPS5847792B2 (ja) * 1979-07-26 1983-10-25 富士通株式会社 ビット線制御回路
US4292675A (en) * 1979-07-30 1981-09-29 International Business Machines Corp. Five device merged transistor RAM cell
JPS5842556B2 (ja) * 1979-08-30 1983-09-20 富士通株式会社 半導体記憶装置
JPS5665395A (en) * 1979-10-30 1981-06-03 Fujitsu Ltd Bit-line voltage level setting circuit
DE3071976D1 (en) * 1979-11-28 1987-07-02 Fujitsu Ltd Semiconductor memory circuit device
US4302823A (en) * 1979-12-27 1981-11-24 International Business Machines Corp. Differential charge sensing system
US4387445A (en) * 1981-02-24 1983-06-07 International Business Machines Corporation Random access memory cell

Also Published As

Publication number Publication date
JPS62102557A (ja) 1987-05-13
EP0222154B1 (de) 1992-03-04
EP0222154A2 (de) 1987-05-20
EP0222154A3 (en) 1989-05-03
JPH0432547B2 (de) 1992-05-29
US4813017A (en) 1989-03-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee