DE3621682A1 - Device for transmitting signals and multi-frequency code receivers suitable for this purpose - Google Patents

Abstract

The invention makes use of the fact that in an OR operation on digital signals, none of the signals logically combined with one another are lost. The digital part-signals can be selected in such a manner that, with an arbitrary phase relationship between the part-signals, the aggregate signal reveals which of the part-signals are currently contained in the aggregate signal and which are not. Examples of suitably selected sets of part-signals are specified. The invention specifies a device for transmitting signals which makes use of this finding. A multi-frequency code receiver for recognising the individual part-signals is specified. <IMAGE>

Description

The invention relates to a device with a plurality of signal generators and detection circuits associated with them according to the preamble of claim 1 and a multi-frequency code receiver according to the preamble of claim 8.

Such a multi-frequency code receiver and such a device are known from DE-OS 24 36 691. This document describes a "multiple programming circuit" in which "various interrelated devices ... are to be operated simultaneously, in a specific order, alternately or in another way". The control signals for this are recorded as sound signals with different pitch (frequency) on a magnetic tape device. A sound channel is assigned to each control channel. Several control signals can also occur simultaneously, with which either several devices can be controlled simultaneously or, as indicated on page 3 below, by binary coding via n channels 2 ⁿ devices, but then not simultaneously. To run the program, the output signal of the magnetic tape device is fed to this circuit, which then works as a multi-frequency code receiver. This multi-frequency code receiver consists of an analog audio frequency filter with an assigned threshold value detector per control channel, which serve as a detection circuit. The same multi-frequency code receiver is used for programming, ie when recording on the magnetic tape, the individual audio frequency filters now being caused to oscillate by means of a feedback branch which can be switched on by hand, as a result of which they become signal generators.

These known arrangements are based on the principle of Frequency division multiplex. Thereby several signals on different Transmit frequencies over the same medium. The frequencies are determined by frequency-determining components set the transmitter and receiver of these signals can therefore be completely independent of each other. Also where the frequencies are far apart is still a not inconsiderable amount of circuitry what is required mainly on the analog structure is due.

Another common principle of transmission The principle is multiple signals over the same medium of time division multiplexing, in which the signals are the medium split time. Since time is not due to device constants Coordination must be determined of the different transmitters and receivers take place among themselves. This can be done, for example, by synchronization or by arbitration. Time division multiplexing devices have the advantage of digital circuits being able to be realized, which is pretty problem-free construction results, but for that the The disadvantage is that additional effort is necessary for the time coordination.

The invention has for its object a device for transmitting signals with a plurality of Signal generators and detection circuits and one to create suitable multi-frequency code receiver.

The object is achieved by a device according to claim 1 and a multi-frequency code receiver according to claim 8. Further refinements of the invention are can be found in the subclaims.

The invention takes advantage of the fact that in an OR Linking digital signals none of the other linked signals goes down. The digital partial signals can be selected so that at any Phase relationship of the partial signals to each other, the sum signal shows which of the partial signals is currently in the Sum signal are included and which are not. Examples suitably selected sets of partial signals are given.

The invention provides a device for transmitting Signals that take advantage of this knowledge. A multi-frequency code receiver for recognizing the individual partial signals is specified.

The following is the invention of exemplary embodiments with the help of the attached drawing explained further.  

Fig. 1 shows simple waveforms ( Fig. 1 a) and suitable simple multi-frequency receivers ( Fig. 1 b. .1 f);

Fig. 2 shows a multi-frequency code receiver for detecting a plurality of sub-signals whose frequencies are each spaced apart by one octave;

Fig. 3 shows a device for transmitting signals having a plurality of embodiments;

Fig. 4 shows an assembly of the device according to Fig. 3, and

Fig. 5 shows a known wired-OR circuit.

Fig. 1 shows a partial digital signals Sa and Sb, as well as the resulting by ORing resulting sum signal S = Sa V Sb. The signals Sa and Sb consist of regular pulse sequences with the period lengths Ta and Tb , in the example shown Ta : Tb = 1: 8. The sum signal S = Sa V Sb also has the period Tb in this example. It has individual pulses of length (Ta + Tb) / 2 and Ta / 2. With any phase shift of the partial signals Sa and Sb against one another, the longer individual pulse can dissolve into two parts with the lengths Ta / 2 and Tb / 2. If the sum signal is sampled with the clock Ta / 2, then this resolution is no longer recognizable. Depending on which of the sub-signals is included in the sum signal, different signal forms of the sum signal result, but the number of possible signal forms is very limited.

It is easy to see that even then a very limited number of possible waveforms if the Partial signals not OR-linked, but additively superimposed if the amplitudes add up. In this case too, the evaluation of the sum signal can done in the same or similar manner as in following for OR-linked and thus digital signals will be shown.

If, based on the specific application, it can be expected that the sampling times (clock Ta / 2) will meet with edges of the sum signal and errors may result, a clear evaluation can be made, for example, by a finer resolution (e.g. clock Ta / 4) Ta / 2) can be achieved.

The evaluation according to the Fig. 1 b to 1 e is such that the sum signal S with the timing Ta / 2 is input serially into a shift register and in that a device connected to the parallel outputs of the shift register decoding means evaluates the signal form in each case contained in the shift register. The shift register itself is not shown in the figures. This can be easily implemented by the person skilled in the art. The content of the shift register reflects the course of the waveform of the sum signal S shown in FIG. 1 a. The inputs of the decoding circuits shown in FIGS. 1 b to 1 e are therefore not routed to a shift register here, but instead point by arrows to the corresponding sections of the sum signal S in FIG. 1 a.

A signal a , which indicates whether the partial signal Sa is present or not, can be formed in accordance with the circuit in FIG. 1b by evaluating two signal values separated by Tb / 2 (1 and 9 in FIG. 1b).

These two points can only be at logic 1 at the same time if the partial signal Sa is contained in the sum signal S , the partial signal Sb has no influence here. This condition is certainly met once during the period Ta if Sa is present. An AND gate GUa with subsequent monoflop MF 1 is sufficient for decoding the partial signal Sa.

Also shown in FIG. 1b is a simple circuit for decoding the partial signal Sb and for emitting a signal b . It is sufficient here to evaluate two successive cells of the shift register (1 and 2), which is possible by means of an AND gate GUb with a subsequent monoflop MF 2 . The service life of the monoflop MF 2 must be somewhat longer than the period Tb .

The two decoding circuits in FIG. 1 b then together with the shift register and possibly a circuit for forming or regenerating the clock Ta / 2 for the shift register form a complete multi-frequency code receiver.

Compared to decoding the signal b , a relatively long shift register is required to decode the signal a . A modification for decoding the signal a , which also manages with a shorter shift register, is shown in FIG. 1 c. With an AND gate GUc , the input of which is assigned an inverter, and a monoflop MF 3 , it is determined whether the logic sequence 101 occurs at least once in a period of length Tb , which is only possible if the partial signal Sa is in the sum signal S is included.

A further modification is shown in FIG. 1 d, in which a circuit is shown which avoids the use of monoflops and only uses gates. On the one hand, the dependency on the absolute value of the period is no longer given; it is only the ratio of the periods that is decisive. On the other hand, the gates can also be implemented using programmable logic fields. Similar to the example according to FIG. 1 b, the AND gates GUda 1 and GUda 2 determine whether the partial signal Sa is present. If the partial signal Sa is present, this is always alternately determined by one of the two AND gates GUda 1 and GUda 2 , their outputs are therefore combined by an OR gate GDa , at the output of which the signal a can then be tapped. Correspondingly, the partial signal Sb is determined by four AND gates GUdb 1 , GUdb 2 , GUdb 3 and GUdb 4 and an OR gate GOb and is indicated by signal b .

The decoding devices of Fig. 1 d have a total of four inputs (taps 1, 2, 9 and 10) and two outputs for the signals a and b. Every combination of logical signals at these four inputs is assigned exactly one pair of values at the output. As shown in FIG. 1e, this assignment can also be carried out by a read-only memory M with four address inputs A 0 , A 1 , A 2 , A 3 and a memory capacity of two bits per address and thus two data outputs D 0 , D 1 .

A completely different type of decoding is shown in the example in FIG. 1 f. With this circuit, the lengths of the individual pulses contained in the sum signal S are counted and the partial signals involved are determined therefrom. A shift register is not required here. The input signal of this circuit is the sum signal S itself, which is given via a delay element V to the clearing input Cl (Clear) of a counter Z. At the clock input Ck (clock) of the counter, which is enabled with Clear = 1, there is a clock with the period Ta / 2. If no individual pulses are detected by the counter Z , then neither of the two partial signals is contained in the sum signal S. Whenever the counter Z is already reset to 1, the partial signal Sa is contained in the sum signal S. Whenever the counter Z counts at least to 2, the partial signal Sb is present. It is therefore sufficient to use a counter that can distinguish between counts 0, 1 and 2; the example shows a two-stage binary counter that can count from 0 to 3.

If a monoflop MF 5 is set when the counter reading 2 is reached via its data output D 1 and the service life of the monoflop MF 5 is slightly more than a period Tb , then the signal b can be tapped at its output Q , which shows when the partial signal Sb in Sum signal S is included. So that the monoflop MF 5 can function as desired as a memory, the memory content of which is at 1 as long as the partial signal Sb is present, it must be retriggerable, that is, an input pulse at its clock input Ck must also have an effect if its useful life has not yet expired is. This also applies to the MF 1 , MF 2 and MF 3 monoflops already mentioned above. The fact that the counter Z does not count the full length of the pulse, but is reset at the counter reading 3 and starts all over again, whereby the monoflop MF 5 is then triggered again at counter reading 2, since this only has to be determined whether the Meter reading 2 is reached at all, not whether it is exceeded.

With regard to the partial signal Sa, on the other hand, only the final reading of the counter Z is important, but it is sufficient to determine whether the counter reading is even or odd at the end. The presence of the partial signal Sa leads to odd counts occurring. The sum signal S is therefore fed to the clock input Ck of a monoflop MF 4 , which has a further input which is connected to the data output D 0 of the counter Z. The other input is a preparation input, ie the monoflop MF 4 is set or retriggered when a transition from 1 to 0 appears at the clock input Ck (negative edge, filled arrow) and a 1 is present at the other input. At the end of each individual pulse that leads to an odd counter reading, the monoflop MF 4 is triggered or retriggered. The signal a is then present at its output Q. Immediately after the end of a single pulse, the counter Z is cleared again via the delay element V and stopped until the next single pulse begins.

Using the simple example shown in FIG. 1, it was shown that, and how with little structure, it is possible to separate two suitably selected and superimposed partial signals. This principle can also be applied to more than two partial signals and also to those whose frequencies are not as far apart as in the example shown. It is readily apparent that a computing unit can also take over or take over the function of the multi-frequency code receiver according to this principle.

Such a multi-frequency code receiver can also be easily supplemented so that it still works satisfactorily if occasional interference occurs in the signal to be received. For this purpose, it must be provided with an additional device for each partial signal, which only displays the respective partial signal as recognized if it has been recognized with a predetermined minimum frequency during a predetermined time. The output of the AND gate GUa in FIG. 1b, for example, changes eight times between 1 and 0 in the case of partial signals Sa present during a period Tb. The signal Sa could, for example, be recognized if a 1 occurs at least four times during this period. This could be determined, for example, by two counters, one of which determines the period (from the clock with which the shift register is also clocked), while the second counter counts how often a 1 occurs.

A multi-frequency code receiver is now described with reference to FIG. 2, which is suitable for those partial signals whose frequencies are in the ratio 1: 2 to one another and which have a pulse-pause ratio of 1: 1. Such partial signals can easily be derived from a basic cycle by continued halving. This multi-frequency code receiver has a binary counter with a clock input Ck , an erase input Cl and several data outputs. An eight-stage counter Z with eight data outputs D 0 to D 7 is shown . Is located at the clock input CK of a clock signal T 0/2, whose frequency is twice as high as that of the partial signal T 0 with the highest frequency. At the clearing input Cl of the counter Z , the sum signal S is present as an input signal via a delay element V. Each stage of the counter Z is assigned a memory cell Sp 0 to Sp 7 , each with a clock input Ck , a data input D and an output Q. The data inputs D of the memory cells Sp 0 to Sp 7 are connected to the data outputs D 0 to D 7 of the counter Z. The sum signal S is applied to all clock inputs Ck of the memory cells Sp 0 to Sp 7 , so that at the end of each individual pulse the counter reading of the counter Z is transferred to the memory cells. The counter Z is then stopped and reset via the delay element V. Each stage of the counter and the associated memory cell corresponds to one of the partial signals, which are referred to here as " T 0 " to " T 7 ", the designation reflecting the respective period. The memory cells Sp 0 to Sp 7 could, as in the example according to FIG. 1 f, be monoflops. However, an alternative with D flip-flops is shown here. The outputs Q of the D flip-flops are connected to the data inputs D via OR gates G 0 to G 7 , the other inputs of the OR gates G 0 to G 7 being connected to the data outputs D 0 to D 7 of the counter Z. are. In contrast to monoflops, the D flip-flops must be reset after each query. For this purpose, they have extinguishing inputs C1 which are connected to one another and to the output of a divider T. The divider T is a binary counter like the counter Z and has as many levels as this. At its clock input Ck also the same clock T 0/2 is applied. However, it is not reset. If the period T 7 of the partial signal with the lowest frequency has passed, then the sum signal has been completely evaluated because the sum signal also has the period T 7 . Now the D flop flops can be reset by the output signal of the divider Z. If necessary, this signal can also be used to trigger a query. Another D-flip-flop could be connected downstream of the D-flip-flops, for example, the clock inputs of which are connected to the output of the divider T and the data inputs of which are connected to the data outputs Q of the D-flip-flops Sp 0 to Sp 7 are. The query result would then be available continuously, and not only briefly at the end of a query period.

The number of stages of the multi-frequency code receiver according to FIG. 2 can be varied as desired, in particular because counters Z and divider T can also be constructed such that they have one D flip-flop per stage.

With reference to FIG. 3 shows a device will now be described for transmission of signals, which can preferably be operated with a multi-frequency code receiver of the type described above. This device is preferably suitable for submitting fault reports from decentralized modules to central devices. The example in FIG. 3 is chosen so that several embodiments can be described using this example. The example contains a total of four devices according to the invention, which are connected to one another, partly by superimposition.

The first such device consists of a plurality of signal generators SG 11 to SG 18 , a receiver E 4 and a signal bus B 4 . The signal generators are digital circuits which emit digital signals which differ in their frequency from one another and which can be switched on and off by electrical signals. Such signal generators are familiar to the person skilled in the art, for example frequency filters which derive pulse trains of different frequencies from a common basic clock. The receiver E 4 contains a detection circuit for each signal generator, which is able to distinguish the partial signal coming from the associated signal generator from other partial signals contained in the sum signal. The detection circuits are preferably combined to form a multi-frequency code receiver as described above. The outputs of all signal generators SG 11 to SG 18 and the inputs of the detection circuits are connected to one another by the signal bus B 4 . The outputs of the signal generators are preferably connected to the signal bus B 4 by a wired-or circuit, which results in an OR operation of the output signals and thus a digital sum signal.

The shape of the signal bus (line, star, tree, network or The combination of these is irrelevant, including the connection individual signal generators, detection circuits or about an additional receiver with the signal bus changing points is possible.  

This device is now preferably used to monitor different units of a larger system. For this purpose, the signal generators are each assigned to a unit to be monitored and spatially connected to it. The signal generators can be switched on and off by means of error messages or alarms. The signal generators are switched on during fault-free operation, otherwise they are switched off or fail. The receiver E 4 can thus easily trigger an alarm. In addition to the units to be monitored, the function of the monitoring device itself, including the signal bus, is also monitored. Only the receiver E 4 is excluded from this monitoring. However, it is easily possible to connect another receiver of the same type to the signal bus B 4 , which improves both the monitoring possibility and the security.

A second device according to the invention shown in FIG. 3 has a plurality of signal generators SG 2 , SG 4 and SG 5 to SG 8 , two receivers E 2 and E 5 and a signal bus B 1 . Another (third) device of the same type with a signal bus B 2 is superimposed on this device. Each of the signal generators SG 2 , SG 4 and SG 5 to SG 8 is assigned a plurality of further signal generators, the outputs of which are connected to the signal bus B 2 . The further signal generators are not shown separately in FIG. 3; they are to be regarded as combined with the signal generators SG 2 , SG 4 and SG 5 to SG 8 . Each of these signal generators SG 2 , SG 4 and SG 5 to SG 8 is thus constructed in such a way that it can emit one frequency on the signal bus B 1 and several frequencies on the signal bus B 2 . Each signal generator must have a different frequency on the signal bus B 1 , while the same frequency can also come on the signal bus B 2 from different signal generators. The signal generators are now switched in such a way that all possible frequencies are present on signal bus B 1 in the case of trouble-free operation and that no signal occurs on signal bus B 2 . When a fault occurs, the corresponding frequency on signal bus B 1 is then interrupted and the type of fault is identified in more detail on signal bus B 2 . This can be done both by assigning a single frequency to each type of fault and by assigning a binary value to each frequency, which results in a multi-frequency code and by assigning a multi-frequency code word to each type of fault. Total failures of a unit can also be identified in this way, and in the case of the multi-frequency code an error accumulation can be treated like a total failure.

A fourth device according to the invention shown in FIG. 3 has a plurality of signal generators SG 31 to SG 34 , a signal bus B 3 and a receiver E 3 . The receiver E 3 is part of a transfer unit ESG 3 , which also contains signal generators that can send fault messages to the signal buses B 1 and B 2 . The delivery of a signal to the signal bus B 1 then indicates that there is no fault message, the delivery of a signal to the signal bus B 2 indicates in the event of a failure which is disturbed by one of the signal generators SG 31 to SG 34 monitored subunit. The transfer unit ESG 3 is described in more detail below with reference to FIG. 4.

In the same way as the fourth device described last, the first device described first, which is already functional by the receiver E 4 , is connected to the signal buses B 1 and B 2 by a transfer unit ESG 1 and thus also by the receiver E. 2 and E 3 can be monitored. The transfer unit ESG 1 corresponds to the transfer unit ESG 3 .

The transfer unit ESG 3 of the arrangement according to FIG. 3 will now be described with reference to FIG. 4. It contains the aforementioned receiver E 3 , the input of which is connected to the signal bus B 3 , a signal generator SG 3 , the output of which is connected to the signal bus B 1 , four signal generators SG 301 to SG 304 , the outputs of which are connected to the signal bus B 2 an AND gate U 30 and four inverters I 31 to I 34 . The receiver E 3 evaluates the signal S 3 present on the signal bus B 3 and outputs the signals S 31 to S 34 at its outputs. As long as all four signals S 31 to S 34 are at 1, the signal generator SG 3 is switched on via the AND gate U 30 and thus indicates on the signal bus B 1 that all subunits monitored by the signal generators SG 31 to SG 34 as well the transfer device SG 3 shows no malfunction. If a fault is indicated by the failure of one of the signals S 31 to S 34 , then the signal generator SG 3 is switched off and one of the signal generators SG 301 to SG 304 is switched on via the associated inverter I 31 to I 34 .

On the basis of Fig. 5 will be explained briefly what is meant in the present application as a wired-OR circuit. The outputs of the signal generators SG 11 to SG 12 and the signal bus B 4 are shown . Each output has a resistor R 1 or R 2 and a transistor T 1 or T 2 . The resistor is connected to the positive level H , the transistor to ground. The common connection point of resistor and transistor is connected to signal bus B 4 . If the transistor in any of the connected signal generators is conductive, then the signal bus B 4 is grounded, otherwise it is at the positive level H. Another widespread alternative is to omit the individual resistors R 1 and R 2 and to connect the connection point, here the signal bus B 4 , to the positive level H via a resistor R. The individual outputs then have an open collector.

Such a facility can also be used for one, albeit not too fast, data transmission can be used. A period duration common to all partial signals, preferably the smallest common multiple of the periods of the partial signals, indicates the clock which for example by switching one of the partial signals off and on can be contained in the sum signal.

It has already been noted that a phase shift of the partial signals against each other without influence the evaluability is. Also deviations from the target value of the frequencies of the partial signals and of the evaluation used clocks are without influence as long as long the resulting phase shift within an evaluation interval less than one clock period remains. An evaluation interval is in the Usually equal to the period duration common to all partial signals, this is usually the period of the partial signal with the lowest frequency. Unless the frequencies can be held within this framework no mutual synchronization required.

Claims (16)

1. Device with a plurality of signal generators (SGx) and a plurality of detection circuits (Ey ) assigned to the signal generators (SGx) , in which the outputs of all signal generators (SGx) and the inputs of all detection circuits (Ey) are each connected to one another and in which the output signals of the signal generators (SGx) differ from one another by their frequency, characterized in that the signal generators (SGx) and the detection circuits (Ey) are digital circuits which emit and receive digital signals, and the signal generators (SGx) are input by digital electrical signals - And can be switched off that the outputs of the signal generators (SGx) and the inputs of the detection circuits (Ey) are interconnected by a signal bus (B 1 , B 3 , B 4 ) and that the outputs of the signal generators (SGx) are connected to the signal bus (B 1 , B 3 , B 4 ) are connected so that there is an OR operation for the signals. 2. Device according to claim 1, characterized in that a wired-or circuit for realizing the OR operation is present ( Fig. 5). 3. Device according to claim 1 or 2, characterized characterized in that each signal generator to be monitored Unit associated with a larger system and  spatially connected to this that the detection circuits with facilities for error reporting or Alarm signals are connected to each signal generator is switched on as long as the one to be monitored Unit shows no interference and that everyone Signal generator is off or fails when the unit to be monitored is disrupted. 4. Device according to claim 3, characterized in that this device is superimposed on a second device according to claim 1 or 2 with a second signal bus (B 2 ) that each unit to be monitored has a plurality of further signal generators (SG 301 ). . ., SG 304 ), the outputs of which are connected to the second signal bus (B 2 ), that the further signal generators (SG 301 , ... , SG 304 ) are switched off as long as the unit to be monitored does not reveal any malfunction, and that If a malfunction occurs in the unit to be monitored, the other signal generators (SG 301 , ... , SG 304 ) report a malfunction, which characterizes the type of malfunction. 5. Device according to claim 4, characterized in that at least one unit to be monitored contains a further device (B 3 , SG 31 , ..., SG 34 , E 3 ) according to claim 3, which is intended for monitoring subunits and that the fault message contains information about which subunit is faulty. 6. Device according to claim 1 or 2, characterized in that a partial signal in the rhythm of a period duration common to all partial signals and is turned on and as a clock for data transmission by means of the other partial signals. 7. Device according to one of claims 1 to 6, characterized in that further identical detection circuits (E 2 , E 5 ) for detecting the same signal at other points of the signal bus (B 1 , B 2 ) are connected. 8. Multi-frequency code receiver for determining the partial signals (T 0 ,..., T 7 , Sa, Sb, S 31 , ... , S 34 ) contained in an input signal (S, S 3), each of which is characterized by a specific frequency Characterize from a limited number of individual frequencies, characterized in that the multi-frequency code receiver forms a set of associated detection circuits (E 2 , E 3 , E 4 , E 5 ) of a device according to one of Claims 1 to 7 and in that the input signal (S, S 3 ), which consists of a sequence of individual pulses (rectangular pulses), is examined with regard to the portions of partial signals contained in the individual pulses (T 0 ,..., T 7 , Sa, Sb, S 31 , ... , S 34 ) . 9. Multi-frequency code receiver according to claim 8, characterized characterized in that the lengths of the individual pulses counted and the partial signals involved be determined. 10. Multi-frequency code receiver according to claim 8, characterized in that a shift register and a decoding device ( Fig. 1 b, .. , Fig. 1 e) are present, that the input signal is entered serially in the shift register and that the inputs of the decoding device the parallel outputs of the shift register are connected. 11. Multi-frequency code receiver according to claim 9, for partial signals whose frequencies are in the ratio 1: 2 to each other and which have a pulse-pause ratio of 1: 1, characterized in that a k-stage binary counter (Z) with a clock input (Ck ), a clear input (CL) and k data inputs (D 0, D 1,..., D is available 7), at whose clock input (Ck), a clock signal (Ta / 2, T 0/2) is applied, a frequency twice is as high as that of the partial signal (Sa, T 0 ) with the highest frequency and at the clearing input (Cl) the input signal is applied via a delay element (V) that k memory cells (Sp 0 , Sp 1 , ... , Sp 7 ), each with a clock input (Ck) , a data input (D) and a data output (Q) , that the data inputs (D) of the memory cells (Sp 0 , Sp 1 , ... , Sp 7 ) with the data outputs ( D 0 , D 1 , ... , D 7 ) of the binary counter (Z) are connected and that the input signal (S) to all clock inputs (Ck) of the memory cells (Sp 0 , Col 1 ,. . ., Sp 7 ) is created so that the memory cells (Sp 0 , Sp 1 ,..., Sp 7 ) take over the count of the binary counter (Z) before it is reset. 12. Multi-frequency code receiver according to claim 11, characterized in that the memory cells are monostable multivibrators (Sp 1 ), the service life of which is approximately equal to the period of the partial signal (Sb) with the lowest frequency. 13. Multi-frequency code receiver according to claim 11, characterized in that the memory cells are D flip-flops (Sp 0 , Sp 1 ,..., Sp 7 ) with clear inputs (Cl) that their data outputs (Q) via OR gates ( G 0 ,..., G 7 ) are connected to the data inputs (D) , the other inputs of the OR elements (G 0 ,..., G 7 ) being connected to the data outputs (D 0 ,..., D 7 ) the binary counter (Z) are connected and that their clear inputs (Cl) are connected to each other and connected in such a way that they are reset after each query. 14. Multi-frequency code receiver according to claim 10, characterized in that the decoding device is a multi-digit addressable memory (M) , preferably a read-only memory and that the number of digits is equal to the number of partial signals to be decoded ( Fig. 1 e). 15. Multi-frequency code receiver according to claim 10, characterized in that the decoding device contains logic modules (gates) ( Fig. 1 b. .1 d). 16. Multi-frequency code receiver according to one of claims 8 to 15, characterized in that means are provided which have an output signal (a, b, "T 0 ",..., " T 7 ") which enables the detection of a partial signal (Sa, , was found to the sub-signal several times or for a certain period 7) displays.. Sb, T 0,., T, delayed so long.