DE3504199A1 - Process for preparing polycrystalline silicon layers having smooth surfaces - Google Patents

Abstract

The polysilicon deposition is carried out in two stages with an interposed inert-gas flushing step, a first stage involving a deposition (3a), which is thinner compared with the second stage, of polycrystalline silicon, immediately followed by the second stage in which, in the same reactor and at the same temperature, the polysilicon deposition (3b) is terminated. The process avoids "hillocks" (4) in the polysilicon layer (3) deposited on single-crystal silicon (1) and is used in the fabrication of low-resistance base terminals in bipolar transistor circuits. <IMAGE>

Description

Process for the production of polycrystalline silicon

layers with smooth surfaces.

The invention relates to a method for producing from polycrystalline Silicon existing layers with smooth surfaces on predominantly of single crystal Silicon existing substrates, such as those in particular as low-resistance base connections used in bipolar transistor integrated circuits by chemical Deposition from the gas phase at low pressure (LPCVD = low presseure chemical vapor deposition).

Process for depositing polycrystalline silicon using the LPCVD process are for example from the article by J. Kamins to J. Electrochem. Soc., March 1980, Pages 686 to 690, to be found. When deposited on silicon oxide a surface roughness in the range of 20 nm. However, if the substrate consists entirely or partially of single-crystal silicon, it was found that on the monocrystalline silicon the growth of individual, Particularly large crystallites can appear, which act as "bumps" over the polysilicon surface protrude clearly.

These bumps are, as they are during the subsequent dry etching of the Polysilicon are not leveled, but are transferred essentially conformally become very detrimental in the manufacture of semiconductor integrated circuits.

In the case of a self-aligned bipolar transistor, this leads to that the cusp structure is either carried over into the mono-area of the emitter (see Figure 1), or, that p + polysilicon residues remain in the emitter area (see Figure 2).

The problem of the "bumpy polysilicon layer on the monocrystalline Silicon areas has not yet been resolved. The prevention of hump formation by leaving the natural oxide on the mono-silicon field provides with regard to on the electrical properties of the transistor is not an advantageous way. Different surface treatments of the mono-silicon do not have to either a reproducible influence on the roughness of the deposited polysilicon layers guided.

For a leveling of an already existing, granular layer stands currently only one wet etching step available. Here, the polysilicon layer is first used Etched through just a little dry or a residual layer (of a few 10 nm) is left. Then the wet etching then takes place, for example with a mixture of one Part hydrofluoric acid, three parts nitric acid, sixteen parts acetic acid, which is selective compared to the p poly / n mono-regions. However, this method is difficult to reproduce and unreliable.

The object of the invention is therefore to provide a process that is easily reproducible for the production of polysilicon layers on monocrystalline silicon substrates indicate, in which the, the electrical properties of a bipolar transistor annoying humps can be avoided.

This task is performed in a method of the type mentioned at the beginning solved in that the deposition process in two stages with an interposed Inert gas purging step is carried out, in a first stage one opposite the second stage carried out thinner deposition of polycrystalline silicon and immediately thereafter in the second stage in the same reactor and at the same temperature the Polysilicon deposition ended will.

It is within the scope of the invention that the layer thickness of the first polycrystalline silicon layer to 10 to 20 nm and the deposition temperature im Range from 620 to 650 ° C, preferably at 630 ° C, is set.

According to a particularly favorable embodiment according to the teaching the invention is the inert gas purging step with nitrogen in a period of time Range performed from 10 to 30 minutes.

In the method according to the teaching of the invention, one of the substrate outgoing grain growth leading to individual, particularly large grains thereby prevented that the process is carried out so that the grain growth with many small Crystallites begins. Due to the double separation according to the invention without an intermediate It is possible to remove the substrate wafers from the reactor without generating a natural oxide between the two layers forming the silicon substrate to prevent induced humps.

Further details are explained in more detail with reference to FIGS. Figures 1 and 2 show the appearance of the "bumps" during the deposition of polycrystalline silicon on a single crystal silicon substrate and the Figure 3 has the same structure as Figure 1, but without the humps, as they are after Process according to the invention is obtained.

From Figure 1 it can be clearly seen how the hump-like Outgrowths 4 transferred almost conformally (4a) to all subsequent layers. The following apply Reference Characters: 1 = single crystalline silicon substrate, 2 = areas made of Si02, 3 = polysilicon layer, 4, 4a = hump-like outgrowths and 5 = on polysilicon deposited silicon oxide acting as an intermediate oxide.

FIG. 2: If the polysilicon layer 3 according to FIG. 1 is purely dry etched through, the "bumps" 4b remain on the silicon substrate 1 (emitter window with bipolar transistor). More overetch will only result in a transfer the surface shape on the monosilicon area 1.

The deposition of a further layer 5, for example of intermediate oxide and their etching back also leads to the generation of spacers on the polysilicon flanks 3 at the steep humps flanks 4 to form a spacer-like coat.

FIG. 3 shows the structure after the implementation of the invention Procedure. The first polycrystalline silicon layer is denoted by the reference numeral 3a (10 to 20 nm thick) and with 3b that after 10 to 30 minutes of inert gas purging the second polycrystalline silicon layer was deposited. Otherwise The same reference numerals apply as in FIG. 1.

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Claims (4)

Claims 1. A method for producing from polycrystalline Silicon existing layers with smooth surfaces on predominantly of single crystal Silicon existing substrates, such as those in particular as low-resistance base connections used in bipolar transistor integrated circuits by chemical Deposition from the gas phase at low pressure (LPCVD = low presseure chemical vapor deposition), d u r c h e k e n n -z e i c h n e t that the deposition process carried out in two stages with an intermediate inert gas purging step is, in a first stage, compared to the second stage, thinner deposit (3a) is carried out by polycrystalline silicon and immediately thereafter in the second stage in the same reactor and at the same temperature the polysilicon deposition (3b) is ended. 2. The method according to claim 1, d a d u r c h g e -k e n n z e i c h n e t that the layer thickness of the first polycrystalline silicon layer (3a) 10 to 20 nm is set. 3. The method according to claim 1 and / or 2, d a d u r c h g e k e n n indicate that the deposition temperature is in the range from 620 to 650 ° C, preferably at 630 ° C. 4. The method according to at least one of claims 1 to 3, d a d u It is noted that the inert gas purging step has a duration is carried out in the range of 10 to 30 minutes and with nitrogen as the purge gas.