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DE3481560D1 - Mechanismus fuer die realisierung von in einem operationszyklus ablaufenden fallenbefehlen in einem rechnersystem mit primitivem befehlssatz. - Google Patents

Mechanismus fuer die realisierung von in einem operationszyklus ablaufenden fallenbefehlen in einem rechnersystem mit primitivem befehlssatz.

Info

Publication number
DE3481560D1
DE3481560D1 DE8484106175T DE3481560T DE3481560D1 DE 3481560 D1 DE3481560 D1 DE 3481560D1 DE 8484106175 T DE8484106175 T DE 8484106175T DE 3481560 T DE3481560 T DE 3481560T DE 3481560 D1 DE3481560 D1 DE 3481560D1
Authority
DE
Germany
Prior art keywords
realization
computer system
command set
operation cycle
primitive command
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8484106175T
Other languages
English (en)
Inventor
Marc Alan Auslander
John Cocke
Hsieh Tung Hao
Peter Willy Markstein
George Radin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3481560D1 publication Critical patent/DE3481560D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)
  • Devices For Executing Special Programs (AREA)
DE8484106175T 1983-06-30 1984-05-30 Mechanismus fuer die realisierung von in einem operationszyklus ablaufenden fallenbefehlen in einem rechnersystem mit primitivem befehlssatz. Expired - Lifetime DE3481560D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/509,733 US4589065A (en) 1983-06-30 1983-06-30 Mechanism for implementing one machine cycle executable trap instructions in a primitive instruction set computing system

Publications (1)

Publication Number Publication Date
DE3481560D1 true DE3481560D1 (de) 1990-04-12

Family

ID=24027878

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484106175T Expired - Lifetime DE3481560D1 (de) 1983-06-30 1984-05-30 Mechanismus fuer die realisierung von in einem operationszyklus ablaufenden fallenbefehlen in einem rechnersystem mit primitivem befehlssatz.

Country Status (4)

Country Link
US (1) US4589065A (de)
EP (1) EP0130378B1 (de)
JP (1) JPS6014341A (de)
DE (1) DE3481560D1 (de)

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US4719565A (en) * 1984-11-01 1988-01-12 Advanced Micro Devices, Inc. Interrupt and trap handling in microprogram sequencer
US4747046A (en) * 1985-06-28 1988-05-24 Hewlett-Packard Company Mechanism for comparing two registers and storing the result in a general purpose register without requiring a branch
JPS6298434A (ja) * 1985-10-25 1987-05-07 Hitachi Ltd デ−タ処理システム
US4766566A (en) * 1986-08-18 1988-08-23 International Business Machines Corp. Performance enhancement scheme for a RISC type VLSI processor using dual execution units for parallel instruction processing
US5133072A (en) * 1986-11-13 1992-07-21 Hewlett-Packard Company Method for improved code generation in reduced instruction set computers
FR2607607B1 (fr) * 1986-12-01 1991-05-24 Heudin Jean Claude Machine informatique destinee a l'execution de traitements symboliques pour les applications de l'intelligence artificielle
US4992934A (en) * 1986-12-15 1991-02-12 United Technologies Corporation Reduced instruction set computing apparatus and methods
US5341482A (en) * 1987-03-20 1994-08-23 Digital Equipment Corporation Method for synchronization of arithmetic exceptions in central processing units having pipelined execution units simultaneously executing instructions
JPH01241636A (ja) * 1988-03-17 1989-09-26 Internatl Business Mach Corp <Ibm> データ処理システム
US5155817A (en) * 1988-04-01 1992-10-13 Kabushiki Kaisha Toshiba Microprocessor
US5083263A (en) * 1988-07-28 1992-01-21 Sun Microsystems, Inc. BISC with interconnected register ring and selectively operating portion of the ring as a conventional computer
EP0437615B1 (de) * 1989-06-14 1998-10-21 Hitachi, Ltd. Hierarchischer vorsuch-typ dokument suchverfahren, vorrichtung dazu, sowie eine magnetische plattenanordnung für diese vorrichtung
US5220625A (en) * 1989-06-14 1993-06-15 Hitachi, Ltd. Information search terminal and system
AU7305491A (en) * 1990-01-29 1991-08-21 Teraplex, Inc. Architecture for minimal instruction set computing system
US5140644A (en) * 1990-07-23 1992-08-18 Hitachi, Ltd. Character string retrieving system and method
DE4211245B4 (de) * 1991-04-05 2009-05-14 Kabushiki Kaisha Toshiba, Kawasaki Prozessorsystem in Parallelverarbeitungsbauart und Verfahren zu dessen Steuerung
EP0544083A3 (en) * 1991-11-26 1994-09-14 Ibm Interleaved risc-type parallel processor and processing methods
WO1995001601A1 (en) * 1993-07-02 1995-01-12 Oakleigh Systems, Inc. High-speed cpu interconnect bus architecture
US5440703A (en) * 1993-09-20 1995-08-08 International Business Machines Corporation System and method for saving state information in a multi-execution unit processor when interruptable instructions are identified
US5694587A (en) * 1995-03-31 1997-12-02 International Business Machines Corporation Specialized millicode instructions for test PSW validity, load with access test, and character translation assist
US5611062A (en) * 1995-03-31 1997-03-11 International Business Machines Corporation Specialized millicode instruction for string operations
US5754810A (en) * 1996-03-12 1998-05-19 International Business Machines Corporation Specialized millicode instruction for certain decimal operations
US5621909A (en) * 1996-03-12 1997-04-15 International Business Machines Corporation Specialized millicode instruction for range checking
JP3391653B2 (ja) 1997-04-16 2003-03-31 株式会社クボタ リアディスチャージモーアユニット及び芝刈機
US6035390A (en) * 1998-01-12 2000-03-07 International Business Machines Corporation Method and apparatus for generating and logically combining less than (LT), greater than (GT), and equal to (EQ) condition code bits concurrently with the execution of an arithmetic or logical operation
US6567975B1 (en) * 1999-11-08 2003-05-20 Sun Microsystems, Inc. Method and apparatus for inserting data prefetch operations using data flow analysis
US6598153B1 (en) * 1999-12-10 2003-07-22 International Business Machines Corporation Processor and method that accelerate evaluation of pairs of condition-setting and branch instructions
US7861071B2 (en) * 2001-06-11 2010-12-28 Broadcom Corporation Conditional branch instruction capable of testing a plurality of indicators in a predicate register
US7127593B2 (en) * 2001-06-11 2006-10-24 Broadcom Corporation Conditional execution with multiple destination stores
US6986025B2 (en) * 2001-06-11 2006-01-10 Broadcom Corporation Conditional execution per lane
US8447962B2 (en) * 2009-12-22 2013-05-21 Intel Corporation Gathering and scattering multiple data elements
US7984273B2 (en) 2007-12-31 2011-07-19 Intel Corporation System and method for using a mask register to track progress of gathering elements from memory
US10387151B2 (en) 2007-12-31 2019-08-20 Intel Corporation Processor and method for tracking progress of gathering/scattering data element pairs in different cache memory banks
US10175990B2 (en) 2009-12-22 2019-01-08 Intel Corporation Gathering and scattering multiple data elements
US8972697B2 (en) 2012-06-02 2015-03-03 Intel Corporation Gather using index array and finite state machine
WO2013180738A1 (en) 2012-06-02 2013-12-05 Intel Corporation Scatter using index array and finite state machine
US9405534B2 (en) 2013-01-21 2016-08-02 Tom Yap Compound complex instruction set computer (CCISC) processor architecture
US9110657B2 (en) 2013-01-21 2015-08-18 Tom Yap Flowchart compiler for a compound complex instruction set computer (CCISC) processor architecture

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5140772B2 (de) * 1971-07-26 1976-11-05
US3827029A (en) * 1972-09-25 1974-07-30 Westinghouse Electric Corp Memory and program protection system for a digital computer system
US4074353A (en) * 1976-05-24 1978-02-14 Honeywell Information Systems Inc. Trap mechanism for a data processing system
SE456051B (sv) * 1980-02-11 1988-08-29 Western Electric Co Digital processoranordning anordnad for pipeline-databehandlingsoperationer
JPS5750050A (en) * 1980-09-09 1982-03-24 Toshiba Corp Microprogram control type electronic computer
JPS5860355A (ja) * 1981-10-07 1983-04-09 Nec Corp 情報処理装置

Also Published As

Publication number Publication date
EP0130378B1 (de) 1990-03-07
JPH0228173B2 (de) 1990-06-21
EP0130378A2 (de) 1985-01-09
US4589065A (en) 1986-05-13
JPS6014341A (ja) 1985-01-24
EP0130378A3 (en) 1987-10-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee