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DE3480960D1 - Speichereinrichtung mit registerumtauschfunktion. - Google Patents

Speichereinrichtung mit registerumtauschfunktion.

Info

Publication number
DE3480960D1
DE3480960D1 DE8484113029T DE3480960T DE3480960D1 DE 3480960 D1 DE3480960 D1 DE 3480960D1 DE 8484113029 T DE8484113029 T DE 8484113029T DE 3480960 T DE3480960 T DE 3480960T DE 3480960 D1 DE3480960 D1 DE 3480960D1
Authority
DE
Germany
Prior art keywords
memory device
replacement function
register replacement
register
function
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8484113029T
Other languages
English (en)
Inventor
Tomotaka C O Patent Divi Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3480960D1 publication Critical patent/DE3480960D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Information Transfer Systems (AREA)
  • Logic Circuits (AREA)
  • Executing Machine-Instructions (AREA)
DE8484113029T 1983-10-31 1984-10-29 Speichereinrichtung mit registerumtauschfunktion. Expired - Lifetime DE3480960D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58203837A JPS6095651A (ja) 1983-10-31 1983-10-31 記憶装置

Publications (1)

Publication Number Publication Date
DE3480960D1 true DE3480960D1 (de) 1990-02-08

Family

ID=16480518

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484113029T Expired - Lifetime DE3480960D1 (de) 1983-10-31 1984-10-29 Speichereinrichtung mit registerumtauschfunktion.

Country Status (4)

Country Link
US (1) US4641278A (de)
EP (1) EP0143351B1 (de)
JP (1) JPS6095651A (de)
DE (1) DE3480960D1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61265798A (ja) * 1985-05-20 1986-11-25 Fujitsu Ltd 半導体記憶装置
JPS61288227A (ja) * 1985-06-17 1986-12-18 Toshiba Corp レジスタ選択回路
US4809222A (en) * 1986-06-20 1989-02-28 Den Heuvel Raymond C Van Associative and organic memory circuits and methods
JPS63173134A (ja) * 1987-01-13 1988-07-16 Nec Corp 引数レジスタ装置
DE3801380A1 (de) * 1987-01-20 1988-07-28 Nec Corp Zeichenfolge-erkennungsvorrichtung mit einem speicher, dessen speicherbereiche selektiv zugreifbar sind
JP2852049B2 (ja) * 1987-05-06 1999-01-27 日本電気アイシーマイコンシステム株式会社 シリアル列選択回路
US5081375A (en) * 1989-01-19 1992-01-14 National Semiconductor Corp. Method for operating a multiple page programmable logic device
US5055712A (en) * 1990-04-05 1991-10-08 National Semiconductor Corp. Register file with programmable control, decode and/or data manipulation
JPH0874275A (ja) * 1994-09-07 1996-03-19 Kokubu Kensetsu Kk コンクリート壁及びその施工方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4280177A (en) * 1979-06-29 1981-07-21 International Business Machines Corporation Implicit address structure and method for accessing an associative memory device
DE3174130D1 (en) * 1981-08-19 1986-04-24 Ibm Improved microprocessor
US4592019A (en) * 1983-08-31 1986-05-27 At&T Bell Laboratories Bus oriented LIFO/FIFO memory

Also Published As

Publication number Publication date
US4641278A (en) 1987-02-03
EP0143351B1 (de) 1990-01-03
EP0143351A3 (en) 1987-09-09
JPH057738B2 (de) 1993-01-29
EP0143351A2 (de) 1985-06-05
JPS6095651A (ja) 1985-05-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)