DE3445202A1 - Method and arrangement for analog/digital conversion - Google Patents

Abstract

A method for analog/digital conversion in the microwave range is described. A periodic RF auxiliary signal s(t) with a period duration T is time-modulated with the analog input signal x(t) to be converted. The digital code word zi is identified at time ti through integral division: zi = int((m.x(t))/T), where m = constant. Preferred arrangements to carry out the method operate in the indirect parallel procedure with conversion channels weighted in dual or Gray code. A radio frequency generator supplies the RF signal s(t) in parallel to a time coefficient bank (bo to bN) comprising frequency dividers for N conversion channels and one reference channel. The analog input signal x(t) is applied in parallel to a signal coefficient bank (ao to aN) comprising attenuators for the N conversion channels and the reference channel. The outputs of the time coefficient bank (bo to bN) and the signal coefficient bank (ao to aN) are in each case connected to the two inputs of time modulators (ZMo to ZMN) of a time modulator bank for the N conversion channels and the reference channel. The conversion channels are checked for coherence with the reference channel in N coherence detectors (KD1 to KDN) (Fig. 1). <IMAGE>

Description

Procedure and arrangement for analog / digital conversion

The invention relates to a method according to the preamble of the claim 1 and advantageous arrangements for carrying out the method.

The advent of new, monolithically integrated microwave circuits (MMICs), especially of digital circuits (gigabit logic) in GaAs-FET technology (cf. J. Siegl: Monolithic Integrated Microwave Circuits. Electronics, No. 18, 1984, pp. 80-85), conditionally accordingly for use far in the GHz range fast A / D converter for digitizing the GHz signals.

Especially for digital signal processing in the field of satellite radio, satellite television, space radio, radio relay, radar technology and Such fast A / D converters are required for digital high-frequency receivers. But are the ones that have existed so far A / D converter and known methods in most cases not at all able to meet these requirements of digital signal processing in the GHz range.

Fast A / D converters, both monolithic and discrete / hybrid Construction, are only available today in bipolar and unipolar silicon technology. A separation in terms of resolution (word length) emerges here. and the speed (sampling frequency). The monolithic ADUs, e.g. B. the 8 bit / 100 MHz ADC: CX20i16 (see data sheet for the 8 bit / 100 MHz - A / D converter, Designation: CX20116, Sony (JP), 1984), will iii tloii Iiiicl.rtcri Jihi-cii illl lower resolution range up to 10 bit word length dominate the market. From the Literature (cf. M. Zimmer: A contribution to analog / digital converters for digital High frequency receivers and their technical feasibility. Dissertation at the institute für Elektronik, Ruhr-Universität Bochum, 1983) shows that by using other technologies or principles (GaAs RETs, Josephson junctions, optical modulators, Coding tubes, etc.) implemented very fast converters down to the lower GHz range were or will be.

But all A / D converters currently available for sale have the essentials The disadvantage is that they are much too slow for microwave digitization. The current limits on their sampling or conversion frequencies at a word length N 4 8 bits are between 100 MHz and 200 MHz. The few known from literature faster ADCs are still in the research or development stage and therefore not available for purchase. In addition, these faster ADUs, with the exception of the optical Us e procedures that are still completely in the research stage, a disadvantage caused by the direct implementation process: The speed of implementation is largely due to the frequency multiplication effect limited in the individual active ADC components that result from the quantization semi-periodic, sawtooth-shaped or ramp-shaped transfer characteristics (binary-coded ADUs or

Fold ADUs) follows. Due to the approx. 2N periods of these quantification characteristics the bandwidth BS of a band is a maximum bandwidth BU # 2N.BS with N = ADU word length in bit (1) U for full ADU control. Now today at Si bipolar transistors Transit frequencies of approx. 10 GHz reached. In a rough calculation example according to the above Equation (1) for a known ADC with the word length N = 8 bits and such transistors results for an input signal x (t) that is still fairly error-free from the ADU can be implemented, a bandwidth BS s50 MHz.

In contrast, the sampling frequency of such an ADC may be significantly higher as 2.BS = 100 MHz. But this has no effect on the quantization accuracy Advantage.

To meet the extreme bandwidth requirements of microwave digitization to the individual ADU components of the direct process including the "flash converter" are to be provided, largely to be avoided, must in principle different procedures to be searched for.

The object of the invention is therefore to provide a method and arrangements for analog / digital conversion in To indicate the microwave range realizable with the means available for mass production according to the state of the art are.

The solution to the problem is given in claims 1 and

5 marked. The further claims contain preferred embodiments the invention.

The method according to the invention is not only characterized by sampling frequencies or conversion rates far in the GHz range, but is also in integrated microwave circuit technology (MMICs) as monolithic integrated circuits (single chip systems), preferably in GaAs-FET technology, realizable. Plus, it owns over most conventional processes still have further technical advantages. So it is suitable as a result its high sampling frequencies (> 1 GHz) particularly good for interpolative ADCs, those by signal oversampling and digital filtering after quantization enable dynamic increase in resolution. Also the parallel word output directly in dual code or gray code, which is very simply derived from the structure of the parallel Conversion channels results is for extremely fast digital signal processing very advantageous.

The invention is explained in more detail below with reference to the figures.

FIG. 1 shows in the basic circuit diagram a preferred arrangement according to of the invention FIG. 2 shows a first variant of the preferred embodiment according to the invention arrangement FIG. 3 shows the relationship of selected phase signals in the arrangement according to FIG. 2 to the valences. of the dual code FIG. 4 and 5 serve to explain FIG. 2 FIG. 6 shows a second variant of the preferred according to the invention Arrangement FIG. 7 and 8 serve to explain FIG. 6 FIG. 9 and 10 show one third and fourth variant of the preferred arrangement according to the invention.

First, however, the theoretical basics will be discussed.

In principle, any A / D conversion can be carried out in a mathematical sense integer divisions x z = int q (2) q can be fully described, where x the analog input variable and z form the output word. The abbreviation "int" represents here the rounding or termination operator for the integer representation of the code word z. The divisor q, which is identical to the ADC resolution q = Ao. 2-N (3) is calculated consists of the ADC modulation range Ao = | Axmax} and the ADC word length N in bit.

Instead of this division according to eq. (2), as previously common practice, with the help of non-linear transfer characteristics of the corresponding ADC components (comparators, analog switches, folding amplifiers, etc.), according to the invention the conversion divisions are made using the periodicities (parameter divisions) of periodic HF auxiliary signals with n = 0,1,2, ... Ni (4). For this purpose, the period T and the number of periods of the signal s (t) with respect to a defined starting time t with the period number n0 = 0 are to be set. For simple technical application, the auxiliary functions g (t) should also be continuous and monotonic within the period T or the frequency f = 1 / T, except at the point of their 0 peak values. Therefore, sinusoidal, rectangular and ramp-shaped periodic functions g (t) for s (t) are particularly recommended.

In order to determine the ADC code word z, Eq. (2) by the equation for determining the number of periods - executed at the defined times ti - replaced. In order to now set the number of periods n. In a linear relationship to the instantaneous values x of the analog input signal x (t), G1. (5) into the whole number division m = constant (6) converted to A / D conversion of x (t). Here the time variable t is G1. (5) to be replaced by the product mwx. Technically, this is done by time modulating the auxiliary signal s (t), Eq. (4), with the input signal x (t). The A / D conversion can thus be described with the equation zi int (Qmx (t)) (7) and the modulation process Q}} x (t). The quotient Q = m / T represents the constant modulation coefficient.

For the technical implementation of the method for determining the code word zK from the number nK of synchronous periods T according to Eqs. (5), (6) and (7) is especially the parallel process according to FIG. 1 with K. = 1,2, ... N parallel conversion channels that reflect the cyclic nature of certain codes, e.g. B. the dual code exploits. The Gray code is equally suitable. For the sake of clarity, however, the considerations are only given here for the dual code. If an independent conversion channel K is formed for each dual bit position DK in a parallel circuit and the respective modulation coefficient is weighted according to the significance of the dual code in the conversion channel K: = m 2K-N (9), the counting of the synchronous periods T is simplified for the coherence detection of the instantaneous signal phase pattern in the conversion channels K at the defined interrogation times ti (synchronous phase pattern detection). If the dual code structure, G1. (8), symmetrical half-waves of the auxiliary signals s (t) or sK (t) according to Eq. (4) is used, the coherence detectors in this preferred arrangement according to the invention only have the task of performing the modulations according to Eqs. (6) and (7) on even or odd numbers int (2Qx) = 4o even i ZK = O (10) int (2QK x) = qEuneven $ ZK = 1 (11) each time to check tle n synchronization query time reference t. The conversion channels weighted in the dual code or in the Gray code thus deliver the bits zK directly at the output of the coherence detectors, which then form the digital word z in the dual code d or in the Gray code g via the output register, see FIG. 1.

The representation of the modulation coefficients of Eq. (7) or QC of G1. (9). The conversion equation (6) can be extended with regard to the modulation behavior to by inserting signal attenuation coefficients aK in the quotient counter and frequency divider coefficients bK in the quotient separator.

If the other set of coefficients is set equal to 1, the following equations result from equations (3), (9) to (11) for the auxiliary coefficients aK and b K: The modulation coefficients can therefore be represented in two different ways (aK = 1 or bK = 1). This requires two main variants for the technical implementation of the preferred arrangement according to the invention: the phase-staggered ADC and the frequency-staggered ADC. This fact is explained in more detail in the following technical exemplary embodiments.

Preferred embodiments of the invention, which according to Eqs. (10) to (15) on an indirect parallel method with periodic HF auxiliary signals 5K (t) and in the dual code d or in the Gray code g weighted and independent conversion channels K are shown in FIG. 1 summarized in a block diagram.

A high-frequency generator supplies its auxiliary signal s (t) or t (t) parallel to a time coefficient bank with frequency divider coefficients bK, K = 0,1,2, ... N.

The analog input signal x (t) is also sent in parallel to a signal coefficient bank, consisting of individual damping coefficients aK. These coefficients aK and bK represent the auxiliary coefficients, Eqs. (13) and (14), for the time modulation of the individual signals sK (t) or

VK (t) with the signals xK (t) in the respective conversion channels K Here, the coefficients aK, bK indicate by their values that according to the valences the dual code or the gray code with respect to the respective conversion channel K the correct, bit-weighted modulation of the modulators ZMK a time modulator bank. With the time modulators ZMK are now proportional the time parameters t or the phase parameters f of the auxiliary signals for the instantaneous level of xK (t) flK (t) changes (modulates) and thus results in the time-modulated signals fK (x, t). All that remains for the parallel bit pattern extraction for the K digital word z is that synchronous instantaneous time or instantaneous phase patterns of the ones supplied by the modulators ZMK Signals fK (x, t), according to Eq. (12) on the conversion channels K to be detected. This essentially takes place on a bank of coherence detectors KDK.

For time or phase comparison, these detectors KDK receive a from HF generator reference signal derived from the coefficients b and 0 modulator ZM fo (x, t). For 0 time buffering and clock-synchronized output of the bits ZK resp. D K at the system output in dual code d or in Gray code g is the coherence detectors Another output register, which is preferably made up of master-slave or edge-triggered D flip-flops FFK is connected downstream. As a clock signal (t) for the registers FFK the reference signal fo (x, t) delayed by a delay C is used.

On the basis of four typical implementation examples, each on a 4 bit A / D conversion and based on coding only in dual code are the most important ADU variants that are of particular importance for the technical implementation, subsequently explained in more detail.

1st embodiment: Phased ADC With this variant, shown in FIG. 2, which is supplied by the HF generator as an auxiliary signal s (t) sinusoidal continuous signal 9 (t) with the frequency f (t) = f = const.

0 is used, A / D conversion frequencies f = f are far in the u 0 GHz range accessible. There are certain, selected instantaneous phases #K (x, ti) for the individual Dual code digits DK of the conversion channels K related in such a way that they are from the coherence detectors KDK are recognized as a bit pattern in the dual code.

The four different phase signals ÇK (X, t) are generated here according to FIG. 2 on four identical phase or frequency modulators PM1 bis PM4, the sinusoidal continuous signal f (t) separated by the channel signals xK (t) for each conversion channel K is modulated in phase or frequency and thus result in the phase signals WK (x, t) on the channels. Here are the channel signals xK (t) derived from the input signal x (t) by dividing x (t) for xK (t) by the damping coefficient. al to a 4 according to the value of the conversion channel K in each case in level is decreased. As a result, there is a preamplifier for the input signal to provide a gain factor V = 8 (2). The coefficients bK are all chosen one.

In FIG. 3A) shows which amplitude values the instantaneous phases PK in the four conversion channels of FIG. Assume 2 at the sampling times t, depending on the value of the analog input signal x (ti). A is the off-0 control area of the ADU, see Eq. (3), S is the maximum 0 amplitude of the RF auxiliary signal.

FIG. 3B) shows the relationship to the dual code D. The figure is as follows to read: if the instantaneous amplitudes in FIG. 3A) are in the hatched area, take the in FIG. 3B) hatched bit positions to be found vertically underneath the value "1".

The necessary modulation characteristics of the phase or. Frequency modulators PM1 to PM4 are shown in FIG. 4 shown for the phased 4 bit ADC. In order to With this variant, the four modulators of the same type have dual-level control ranges assigned. Consequently, the maximum phase deviation of the modulators in the channel applies 1 fl, f1 = 2t, in channel 2 to 2 = 4n, in channel 3 93 = 8t and in channel 4 Af4 = 16t. The control ratio of 1: 2: 4: 8 in the four conversion channels is created in a simple way Way by the level weightings with the damping coefficients a1 to a4 according to FIG. 2. If coding in Gray code is used instead of coding in dual code, then halving the above maximum phase excursions of the modulators, but also different ones Introduce initial phase positions for the phase signals fK (x, t).

In general, the phase, Frequency, clock phase and delay modulators (see below) with controllable Impedance elements, controllable active filter networks or by Circuits the impulse technology can be realized. So come, especially for sampling frequencies in the GHz range, as controllable capacitive impedance elements, capacitance diodes, as controllable inductive impedance elements YIG filters or special high-frequency lines with controllable ferrite or piezoelectric components in question.

The coherence detectors KDK, the summation signals v (x), cf. FIG. 2, query phase coherence using comparators KK or threshold value elements, can be implemented in the simplest case by appropriately biased semiconductor diodes will. The reference phase signal #o (t) required for the coherence detectors becomes here by a phase shifter PG6 with constant phase shift from the HF generator signal f (t) is generated. The phase shift elements used are generally passive or active electrical ones Networks or RF lines in question.

FIG. 5 explains the process of coherence detection in the arrangement according to FIG. 2. The reference phase signal fo (t), it is drawn in a solid line, has the maximum amplitude So. The threshold value q at the 0 comparators is at this value KK according to FIG. 2 established. The phase signals fK (x, t) also have maximum amplitude SO, but are opposite to the time modulators according to the weighted modulation shifted in phase with the reference phase signal. In FIG. 5 are in interrupted Lines showing several summation signals YK = #o + <PK, namely for um, 900, 0 °, 900, 1800 phase-shifted signals The summation signal YK is present at the time of the query (with the clock i (T)) either below or above the threshold q, and lies accordingly the bit value ZK at "0" or "1" at the output of the coherence detectors.

The output of the digital comparator signals zK at the system output are summarized as a digital word z in the dual code d, takes place in all of the described Master-slave or edge triggered D flip-flops versions of the invention OFF. Via a second phase shifter PG5 and a sine / square converter SRU, these flip-flops FFK are supplied with the clock i (T), which is derived from the reference phase signal fo (t) is derived.

2nd embodiment: frequency-graded ADC A second embodiment the arrangement according to the invention is shown in FIG. 6 shown. In contrast to the phased ADC are not used here for bit pattern detection, the phase signals fK (x, t) on the conversion channels * K, but frequency phase signals (t) that have dual K graded frequency ratios for the HF generator frequency f (t) = f. But otherwise is the implementation process 0 with the help of a sinusoidal continuous signal + (t) of constant frequency f equal with the described implementation process of the phased ADC. So that applies FIG. 3 also for this ADU variant.

There are some important differences to the technical implementation. The four signal attenuators with the coefficients a1 to a4 are omitted, instead are four different dual graded frequency dividers with the coefficients b to b4 (frequency ratios: 1: 1, 1: 2, 1: 4, 1: 8) for the frequency phase signals 9K (t) to be inserted into the channels. The time modulator bank is also the same as in the first exemplary embodiment from four identical phase resp.

Frequency modulators consisted of four identical phase rotators PG1 to PG4 of constant phase rotation angle to replace. as well the phasing element PG6 of the phased ADC against a single phase or frequency modulator PM can be exchanged. The other components remain in the System same with the first version.

With little effort from just a single time modulator PM and This variant has an amplifier (V = 1) that is not necessary for the input signal x (t) however, the restriction that only one sampling or conversion frequency = = b1 fO, in the case of a 4-bit conversion fu = 1/8 f0, is achievable. Here the determines MSB conversion channel with the lowest frequency in the system the highest possible sampling frequency. However, when choosing a suitably high frequency f of the HF generator and at ADC word lengths 0 N 4 6 bit, sampling frequencies fA i 1 GHz are possible for this version.

3rd embodiment example: staggered runtime pulse ADC A third Embodiment of the arrangement according to the invention is shown in FIG. 9 shown. Will with the versions of the phase-staggered ADC or the frequency-staggered ADC periodic, square-wave auxiliary signals g (t) instead of the sinusoidal continuous signals + (t) are used, these are "pulse ADCs" with the means of pulse technology and the to implement new integrated microwave circuit technology in a particularly cost-effective manner. In the case of the delayed 4-bit pulse ADU according to FIG. 9 are therefore periodic, Square-wave pulse signals T (t) with a ratio of the pulse duration to the interpulse period applied at a rate of 1: 1.

These pulse trains' C (t) are derived from the sinusoidal signals g (t) of the HF generator is generated by means of a sine / square-wave converter SRU. The bits for the digital word z in the dual code are derived from the correspondingly generated clock phase pattern of the clock phase signals (x, t) obtained on the four conversion channels. This is what happens the formation of the four clock phase signals CK (x, t) by four delay K modulators LZMK, which make the clock signal t (t) proportional to the levels of the controlling channel signals xK (t) change with regard to their signal transit times through the modulators LZMK. For the signal attenuation coefficients a1 to a4 and for the modulation of the transit time modulators LZMK, the same applies as for the phased ADC based on FIG. 2 and 4 has been described. FIG. 7 shows selected instantaneous clock phases, analogous to FIG. 3.

However, the coherence detection of the individual clock phase signals is simplified here ZK (x, t) considerable. The digital coherence detectors U1 to U4 are only simple logical AND links for the pulse signals r (x, t) and the reference pulse train T (t) to be carried out. FIG. 8 0 shows, analogously to FIG. 5, examples of against the reference pulse train clock phase signals shifted by -T / 4 or + T / 4.

For the digital output z of the detection results zK is again the register listed above with the flip-flops FF K is proposed. Here the phase shift elements Po5,6 are to be replaced by delay elements LG5 / 6.

4th embodiment: Frequency-graded pulse ADC This ADU variant with rectangular pulse trains t (t), as an auxiliary signal s (t) for the A / D conversion, provides the technical analogy to the procedure of the frequency-staggered ADCs. Thus, the same procedures apply, only with the difference that that they are based on rectangular pulse trains with the pulse duration / pulse pause ratio of 1: 1 are to be applied.

The embodiment is shown in FIG. 10 shown. Compared to the ADC version of the phased pulse ADC according to FIG. 9 the damping coefficients are omitted here al to a 4 for the channel signals xl (t) to x4 (t). Therefor are new in the four lines of the clock phase signals tK (t) the frequency divider with the dual graded coefficients insert bl to b4. In addition, the four delay modulators LZM1 to LZM4 are through four constant delay elements LG1 to LG4 and the delay element LG6 of the phased one Replace pulse ADUs with a single transit time modulator LZM.

For the technical implementation of the individual ADC components, RF signal generator, Sine / square converter SRU, clock frequency divider (coefficients bK), timing elements LGK, transit time modulator LZM, digital coherence detectors with AND gates U1 to U4 and the output register, the same conditions and principles apply as in the described phase-staggered pulse ADC of the 3rd embodiment. So this ADU variant is also subject to the same restriction with regard to the highest possible Sampling frequency A = b1 fO, f, as for the variant of the frequency graded ADUs according to the 2nd embodiment applies. The highest possible sampling or conversion frequency is here by the lowest channel signal pulse repetition frequency of the MSB conversion channel (Frequen, dividing coefficient bl) determined. Possible applications for signal oversampling These ADC versions are particularly advantageous in interpolative ADU systems for dynamically increasing the ADU resolutions and conversion accuracy to be used, provided that the signal oversampling is correspondingly high with an oversampling factor K by an ADC with a smaller word length of N. bit and a subsequent digital filtering and sampling rate reduction by the factor K, this results in an enlarged ADC word length of Nb bit> Na bit with respect to of the inner ADU to win. A more detailed description of this procedure is given can be found in DE-OS 32 12 103.

Claims (13)

A method for analog / digital conversion, characterized by the following features: a periodic RF auxiliary signal s (t) with a period T is time-modulated with the analog input signal x (t) to be converted; - The determination of the digital code word z. at time t. is done by whole number division: with m = constant. 2. The method according to claim 1, characterized in that the RF auxiliary signal s (t) is sinusoidal, rectangular or ramp-shaped. 3. The method according to claim 1, characterized in that the implementation in independent parallel implementation channels, which correspond to the priority of the code used are weighted. 4. The method according to claim 3, characterized by the use the dual code or the gray code. 5. Arrangement for performing the method according to claims 1 to 4, characterized by the following features: -, i II t> t '. 1 1. t Ltt ', II?, g . 1 t Lt> [i 1 't'. L tI <. III "- ii L 1 1 g II it 1 s (t) parallel to a Time coefficient bank (b to bN) from frequency dividers for N conversion channels and a reference channel; - the analog input signal x (t) is parallel to a signal coefficient bank (a to aN) of attenuators for the N conversion channels and the reference channel placed; - the outputs of the time coefficient bank (bo to bN) and the signal coefficient bank (aO to aN) are each connected to the two inputs of time modulators (ZMo to ZMN) a time modulator bank for the N conversion channels and the reference channel connected; - the outputs of the time modulators (ZM1 to ZMN) of the N conversion channels sin.d each connected to a first input of N coherence detectors (KD1 to KDN); - the The output of the time modulator (ZMo) of the reference channel is parallel to the second inputs connected to the N coherence detectors (KD to KDN); - to the outputs of the N coherence detectors (KD to KDN) an output register is connected, its output with a clock signal ((T)) is clocked, which is derived from the reference channel; (FIG. 1). 6. Arrangement according to claim 5, characterized in that the output register consists of master-slave or edge-triggered D flip-flops (FFl to FFN). 7. Arrangement according to claim 5, characterized in that the RF auxiliary signal s (t) is a sinusoidal continuous signal (# (t)). 8. Allordllulog leach Allsprchell 5 and 7, characterized by the following Features: - the time coefficients (bo to bK) of the time coefficient bank all elected equal to one; - the analog input signal x (t) is initially about a preamplifier with a gain of 2N-1; - the attenuators (a1 to a4) of the signal coefficient bank set the amplified in the preamplifier Input signal x (t) according to the value of the respective conversion channel down in level; - The time modulator bank consists of identical phase or Frequency modulators (PM1 to PM4) for the N conversion channels and a phase shift element (PG6) with constant phase shift for the reference channel; (FIG. 2). 9. Arrangement according to claims 5 and 7, characterized by the following Features: - the signal coefficient bank is omitted; the analog input signal x (t) is only fed to the reference channel; - the frequency dividers (b1 to b4) of the time coefficient bank set the frequency of the RF auxiliary signal (t (t)) in the N conversion channels accordingly their value, and in the reference channel according to the value of the MSB conversion channel down; - The time modulator bank consists of identical phase rotation elements (PG1 to PG4) of constant phase rotation angle for the conversion channels and one Phase or frequency modulator (PM) for the reference channel; (FIG. 6). 10. An arrangement according to claims 8 or 9, characterized in that the coherence detectors each consist of an adder (#) and a downstream one Comparator (up to K4) exist (FIGS. 2 and 6). 11. Arrangement according to claims 5 and 7, gekennzeichl1et by the following Features: - the HF auxiliary signal (# (t)) is converted into a sine / square-wave converter (SRU) converted into square-wave signals (t (t)); - the time coefficients. the time coefficient bank are all chosen equal to one; - the analog input signal x (t) is initially passed through a preamplifier with a gain factor of 2N-1; - the attenuators (a1 to a4) of the signal coefficient bank set the amplified in the preamplifier Input signal x (t) according to the value of the respective conversion channel down in level; - The time modulator bank consists of identical runtime modulators (LZM1 to LZM4) for the N conversion channels and a delay element (LG6) with constant Runtime for the reference channel; (FIG. 9). 12. Arrangement according to claims 5 and 7, characterized by the following Characteristics: - The HF auxiliary signal (p (t)) is converted into a sine / square-wave converter (SRU) converted into square-wave signals (t (t)); - the signal coefficient bank not applicable; the an.aloge input signal x (t) is only fed to the reference channel; - the frequency dividers (b to b4) of the time coefficient bank set the frequency of the RF auxiliary signal (t (t)) in the N conversion channels according to their valency, and down in the reference channel according to the weight of the MSB conversion channel; - the time modulator bank consists of identical delay elements (LG1 to LG4) of constant runtime for the conversion channels and a runtime modulator (LZM) for the reference channel; (FIG. 10). 13. Arrangement according to claims 11 or 12, characterized in that that the coherence detectors (U to U4) each consist of a simple logical AND operation exist for two input variables each (FIGS. 9 and 10).