DE3444736A1 - VIDEO PLAYER - Google Patents

Description

3 1, k 4 7 3 6

Video game device

The present invention relates to a video game machine, particularly a video game machine for commercial use with the can be played against payment, d. H. by inserting a means of payment such as a coin an inlet slot.

For practical use, the so-called TV game machines or video game machines are generally known in which the Game associated characters are shown on a screen of a display unit, such as a color picture tube and for the game, for example, by means of joysticks or control switches known as "joy sticks" being controlled. The conventional video game machines can be roughly classified into two categories; H. such for use in the home and those for commercial use. Previously, video game machines were disregarded the above Categories available in different types with one video display screen used by two people who alternately play became a display screen shared by two people to play at the same time or a plurality of video display screens is used by one person for solo play. However, no proposal has been made heretofore for a video game machine in which a plurality of video display screens have been made. used by a plurality of people to play the same type of game at the same time. In particular, so far has been no such video game machine is known in which the same game is displayed on a plurality of display screens is to display the characters assigned to the game not only on the display screen of the respective game but also on the Display screen of the other by means of an individual control arrangement by each of the plurality of players

steer.

The easiest way to provide such a video game machine is to simply assemble or combine conventional video game machines. That way would However, lead to a video mirror that inevitably more than is twice as expensive as a conventional arrangement.

The present invention 1 is therefore based on the object of specifying a novel gaming device with which a plurality people can play the same game displayed on a plurality of screens of a plurality of display units will. The new video game device should have a compact shape and be producible at a low price be.

According to the invention, the object is given in the video game machine by those specified in the characterizing part of claim T. Features solved.

The video game machine according to the invention includes a plurality of display units and one arranged in a housing A plurality of groups of control buttons, etc. for the respective display units, a plurality of computer systems according to the operation of the assigned groups of control buttons, etc., game data corresponding to Supply display units and furthermore the data from one of the computer systems via a transmission circuit direct or indirect transmission between the respective computer systems to the one assigned to the other »computer system Display unit can be transmitted so that the game data displayed on each display unit not only through the assigned group of control buttons etc., but rather can also be controlled by the other group of control buttons.

Since according to the invention a transmission arrangement for data transmission between a plurality of groups of tax

Orders, d. H. Computer systems, it is intended for a plurality of players are possible to enjoy the same game displayed on a plurality of display units each player with his own group of control orders has the option of including those in the game to control assigned characters on the display unit of the other. Since in the device according to the invention, the transmission arrangement for a plurality of groups of control arrangements is shared, it is much more compact and cheaper than a conventional arrangement made thereby becomes that simply a plurality of video game machines are connected to each other.

Embodiments of the video game device according to the invention are explained in more detail below with reference to drawings.

Show it:

Pig. 1 is an overall perspective view

a preferred embodiment of the invention,

Fig. 2 is a block diagram of an embodiment

example of the electrical circuit of the embodiment shown in FIG ,

Figs. 3A and 3B are flow charts used for explanatory purposes

serve to handle or operate the embodiment,

4 to 6 representations, the corresponding An

show in memory show.

Fig. 1 is a general perspective view showing an embodiment of the invention. The video game machine This embodiment includes a housing 1 with feet for installation. This case contains a table / the is essentially T-shaped in its side view and a housing arranged thereon, which in its side view is trapezoidal and on the opposite sloping sides of the housing, which is trapezoidal in section, are two display units, i. H. Cathode ray tubes 2 and 3 arranged with their backs to one another. In addition to the cathode ray tubes in this embodiment, for example, known liquid crystal display units, Plasma display units, electroluminescent displays, etc. can be used. On the sloping sides of the The housing, which is trapezoidal in section, is also provided with slots 4 and 5 for coins. These slots 4 and for the coins are insertion openings for coins as a means of payment for the price of playing a game, since the Video game machine of the present embodiment is intended for commercial use. As a means of payment In addition to the coins mentioned above, cards such as magnetic cards or optical cards can also be used.

On the opposite sides of the table-shaped part of the housing 1 are various operating arrangements, switches etc. necessary to play the games.

On one side two groups of operating arrangements are provided, which two joysticks 6 and 12, which also under the name "joy sticks" are known and four control buttons 8, 10, 14 and 16 and also four mode switches 18, 20, 22 and 24, also referred to as mode switches. On the other hand are similarly two types of operating instructions are provided, the two control sticks 7 and 13, four operating buttons 9, 11, 15 and 17 and also four mode switches 19, 21, 23 and 25 include. With this video

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game device, up to four people can play the game using the four groups of operating arrangements. As is well known, the control sticks 6, 12, 7 and 13 are used to move the game characters on the screens the cathode ray tubes 2 and 3 both in the vertical and in the lateral direction, while the control buttons 8, 10, 14, 16, 9, 11, 15 and 17 are provided that the game characters perform certain types of movements, such as jumping, shooting, or pushing. With the video game machine one of four different operating modes, also known as modes, can be selected to to play a specific game. The mode switch 18, 22 and 19, 23 are used to select the first mode and mode switches 20, 24 and 21, 25 are used to select the second mode. For example, when the video game machine is used to play a tennis game, can the first game type switch 18 and the second game ■ mode switch 20 can be used to select the "single" mode, while the first mode switch 22 and the second mode switches 24 can be used to select the "double" mode. Similarly, the first mode switch 19 and the second mode switch 21 are used to select the "single" mode, while the first mode switch 23 and the second mode switch 25 can be used to select the "double" mode. The first mode switches 18, 22, 19 and 23 are used to set the first Select the mode of this video game device, d. H. the mode in which the players on each side take part in independent Enjoy playing while the second mode switches 20, 24, 21 and 25 are used to set the second mode of operation select in which the. Players on opposite sides intend to play the same game. This means, that in the first mode each player plays the game with the corresponding computer system built into the housing 1 plays as an opponent, while in the second mode he plays the game with the player on the opposite side.

The types of games that can be played include other simulated ball games besides the tennis game mentioned above, Card games, mah-jong and the like.

Fig. 2 is a block diagram showing an embodiment of the present invention. The left side of Fig. 2 shows one computer system 26 and the right side shows the other Computer system 27. Computer system 26 is for cathode ray tube 2 on the left in FIG Computer system 27 for the cathode ray tube 3 at the right side of Fig. 1 is provided. The computer system 26 includes a central processing unit 28, which also is referred to as CPU (central processing unit), with which the corresponding mode switches 18, 20, 22 and 24 are connected. The CPU 28 is also provided with a coin selection arrangement 30 connected to identify the type and value of those introduced through the coin slot 4 Serving coin. This coin selector assembly 30 can be replaced by a card reader or the like if that The means of payment used is a card. Furthermore, the operating arrangements 6 to 16 are connected to the CPU 28, the however, are omitted in FIG.

As far as the CPU 28 is concerned, a CPU in MOS technology, which is designated as 6502, is used, for example. The CPU 28 is equipped with a read-only memory 36, which is also called ROM (read only memory) is referred to, a read-write memory 38, which is also referred to as RAM (random access memory) and an image processing unit 40, which is also referred to as a PPU (picture processing unit), via a 16-bit address bus 32 and an 8-bit data bus 34 tied together. The ROM 36 stores an operation program and a game program for the CPU 28 and, for example, the read only memory Intel 2765 can be used. The Hitachi 6116 read / write memory, for example, can be used as RAM 38 and it is used to store the necessary data for the course of the game. The PPU 40 is used

for the processing or control of the cathode ray tube in accordance with the data output from the CPU 28 and for example a PPU Nintendo 2CO3 is used. Further, with the PPU 40, there are a character ROM 42 and a video RAM 44 connected. The circuit 6116 from Hitachi, for example, can be used for both. The character ROM is used to represent the characters required for a game, such as a ball or player in the case of a Ball game or cards, etc. in the case of a card game, while the video RAM 44 for the fixed display of the background of the game, for example a playing field, net or goal in the case of a ball game.

The CPU 28 is also connected to a tone generator 46 which emits effective sounds as necessary.

The other computer system 27 similarly includes one CPU 29, and this CPU 29 is arranged in the same way as the corresponding memories 37, 39, 41, 43 and 45, as in the case of the computer system 26, so that a detailed description thereof is omitted in order to avoid redundancy became. The CPU 29 is also provided with the mode switches 19, 21, 23 and 25 and additionally with those in FIG. 1 shown operating arrangements 7 and 17 connected for the game, although these have been omitted in FIG. One Coin selection device 31 and a tone generator 47 connected to the CPU 29 are similar to that mentioned above Coin selection assembly 30 and tone generator 46 are identical.

In this embodiment there is a shared read-write memory 101, which is also referred to as C-RAM (common random access memory), provided to a transmission arrangement to build. This C-RAM 101 can be designed as a static RAM and, for example, as a C-MOS RAM 6116 from Hitachi whose capacity is for example 2KB. This C-RAM 101 is provided with address bus lines 103 from an address selection circuit 102 and data bus lines 106 from a single

called tri-state buffers 104 and 107, which have a gate circuit form, connected. The address selection circuit 102 is, for example, the 74LS157 circuit of the company Texas Instruments uses which is a TTL circuit. This address selection circuit is used to select the Address bus lines 103 to be connected to either address bus lines 32 or 33. The tri-state buffer 104 is between the data bus lines 34 and 106 arranged during the tristate Buffer 107 arranged between the data bus lines 35 and 106 is. Such tri-state buffers 104 and 107 can be, for example, the circuit 74LS245 of the company Texas Instruments are used, the three states "1", "0" and "high" according to the signals present Impedance ". With the selection circuit 102 and the tri-state buffers 104 and 107, a signal line 108 is from the Output terminal of the CPU included in the computer system 26 connected. That is, this signal line is connected to a connection point IRQ of the CPU 29 provided in the other computer system and also to a The control terminal of the address selection circuit 102 is connected and it is also connected to the tri-state buffer 107 and from this via an inverter 105 to the other tri-state buffer 104. A signal line 109 is between the output connection of the CPU 29 and a connection point IRQ of the CPU tied together. Thus, the C-RAM 101, etc. composing the communication arrangement are substantially via the Signal line 108 from the output terminal of the CPU 28 provided in the computer system 26 is controlled. This means, that when using the communication arrangement 101 to 109 in the case of a competition situation of the CPU 28 in the Priority is given compared to CPU 27.

Needless to say, the use of the built-in Circuits in this circuit is not limited to the above-mentioned integrated circuits and similar or even different integrated circuits can be used and it is also possible still

12th
to use more discrete building blocks.

Although those with the designations PPU 40 and 41 Image processing units for display on cathode ray tubes 2 and 3 with RGB connections are provided, can also be used to control the cathode ray tubes other methods such as the NTSC color television system can be used.

With reference to the embodiment shown in FIG the following describes the mode of operation for the case that a data transfer between the one computer system 26 and the other computer system 27 using the communication arrangement 101.

In the initial state, the signal lines 108 and 109 at the output connections of the CPUs 28 and 29 both have the binary value ¹¹ O ". Since the tri-state buffers 1n4 and 107 both have the low voltage value, the tri-state buffer 107 is enabled at this point in time and this interconnects the data bus lines 35 and 106. In the meantime, the buffer 104 is then in the "high impedance" state since, inverted by the inverter 105, the binary value "1" is fed to the tri-state buffer 104 and the The connection between the data bus lines 3, 4 and 1o5 is disconnected At the same time, the binary value "0" is also supplied to the address selection circuit 102, so that this selection circuit 102 connects the address bus lines 33 to the address bus lines 103. Thus, the computer system 27 can access the C-RAM 101. In this state, it becomes possible for the computer system 27 to write and read data in the C-RAM 101. To prevent When the other computer system 26 can use the C-RAM 10 while it is being used by the computer system 27, it is ensured that the CPU 29 outputs the binary value "1" to the signal line 109. Thus, the connection point IRQ (interrupt request terminal), the CPU 28, which is assigned to an interrupt request, receives the binary value "1" and

the CPU 28 thus recognizes that the C-RAM 1O1 at the moment cannot be used. In the meantime, the signal line 108 from the CPU 28 then has the binary value "O" and a binary value "O" is fed to the connection point IRQ of the CPU 29 and the CPU 29 is now able to go to the C-RAM via the address bus lines 33 and 103 and the data bus lines 35 and 106. When the CPU 29 stops using of the C-RAM 101 has ended, the CPU 29 outputs the binary value "O" at its output terminal, and then the other Computer system 26 to access the C-RAM 1O1.

When the signal line 109 from the output terminal of the CPU 29 assumes the binary value "O", the CPU 28 confirms the binary value "0" / which is fed to the terminal IRQ and outputs on its Output connection from the binary value "1". Thus, the binary value "1" is then supplied to the connection point IRQ of the CPU 29 and the CPU 29 then recognizes that the C-RAM 101 is currently inaccessible.

When the signal line 108 from the output terminal of the CPU 28 assumes the binary value "1", the address selection circuit 102 connects the address bus lines 32 to the address bus lines 103. Simultaneously, inverted by the inverter 105 , the binary value "O" is fed to the tri-state buffer 104, so that the data bus lines 34 and 106 can be connected to one another through the tri-state buffer 104. In

in the meantime, the binary value "1" has been supplied to the other tri-state buffer 107. This buffer 107 thus takes the status "high impedance" and the connection between the data bus lines 35 and 106 are separated from one another. In this way, the CPU 28 is then enabled through the address bus lines 32 and 103 and the data bus lines 34 and 106 write data into or read data from the C-RAM 101.

If the computer systems 26 and 27 try to access the C-RAM 101 at the same time, the CPU 28 checks the status its connection point IRQ. Since the two CPUs 28 and 29 then

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are not connected to the C-RAM 101, the port IRQ of the CPU 28 has the binary value "0". Thus, the CPU 28 outputs the binary value "1" at its output ^{terminal and the binary value "i! 1} is applied to the terminal IRQ of the CPU 29 via the signal line 108. The CPU 29 then recognizes that the C-RAM 101 therein Thus, the computer system 26 is given priority when it (CPU 28) competes with the computer system 27 (CPU 29).

The access to the C-RAM 101 is carried out as described above and when, for example, data is written into the C-RAM 101 from the CPU 28 at a predetermined address and at the same address in the C-RAM 1o1 are read out by the CPU 29, it means performing data transfer from the CPU 28 to the CPU The data transfer from the CPU 29 to the CPU 28 can also be carried out in the same way by using a predetermined Address in the C-RAM 101 can be performed.

In the embodiment described above, data transmission between the two computer systems 26 and 27 through the medium of the C-RAM 101 indirectly. It however, there are a multitude of other ways of communication.

For example, if CPUs 28 and 29 both have relatively high processing speeds, then one is direct data transmission through connecting lines, not shown, can be carried out in that the outputs of the CPUs without the medium of a shared memory arrangement such as the C-RAM 1o1 can be directly connected to one another.

It is also possible to use an arrangement for direct memory access, also known as DMA (direct memory access) is known. When the CPU 29 requests data from the CPU 28, the contents of the RAM 38 can directly are read into the RAM 39 and in the opposite

3U4736

In this case it is possible by causing the CPU 28 to duplicate the contents of the RAM 39 in the RAM 38.

Furthermore, additional RAMs, not shown, can also be used as the communication arrangement, which are connected to the CPUs 28 and 29 are connected. These can be arranged so that the CPUs 28 and 29 write data into the RAMs 38 and 39, respectively and at the same time write the same data into the additional RAMs on the opposite side are connected in such a way that the CPU on the other hand receives the data as far as necessary from the connected to it RAMs can read.

Thus, since a number of other possibilities can be used for the communication arrangement, the best chosen, taking into account cost, ease of construction, and other factors.

Referring now to the flow charts in FIGS. 3A and 3B, and also FIGS. 4 through 6, the operation will now be described the embodiment shown in FIGS. 1 and 2 described. In the following explanation, the computer system 26 or the CPU 28 is referred to as "own" and the computer system 27 or the CPU 29 is referred to as "opposing".

In the first step 201, the CPU 28 decides by that of of the coin selection arrangement 30, whether the own credit (C1) is greater than half of the credit amount (Q) (= 0/2) or not. When the own credit (C1) is less than (Q / 2), the CPU 28 sets the second mode indicator FL 12 of RAM 38 in FIG. 4 to the binary value "0" in the next step 203, so that the player can recognize that the second Mode is not feasible. If "yes" in step 201, the CPU 28 decides in the next Step 205, whether the sum of your own credit (C1) and the credit (C2) of the opponent is greater than that for playing the second mode required credit amount (Q) or not.

If the decision in step 205 is "no", the second mode display FL1 2 is set to the binary value "0" in step 203 set. If it is "yes", the second mode indicator FL12 is set to the binary value "1". Thus it becomes a decision whether the paid coin or means of payment has the required amount of credit for the Playing the second game mode is required or not and, if not, the selection of the second mode is disabled.

After setting or resetting the second mode indicator FL 12 in step 203 or 207, the CPU 28 decides in the next step 2o9 whether its own credit (C1) is greater is than the credit amount (P) required to play the first mode or not. If the decision is in that Step 209 reads "no", the binary value "0" is entered in the first mode display FL 11 of the RAM 38 (FIG. 4) in the next step 211 and when it is "yes", the binary value "1" is written in the first mode display FL11. then the CPU 28 checks whether the first mode switch 18 (or 22) is pressed or not and if the decision is "no" is, it proceeds to step 219 without an operator query, while in the case of "yes" it goes to step 219 only in that The case where the first mode indicator FL11 has not been set to the binary value "1" in the step 217 proceeds. In step 219, a check is made by the CPU 28 to see if the second mode switch 20 (or 24) has been made or not.

When the first mode indicator FL11 should be set in the foregoing step 217, the CPU 28 executes processing necessary to play the first game mode. That is, in the next step 221, it subtracts the amount of credit required to play the first game mode (P) from the player's own credit (C1) and saves the result as the player's new credit (C1). Then it accesses a predetermined one in the manner shown above Address in the C-RAM 101 too and the binary value "1" is written in the first mode display FL 111, as is

is shown in Fig. 6 accordingly. In this way, it is possible to notify the CPU that the CPU 28 is in the first mode works. The CPU 28 then executes the first game mode in step 225. Implementation of the game may also be generally known, and therefore a detailed description thereof is also omitted here, since this is from is of no particular importance with regard to the present invention. As already described above, in the group of the joystick and the control switches 8 and 10 in Fig. 1 and / or the first mode of the game Group of joystick 12 and control switches 14 and 16 are used so that the player can play with the computer system 26 as his opponent.

When the first game mode 225 is over, the CPU 28 writes the binary value "0" in the first mode display FL 111 of the C-RAMs 101.

When the CPU 28 has recognized that the second mode switch 20 (or 24) not yet actuated in step (219) was carried out, the next step is step 229 and there the CPU 28 decides whether the first Mode display FL 121 of the C-RAM 101 has the binary value "1" or not. This means that it is decided whether the opponent game mode is in the first mode or not. And if the decision is "yes" in this step 229, a further check is made at step 231 to see if the first mode indicator FL11 is in the player's own RAM 38 has the binary value "1", so that the first game mode can be carried out on the own side of the game. If the first game mode is feasible, a display is displayed on the cathode ray tube 2 (FIG. 1) in the next step 233 with the content "press the switch 18 (or 22)" shown. If the first mode of the game is also not feasible, there is a return to the initial step 201.

If the decision is "no" in step 229, The CPU 28 checks to see if the second mode indicator 122 in the C-RAM 101 has the binary value "1" so as to decide whether the mode was selected by the opponent. If "yes" in this step 235 an indication "press" the switch 20 (or 24) ″ on the cathode ray tube 2 (FIG. 1) is displayed in the next step 237.

If "no" in step 235, the CPU 28 checks whether the second mode indicator FL 12 of the player's own RAM 38 is the Has binary value "1", so that the second game mode is possible on its own side. In the case of "no", followed by a Returning to the previous step 231, if yes, a check is made to see if its own first mode indication FL 11 also has the binary value "1" by which enable first game mode. If the first game mode is possible, an indication "press the." Is displayed in step 242 Switch 18 (or 22) or 20 (or 24) "then shown on the cathode ray tube 2 (Fig. 1).

After the display steps 233, 237 and 242 have been run through, a return to the initial step 201 follows.

If "yes" checks in the previous step 219 (Fig. 3A) the CPU 28 in step 241 to see whether the player's own second mode display FL 12 has the binary value "1" to enable the second game mode. If "no" at this step 241, the CPU 28 checks to see whether the second mode display FL 112 in the C-RAM 101 has the binary value "1" in order to decide whether the game mode on the part of the opponent is the second mode.

If "yes" in the previous step 241, the program proceeds to step 245 and there the CPU 28 writes inputs the binary value "1" into the second mode display FL 112 of the C-RAM 101. A waiting process then follows in step 247 during a predetermined period of time, for example 5 seconds. When the time is up, take the second

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Mode display FL 112 of the C-RAM 101 shows the binary value "0" in the next step 249 before the program goes to the initial step 201 returns. If, before the time is up, it should be decided that the second mode indicator FL 112 of the C-RAM 101 has the binary value "1" on the opponent's side, i.e. H. if the opponent has also selected the second mode, In the next step 235, the CPU 28 subtracts half (Q / 2) of the credit amount (Q) required for playing the second Mode required is taken from the player's own credit (C1) and stores the result as the new credit (C1) of the player. Then, in step 255, the second game mode is executed. Besides, as explained above, it cannot only the display on the cathode ray tube 2 on the player's own side but also on the cathode ray tube on the opponent's side by operating the operating instructions 6 to 16 (FIG. 1), and not only the display on the cathode ray tube 3 but also the display on the cathode ray tube 2 can by means of the operating instructions 7 to 17 can be changed by the opponent. As also described above, the data transmission is carried out in between in this embodiment by sharing the data area of the C-RAM 101.

When the second game mode is over, the CBU 28 changes the second mode display Fl 112 of the C-RAM 101 to the binary value "0" / followed by the return of the program to the initial step.

If "yes" in the above-mentioned step 243 (Fig. 3A), the CPU 29 on the opponent's side subtracts half the amount of credit (Q / 2) required for playing the second Mode is required from the credit (C2) of the opponent and stores the result in the RAM 39 as the new credit (C2) of the opponent. Then, the CPU 29 changes the second mode display FL 112 of the C-RAM 101 to in step 261 the binary value "1" and in the process of step 255 for

the second game mode is entered so that the second game mode is also possible in this way.

In the case of "no" in step 243, the program proceeds to step 229, as in the case of "no" in step 219
away.

In the above-mentioned embodiment, when the first game mode is played independently on the player's side and on the opposite side, that is, on the opponent's side, the contents of the games
be identical or the possibility of choosing from a number of possibilities can also be provided. In the latter case, a plurality of game programs (ROMs) can be provided so that one of them can be selected as desired.

List of reference symbols

¹ housing

2, 3 cathode ray tubes (CRT)

4, 5 slots

6, 12, 7, 13 joysticks

8, 10, 14, 16

Control buttons, operating arrangement 9, 11, 15, 17

18 20 22 24 ^ w.

'''~ ^ - mode switch

19, 21, 23, 25 ^

26, 27 computer system, control arrangement

28, 29 CPU

30, 31 coin selection arrangement

32 address bus

34 data bus

36, 37 ROM

38, 39 RAM

40, 41 PPU

42, 43 characters ROM

44, 45 tone generator

101 C-RAM

102 Address Selection Circuit

103 address bus lines 106 data bus lines 104, 107 tri-state buffers

105 inverter

108, 109 signal lines

Claims (8)

PATENT LAWYERS KLAUS D. KIRSCHNER WOLFGANG GROSSE Dl PL.-PHYSI KER Nintendo Co. Ltd., Japan D I PL.-I NG ENIEUR APPROVED REPRESENTATIVE BEFORE THE EUROPEAN PATENT OFFICE HERZOG-WILHELM-STR. 17 D-8000 MÜNCHEN 2 YOUR MARK: YOURREFERENCE:: O 5834 K / st OURREFERENCE: DATE: 07.12.1984 Video game device claims 1. video game device, characterized by a housing (1), a plurality of display units (2, 3) which are arranged on this housing (1), a plurality of groups of actuating arrangements (6 to 16 and 7 to 17) arranged on the housing (1), each of which is assigned to the display units (2, 3) and can be operated manually, a plurality of control arrangements (26, 27) with which data are transmitted to the corresponding display units (2, 3) as a function of the state of the corresponding actuation arrangements (6 to 16 and are fed 7 to 17) and by a transmission arrangement for direct or indirect transmission and reception of data between a control assembly (26) and another control arrangement (27) and by means of data between at least two Steueranordmmgen (26, 27) of the plurality is Steueran <<can be surmounted. 2. Video game device according to claim 1, characterized in that the transmission arrangement a has common memory arrangement (101) which are accessed by the plurality of control arrangements (26, 27) may and includes a plurality of channels of a bus arrangement interposed between the memory arrangement (101) and each of the control arrangements (26, 27) are arranged. 3. Video game device according to claim 2, characterized in that the communication arrangement further comprises a blocking arrangement (102, 104, 107) for blocking a channel of the bus arrangement (32, 33, 34, 35) as a function of the signals from one of the control arrangements (26, 27) contains. 4. Video game device according to claim 3, characterized in that each channel of the bus arrangement has address bus lines (32, 33) extending between the common Memory arrangement (101) and each control arrangement (26, 27) are arranged and contains data bus lines (34, 35), the are connected between the common memory arrangement (101) and each of the control arrangements (26, 27). 5. video game device according to claim 4, characterized in that the locking arrangements (102, 104, 107) an address selection circuit (102nd) for selectively Switching the address bus lines (32, 34) in response to signals from the control arrangements (26, 27) and gate circuits (104, 107) for switching through each of the data bus lines (34, 35) as a function of the signals. 6. Video game device according to one of claims 1 to 5, characterized in that an operating mode setting arrangement is connected to at least one of the control arrangements (26, 27) and is suitable for selecting one of a plurality of modes, the communication arrangement being enabled when a particular mode has been selected by this mode setting arrangement. 7. video game device according to claim 6, characterized in that if and when another mode has been selected by the mode setting arrangement, the control arrangements the content of the corresponding display arrangement (2, 3) depending only on the state of the corresponding Control operating instructions. 8. Video game device according to one of claims 1 to 7, characterized by cine E inlet opening (4, 5) for a Means of payment, an evaluation arrangement which is connected to the control arrangements (26, 27) and which determines the value of the in the inlet slot (4, 5) inserted currency rated and by an arrangement that allows the selection of the particular Selects mode depending on the recognition of the required value by the evaluation arrangement.