[go: up one dir, main page]

DE3305952A1 - Method of mounting an integrated circuit panel on a substrate - Google Patents

Method of mounting an integrated circuit panel on a substrate

Info

Publication number
DE3305952A1
DE3305952A1 DE3305952A DE3305952A DE3305952A1 DE 3305952 A1 DE3305952 A1 DE 3305952A1 DE 3305952 A DE3305952 A DE 3305952A DE 3305952 A DE3305952 A DE 3305952A DE 3305952 A1 DE3305952 A1 DE 3305952A1
Authority
DE
Germany
Prior art keywords
solder
substrate
layer
plate
windows
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE3305952A
Other languages
German (de)
Inventor
Wilhelm Evilard Salathé
Harry Erlenbach Züst
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ETA SA Manufacture Horlogere Suisse
Ebauchesfabrik ETA AG
Original Assignee
Ebauchesfabrik ETA AG
Eta SA Fabriques dEbauches
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR8302462A priority Critical patent/FR2541044A1/en
Application filed by Ebauchesfabrik ETA AG, Eta SA Fabriques dEbauches filed Critical Ebauchesfabrik ETA AG
Priority to DE3305952A priority patent/DE3305952A1/en
Publication of DE3305952A1 publication Critical patent/DE3305952A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/099—Coating over pads, e.g. solder resist partly over pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10992—Using different connection materials, e.g. different solders, for the same connection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/044—Solder dip coating, i.e. coating printed conductors, e.g. pads by dipping in molten solder or by wave soldering
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

The method of mounting an IC panel on a substrate is to deposit on the substrate (3), which carries conductor tracks (4), a layer (6) of insulating substance which has windows (7) which leave the connection regions (5) of the tracks (4) free. A layer of solder (8) is then deposited on the base of the windows. The panel (1) then only has to be laid on the horizontally held substrate (3) in such a way that the contacts (2) engage in the windows (7) and the solder can be melted. The panel (1) then floats freely on the solder material, as a result of which it is able to assume an optimum position. After the solder has solidified, a complete electrical and metallic connection is produced between the contacts (2) and the conductor tracks (4). <IMAGE>

Description

Verfahren zum Anbringen einer Platte mit integrierter Schaltung auf einem SubstratMethod of mounting an integrated circuit board on a Substrate

Die Erfindung betrifft die Anbringung einer Platte mit einer integrierten Schaltung bzw. einer IC-Platte, von der eine der Flächen mit einer Reihe von Kontaktklötzen oder "Perlen" versehen ist, auf einem Substrat, welches Leiterbahnen aufweist, deren Enden Verbindungsbereiche bilden, die in einer Anordnung angebracht sind, welche der der Kontaktklötze der Platte entspricht.The invention relates to the attachment of a plate with an integrated circuit or an IC board, one of the surfaces with a series of contact blocks or "pearls" is provided, on a substrate which has conductor tracks, the ends of which are connecting areas form, which are mounted in an arrangement which corresponds to that of the contact pads Plate corresponds.

Das bisher allgemein verwendete Verfahren für eine solche Anbringung, bei welcher die Verbindung zwischen den Kontaktklötzen der Platte und den Bahnen des Substrats direkt ohne Verwendung von Drähten oder Verbindungslaschen erfolgt, ist das Löten durchThermokompression. Bei diesem Verfahren wird die Platte auf dem Substrat so positioniert, daß ihre Kontakte aufThe previously generally used method for such an attachment, in which the connection between the contact pads of the plate and the tracks of the substrate directly without use is done by wires or connecting straps, the soldering is done by thermocompression. In this process, the plate is positioned on the substrate so that its contacts on

vden Verbindungsbereichen der Leiterbahnen aufliegen, Die Verbindung erfolgt dann durch gleichzeitige Einwirkung eines mechanischen Drucks, der auf die Platte in Richtung des Substrats ausgeübt wird, und von Wärme. Die Verschweißung bzw. Verlötung erfolgt durch wechselseitige Diffusion des Materials, mit dem vorher die Kontakte und die Verbindungsbereiche überzogen worden sind und welches meistens aus Gold besteht. v the connection areas of the conductor tracks rest. The connection is then made by the simultaneous action of mechanical pressure, which is exerted on the plate in the direction of the substrate, and of heat. The welding or soldering takes place through mutual diffusion of the material with which the contacts and the connection areas were previously coated and which mostly consists of gold.

Außer dem Nachteil, daß die Kontakte und die Verbindungsbereiche mit einem Edelmetall überzogen werden müssen, und außer dem Nachteil, daß die Platte auf dem Substrat vor der Thermokompression sehr genau positioniert werden muß, ergeben sich bei diesem Verfahren Schwierigkeiten dadurch, daß auf die Platte ein Druck ausgeübt werden muß. Dieser Druck muß für die Gewährleistung einer guten Verbindung zwischen dem zu verlötenden Flächen ausreichen, wobei jedoch gleichzeitig sichergestellt sein muß, daß eine solche gute Verbindung auf dem Niveau aller Kontaktperlen besteht, und zwar trotz möglicher Änderungen in der Höhe dieser Kontakte, oder in der Stärke oder auch in der Ebenheit der Leiterbahnen des Substrats, die anschließend durch die unterschiedlichen Verformungen dieser Oberflächen absorbiert werden. Diese auf die Kontakte, die Leiterbahnen oder das Substrat ausgeübten Beanspruchungen bringen die Gefahr mit sich, daß Schaden an einzelnen dieser Bauteile auftreten oder auch daß die Haftung anderer benachbarter Elemente auf dem Substrat beeinträchtigt wird.Apart from the disadvantage that the contacts and the connection areas are coated with a noble metal must be, and besides the disadvantage that the plate on the substrate before thermocompression must be positioned very precisely, difficulties arise with this method in that pressure must be exerted on the plate. This pressure needs to be used for warranty A good connection between the surfaces to be soldered are sufficient, however at the same time it must be ensured that such a good connection is on the level of all Contact pearls exist, despite possible changes in the height of these contacts, or in the strength or the flatness of the conductor tracks of the substrate, which is then followed by the different deformations of these surfaces are absorbed. This on the contacts that Conductor tracks or stresses exerted on the substrate bring the risk that Damage to some of these components occurs or that the liability of other neighboring ones Elements on the substrate is affected.

Die der Erfindung zugrunde liegende Aufgabe besteht deshalb darin, das Verfahren der Anbringung von Platten so auszubilden, daß sie auf einem Substrat angelötet werden können, ohne daß es erforderlich ist, die Klötze bzw. Perlen zu beschichten, die Platten auf dem Substrat sehr genau zu positionieren oder die geringste Beanspruchung auf sie auszuüben.The object on which the invention is based is therefore the method of attachment of plates so that they can be soldered to a substrate without it it is necessary to coat the blocks or beads, the plates on the substrate very precisely position or place the least amount of stress on them.

Diese Aufgabe wird mit dem im Patentanspruch 1 beschriebenen Verfahren gelöst. Die Unteransprüche beschreiben vorteilhafte Ausgestaltungen des erfindungsgemäßen Verfahrens.This object is achieved with the method described in claim 1. The subclaims describe advantageous embodiments of the method according to the invention.

Das erfindungsgemäße Verfahren hat den Vorteil, daß Verlötungen mit Zinn - Blei trotz der geringen Abmessungen der Platten und der Kontaktklötze bzw. -perlen ausgeführt werden können, wobei zusätzlich die Substratanordnung vor Feuchtigkeit, Staub und dergleichen durch die Schicht aus isolierender Substanz geschützt ist.The inventive method has the advantage that soldering with tin - lead despite the small dimensions of the plates and the contact blocks or beads can be made, in addition, the substrate assembly from moisture, dust and the like by the Layer of insulating substance is protected.

Anhand der Zeichnung wird die Erfindung beispielsweise näher erläutert.The invention is explained in more detail, for example, with the aid of the drawing.

Fig. 1 bis 5 zeigen im Schnitt eine Platte und ein Substrat während der Ausführung der verschiedenen Verfahrensstufen.Figures 1 through 5 show, in section, a plate and substrate during the execution of the various Procedural stages.

In Fig. 1 ist eine Platte 1 mit einer integrierten Schaltung gezeigt, welche Kontaktklötze 2 aufweist. Beispielsweise können zehn Kontaktklötze vorgesehen sein, deren Höhe etwa 22 μΐη beträgt. Die Platte 1 wird auf ein Substrat 3 aufgebracht, welche Leiterbahnen 4 aufweist, beispielsweise aus Kupfer, an deren Enden Verbindungsbereiche 5 vorgesehen sind.1 shows a plate 1 with an integrated circuit which has contact blocks 2. For example, ten contact blocks can be provided, the height of which is approximately 22 μm. the Plate 1 is applied to a substrate 3, which has conductor tracks 4, for example from Copper, at the ends of which connection areas 5 are provided.

Für das Anbringen der Platte wird zunächst das Substrat in einer Schicht 6 aus isolierender Substanz überzogen, wie dies in Fig. 2 gezeigt ist, jedoch mit Ausnahme von Fenstern 7, was aus Fig. 3 zu ersehen ist, die im gleichen Muster bzw. inTo attach the plate, the substrate is first covered in a layer 6 of insulating substance covered, as shown in Fig. 2, but with the exception of windows 7, which is evident from Fig. 3 can be seen in the same pattern or in

CopyCopy

— ~ι —- ~ ι -

der gleichen Anordnung vorgesehen sind, wie die Kontaktklötze der Platte, so daß die Verbindungsbereiche 5 frei bzw. ausgespart bleiben. Diese Schicht kann dadurch erhalten werden, daß auf der ganzen Oberfläche des Substrats 3 ein lichtempfindlicher Expoxydharz (Ciba Lack Probimer 52) aufgetragen wird, daß dann die Schicht teilweise isoliert wird und anschließend in die Schicht an der Stelle der Fenster chemisch geätzt wird. Die Stärke der isolierenden Schicht 6 liegt wenigstens in der Nähe der Verbindungsbereiche 5 in der Größenordnung von 20 μΐη. Die Form der Fenster 7 kann quadratisch sein und Abmessungen von etwa 0,35 χ 0,35 mm aufweisen.the same arrangement are provided as the contact blocks of the plate, so that the connecting areas 5 remain free or recessed. These Layer can be obtained by having a photosensitive layer on the entire surface of the substrate 3 Epoxy resin (Ciba Lack Probimer 52) is applied, that then the layer is partially isolated and then into the Layer is chemically etched at the point of the window. The thickness of the insulating layer 6 is at least in the vicinity of the connection areas 5 in the order of 20 μm. the The shape of the window 7 can be square and have dimensions of about 0.35 χ 0.35 mm.

In einer späteren Verfahrensstufe wird dann selektiv auf den durch die Fenster 7 freien bzw. ausgesparten Verbindungsbereichen 5 eine Schicht 8 aus einem Lotmaterial mit einer Stärke aufgebracht, die etwa - zwischen 5 und 10 μπι liegt und geringer ist als die Stärke der Schicht 6.In a later stage of the process, the window 7 free or recessed connection areas 5 a layer 8 of a solder material with a thickness applied which is approximately - between 5 and 10 μm and is less than the thickness of layer 6.

Dies ist in Fig. 4 gezeigt. Es kann eine Legierung aus Zinn und Blei verwendet werden, die durch Eintauchen des Substrats in ein Schmelzbad aus diesem Material aufgebracht wird. Die Gleichförmigkeit der Schicht 8 sowie die Beseitigung von Spuren des Lots außerhalb der ausgesparten Verbindungsbereiche 5 wird dadurch gewährleistet, daß anschließend das Substrat in eine Einrichtung geführt wird, in der in bekannter Weise mit Heißluft nivelliert wird.This is shown in FIG. An alloy of tin and lead can be used through Immersing the substrate in a molten bath made of this material is applied. The uniformity of layer 8 and the removal of traces of the solder outside the recessed connection areas 5 is ensured that the substrate is then fed into a device in which in a known manner with hot air is leveled.

Wie in Fig. 5 zu sehen ist, wird dann die Anbringung der Platte 1 dadurch ausgeführt, daß sie auf dem so vorbereiteten Substrat positioniertAs can be seen in Fig. 5, the attachment of the plate 1 is then carried out by the fact that it positioned on the substrate prepared in this way

CQPYCQPY

und in einer im wesentlichen horizontalen Lage gehalten wird. Dabei greifen die Klötze bzw. Perlen 2 teilweise in die Fenster 7 ein.and held in a substantially horizontal position. The blocks or Beads 2 partially into the windows 7.

Es genügt dann, der so gebildeten Anordnung die Wärme zuzuführen, die erforderlich ist, um das Lotmaterial 8 zum Schmelzen zu bringen, wofür beispielsweise das Substrat über seinen unteren Teil erwärmt wird, wie dies durch die Pfeile Q veranschaulicht ist. Unter diesen Bedingungen, nämlich unter dem Einfluß der Oberflächenspannungen des im Schmelzen befindlichen Lots und der Oberfläche der Klötze, bringt sich die Platte, welche frei auf den verschiedenen Massen des geschmolzenen Lots schwimmen kann, selbst in die optimale Position, wobei das Lot die Basis jedes Kontaktklotzes ummanteln kann.It is then sufficient to supply the arrangement formed in this way, the heat that is required to to bring the solder material 8 to melt, for which purpose, for example, the substrate over its lower Part is heated, as illustrated by the arrows Q. Under these conditions, namely under the influence of the surface tensions of the melting solder and the surface the clogs, the plate, which brings itself freely on the various masses of the melted Lots can float, even in the most optimal position, with the solder being the base of each contact block can sheath.

Nach der Abkühlung und Verfestigung des Lots erhält man so eine elektrische und mechanische Verbindung zwischen jedem Kontakt 2 und dem entsprechenden Verbindungsbereich 5 der Leiterbahnen 4.After the solder has cooled and solidified, an electrical and mechanical connection is obtained between each contact 2 and the corresponding connection area 5 of the conductor tracks 4th

Claims (7)

ν. FDNER EBBINGHAUS FINCKν. FDNER EBBINGHAUS FINCK PATENTANWÄLTE EUROPEAN PATENT ATTOU NEY.SPATENT LAWYERS EUROPEAN PATENT ATTOU NEY.S MAWIAHILFPLATZ 2 Λ 3, MÖNCHEN 'IO POSTADRESSE: POSTFACH 95 O1 6O. D-HOOO MÜNCHt.N 9t>MAWIAHILFPLATZ 2 Λ 3, MÖNCHEN 'IO POST ADDRESS: POST BOX 95 O1 6O. D-HOOO MÜNCHt.N 9t> ETA S.A. Fabriques DEAC-30682.1ETA S.A. Fabriques DEAC-30682.1 d'Ebauches 21. Februar 1983d'Ebauches February 21, 1983 Verfahren zum Anbringen einer Platte mit integrierter Schaltung auf einem SubstratMethod of attaching an integrated circuit board on a substrate PatentansprücheClaims Verfahren zum Anbringen einer .PLatte mit integrierter Schaltung, die auf einer Seite mit einer Reihe von Kontaktklötzen versehen ist, auf einem Substrat, welches Leiterbahnen aufweist, deren Enden Verbindungsbereiche bilden, die in einem Muster ancreordnet sind, welches dem der Kontaktklötze der Platte entspricht, dadurch gekennzeichnet, daß die Oberfläche des Substrats mit einer Schicht einer isolierenden Substanz mit Ausnahme von Fenstern überzogen wird, die ebenfalls dem Muster der Kontaktklötze der Platte entsprechend so angeordnet sind, daß die Verbindungsbereiche der Leiterbahnen unbeschichtet bleiben, daß dann eine Lotschicht auf den Verbindungsbereichen der durch die Fenster unbeschichtet gebliebenen Leiterbahnen abgelegt wird, daß anschließend die Platte mit der integrierten Schaltung auf das Substrat gelegt wird, das in einer im wesentlichen horizontalen Stellung gehalten wird, V7obei die Kontaktklötze der PlatteMethod for attaching a plate with an integrated Circuit, which is provided with a row of contact blocks on one side, on a substrate, which has conductor tracks, the ends of which form connection areas which are arranged in a pattern which corresponds to that of the contact blocks of the plate, characterized in that that the surface of the substrate with a layer of an insulating substance except for Windows is covered, which are also arranged according to the pattern of the contact blocks of the plate are that the connection areas of the conductor tracks remain uncoated, that then a layer of solder is placed on the connection areas of the conductor tracks left uncoated by the window, that then the plate with the integrated circuit is placed on the substrate that is held in a substantially horizontal position, V7 with the contact pads of the plate den entsprechenden Fenstern gegenüberliegend angeordnet sind, daß daraufhin der so gebildeten Anordnung Wärme zugeführt wird, die ausreicht, um das Lot zum Schmelzen zu bringen, wodurch sich die Platte dann unter der Wirkung der Oberflächenspannungen frei so positionieren kann, daß jede ihrer Kontaktklötze in Kontakt mit der entsprechenden Zone des im Schmelzen befindlichen Lots kommt, und daß schließlich das Lot verfestigt gelassen wird.the corresponding windows are arranged opposite, that thereupon the arrangement so formed heat sufficient to melt the solder, which then turns the plate can position freely under the action of surface tension so that each of its contact blocks comes into contact with the corresponding zone of the solder in melting, and that eventually the solder is allowed to solidify. 2. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß die Schicht aus isolierender Substanz, welche die Fenster bildet, durch Ablage, partielle Isolierung und anschließende chemische Ätzung einer Fotoepoxydlackschicht erhalten wird.2. The method according to claim 1, characterized in that the layer of insulating Substance that forms the windows by filing, partial insulation and subsequent chemical etching of a photo epoxy lacquer layer is obtained. 3. Verfahren nach Anspruch 1 oder 2, dadurch gekennzeichnet, daß Fensterabmessungen in der Größenordnung von 0,35 χ 0,35 mm verwendet werden.3. The method according to claim 1 or 2, characterized in that window dimensions on the order of 0.35 χ 0.35 mm can be used. 4. Verfahren nach einem der Ansprüche 1 bis 3, dadurch gekennzeichnet, daß eine Schicht aus isolierender Substanz wenigstens in der Nähe der Verbindungsbereiche mit einer Stärke in der Größen-Ordnung von 20 μηι verwendet wird.4. The method according to any one of claims 1 to 3, characterized in that a layer of insulating substance at least in the vicinity of the connection areas with a thickness on the order of magnitude of 20 μηι is used. 5. Verfahren nach einem der Ansprüche 1 bis 4, dadurch gekennzeichnet, daß eine Lotschicht mit einer Stärke von etwa 5 bis etwa 10 μπι verwendet wird.5. The method according to any one of claims 1 to 4, characterized in that a solder layer used with a strength of about 5 to about 10 μπι will. i. Verfahren nach einem der Ansprüche 1 bis 5, dadurch gekennzeichnet, daß die Abscheidung der Lotschicht dadurch erhalten wird, daß das mit der Schicht aus isolierender Substanz überzogene Substrat in ein Schmelzbad des Lots getaucht und dann in eine in an sich bekannter Weise mit Warmluft nivellierende Einrichtung geführt wird.i. Method according to one of Claims 1 to 5, characterized in that the deposition of the solder layer is obtained in that that with the layer of insulating Substance-coated substrate is immersed in a molten pool of solder and then in an in-itself known way is performed with warm air leveling device. 7. Verfahren nach einem der Ansprüche 1 bis 6, dadurch gekennzeichnet, daß das Lotmaterial eine Legierung aus Zinn und Blei ist.7. The method according to any one of claims 1 to 6, characterized in that the Solder material is an alloy of tin and lead.
DE3305952A 1983-02-21 1983-02-21 Method of mounting an integrated circuit panel on a substrate Withdrawn DE3305952A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR8302462A FR2541044A1 (en) 1983-02-21 1983-02-14 Method for mounting a printed-circuit board on a substrate
DE3305952A DE3305952A1 (en) 1983-02-21 1983-02-21 Method of mounting an integrated circuit panel on a substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE3305952A DE3305952A1 (en) 1983-02-21 1983-02-21 Method of mounting an integrated circuit panel on a substrate

Publications (1)

Publication Number Publication Date
DE3305952A1 true DE3305952A1 (en) 1984-08-23

Family

ID=6191397

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3305952A Withdrawn DE3305952A1 (en) 1983-02-21 1983-02-21 Method of mounting an integrated circuit panel on a substrate

Country Status (2)

Country Link
DE (1) DE3305952A1 (en)
FR (1) FR2541044A1 (en)

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4808769A (en) * 1986-09-25 1989-02-28 Kabushiki Kaisha Toshiba Film carrier and bonding method using the film carrier
EP0307766A1 (en) * 1987-09-09 1989-03-22 Siemens Aktiengesellschaft Circuit board to be imprinted with SMD components
DE3824008A1 (en) * 1988-07-15 1990-01-25 Contraves Ag ELECTRONIC CIRCUIT AND METHOD FOR THE PRODUCTION THEREOF
US4955523A (en) * 1986-12-17 1990-09-11 Raychem Corporation Interconnection of electronic components
WO1990013990A2 (en) * 1989-05-02 1990-11-15 Hagner George R Circuit boards with recessed traces
EP0439137A2 (en) * 1990-01-23 1991-07-31 Sumitomo Electric Industries, Ltd. Substrate for packaging a semiconductor device, packaging structure and method
EP0439134A2 (en) * 1990-01-23 1991-07-31 Sumitomo Electric Industries, Ltd. Substrate for packaging a semiconductor device, packaging structure and method
US5055637A (en) * 1989-05-02 1991-10-08 Hagner George R Circuit boards with recessed traces
FR2671933A1 (en) * 1991-01-18 1992-07-24 Ramy Jean Pierre Method of integrating solder material into the fabrication of circuits and housings for electronics
US5189507A (en) * 1986-12-17 1993-02-23 Raychem Corporation Interconnection of electronic components
EP0543411A2 (en) * 1991-11-20 1993-05-26 Sharp Kabushiki Kaisha A wiring board and a method for producing the same
US5341564A (en) * 1992-03-24 1994-08-30 Unisys Corporation Method of fabricating integrated circuit module
US5924623A (en) * 1997-06-30 1999-07-20 Honeywell Inc. Diffusion patterned C4 bump pads
DE10101359A1 (en) * 2001-01-13 2002-07-25 Conti Temic Microelectronic Method of manufacturing an electronic assembly
DE102019126908A1 (en) * 2019-10-08 2021-04-08 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Process for the production of functional objects, functional object

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3676832D1 (en) * 1985-02-15 1991-02-21 Ibm SOLDERED CONNECTION BETWEEN CHIP AND SUBSTRATE AND METHOD FOR PRODUCING THE SAME.
JPS62263645A (en) * 1986-05-06 1987-11-16 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Construction of electric contact and method of forming the same
FR2644632B1 (en) * 1988-04-22 1994-06-17 Commissariat Energie Atomique DETECTION ELEMENT CONSISTING OF DETECTOR BARS

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3429040A (en) * 1965-06-18 1969-02-25 Ibm Method of joining a component to a substrate
GB1361400A (en) * 1970-12-30 1974-07-24 Lucas Industries Ltd Method of electrically connecting a semi-conductor chip to a substrate

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4808769A (en) * 1986-09-25 1989-02-28 Kabushiki Kaisha Toshiba Film carrier and bonding method using the film carrier
US4857671A (en) * 1986-09-25 1989-08-15 Kabushiki Kaisha Toshiba Film carrier and bonding method using the film carrier
US4955523A (en) * 1986-12-17 1990-09-11 Raychem Corporation Interconnection of electronic components
US5189507A (en) * 1986-12-17 1993-02-23 Raychem Corporation Interconnection of electronic components
EP0307766A1 (en) * 1987-09-09 1989-03-22 Siemens Aktiengesellschaft Circuit board to be imprinted with SMD components
DE3824008A1 (en) * 1988-07-15 1990-01-25 Contraves Ag ELECTRONIC CIRCUIT AND METHOD FOR THE PRODUCTION THEREOF
EP0358867A1 (en) * 1988-07-15 1990-03-21 Oerlikon-Contraves AG Flip-chip mounting with a solder barrier layer made from oxidisable metal
US5055637A (en) * 1989-05-02 1991-10-08 Hagner George R Circuit boards with recessed traces
WO1990013990A3 (en) * 1989-05-02 1991-01-10 George R Hagner Circuit boards with recessed traces
WO1990013990A2 (en) * 1989-05-02 1990-11-15 Hagner George R Circuit boards with recessed traces
EP0439137A3 (en) * 1990-01-23 1994-01-05 Sumitomo Electric Industries
EP0439134A2 (en) * 1990-01-23 1991-07-31 Sumitomo Electric Industries, Ltd. Substrate for packaging a semiconductor device, packaging structure and method
EP0439134A3 (en) * 1990-01-23 1994-02-02 Sumitomo Electric Industries
EP0439137A2 (en) * 1990-01-23 1991-07-31 Sumitomo Electric Industries, Ltd. Substrate for packaging a semiconductor device, packaging structure and method
FR2671933A1 (en) * 1991-01-18 1992-07-24 Ramy Jean Pierre Method of integrating solder material into the fabrication of circuits and housings for electronics
EP0543411A3 (en) * 1991-11-20 1993-09-29 Sharp Kabushiki Kaisha A wiring board and a method for producing the same
EP0543411A2 (en) * 1991-11-20 1993-05-26 Sharp Kabushiki Kaisha A wiring board and a method for producing the same
US5397864A (en) * 1991-11-20 1995-03-14 Sharp Kabushiki Kaisha Wiring board and a method for producing the same
US5341564A (en) * 1992-03-24 1994-08-30 Unisys Corporation Method of fabricating integrated circuit module
US5924623A (en) * 1997-06-30 1999-07-20 Honeywell Inc. Diffusion patterned C4 bump pads
DE10101359A1 (en) * 2001-01-13 2002-07-25 Conti Temic Microelectronic Method of manufacturing an electronic assembly
DE102019126908A1 (en) * 2019-10-08 2021-04-08 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Process for the production of functional objects, functional object

Also Published As

Publication number Publication date
FR2541044A1 (en) 1984-08-17

Similar Documents

Publication Publication Date Title
DE3305952A1 (en) Method of mounting an integrated circuit panel on a substrate
DE69204516T2 (en) Printed circuit board with solder coating and process for its manufacture.
DE69836230T2 (en) STRUCTURE AND ELECTRONIC DEVICE CONNECTED TO A LEAD-FREE SOLDER
DE1300788C2 (en) PROCESS FOR THE PRODUCTION OF SPHERICAL SOLDER BEADS ON CARRIER PLATES
DE3818894C2 (en)
DE3042085C2 (en) Semiconductor device
DE3332482A1 (en) COPPER ALLOY WITH HIGH OXIDATION RESISTANCE SUITABLE FOR LADDERS IN SEMICONDUCTOR DEVICES, AND COMPOSITE MATERIAL CONTAINING THIS ALLOY
DE69027448T2 (en) Movements and device for fastening contact bumps on TAB carrier conductors
DE3824008A1 (en) ELECTRONIC CIRCUIT AND METHOD FOR THE PRODUCTION THEREOF
DE69215377T2 (en) MELTING SOLDERING PROCESS FOR FORMING A SOLDERING STICK ON A PRINT PLATE
DE69620273T2 (en) Process for the production of spacers on an electrical circuit board
DE69704678T2 (en) METHOD FOR PRODUCING A TIN / LEAD LAYER PCB ASSEMBLY
DE3502744C2 (en)
EP0487782A1 (en) Method of soldering circuit boards
DE2419157A1 (en) METALLIC SUPPORT FOR SEMICONDUCTOR ELEMENTS
DE19622971A1 (en) Semiconductor device for SMT and mfg. method
DE69803664T2 (en) METHOD FOR PRODUCING PRINTED CIRCUIT BOARDS AND PRINTED CIRCUIT BOARDS PRODUCED THEREOF
DE1915148C3 (en) Process for the production of metallic bumps in semiconductor devices
WO2024110246A1 (en) Method for producing an electronic component
DE10059808A1 (en) Method of connecting an integrated circuit and a flexible circuit
DE69328211T2 (en) Installation of electronic components on mounting plates using reflow technology
EP2916631B1 (en) Structuring of the solder resist mask of circuit boards for improving soldering results
DE69105093T2 (en) Hybrid circuit formed from two circuits, the conductor tracks of which are electrically connected by connecting balls.
DE10157320A1 (en) Process for making micro sliding contacts
DE69331649T2 (en) TAB tape and its manufacturing process

Legal Events

Date Code Title Description
8139 Disposal/non-payment of the annual fee