DE3125529A1 - "METHOD FOR RECODING A SEQUENCE OF DATA BITS INTO A SEQUENCE OF CHANNEL BITS, ARRANGEMENT FOR DECODING THE CHANNEL BITS ENCODED BY THIS METHOD AND RECORDING MEDIUM WITH AN INFORMATION STRUCTURE" - Google Patents

Description

NV Philips' 6l0Giiampenfabtic5srf, ". Hndßovere ^:: ..". ^:: ". 1 31255

tt · ···· · · · PHQ 80.007 *> 12-6-1981

"Method for recoding a sequence of data bits into a sequence of channel bits, arrangement for decoding those after this Methods encoded channel bits and record carriers with an information structure ".

A. Background of the invention »

• A (1) field of the invention .

The invention relates to a method for

Recoding a sequence of data bits into a sequence of channel bits, 5

The sequence of data bits is divided into consecutive blocks of m data bits each and these blocks _{are recoded into consecutive blocks of (n + n_) channel bits (n 1} + n "> m) and the blocks of channel bits each .a block of n information bits and a block of '

n ₂ separating bits contain such that successive blocks of information bits are separated by only one block of separating bits each, two successive channel bits of a first type, of the type "1", by at least d immediately successive bits of a second type, the 15th

Type "0", to be separated and the number of immediately consecutive Channel bits of the second type is at most k, and to a demodulator for decoding the corresponding the process coded data bits and on a

Recording media with a means of this method er-20

evoked information structure with sequences of channel bit cells.

In digital transmission or in magnetic and optical recording / playback systems, the information to be transmitted or recorded is mostly in the form of a sequence of characters. These signs form to- '. .

together the (_of binary) alphabet. In the event that it does is a binary alphabet (this alphabet is also represented by the characters "1" and "0") the one character, for example the "1", corresponds to the

NRZ Mark code on the magnetic disk, magnetic tape or 30th

on the optical disk as a transition between two states be determined by magnetization · or focus. The other character, the "0", is due to the lack of such Transitional set.

β ο β
• β ο *

on

PHQ 80.007 ? α 12-6-1981

In practice, as a result of certain system requirements exist for the sequences of characters that appear allowed, restrictions. In some systems the requirement is that the sequence of characters is self-clocking is. This means that the sequence of characters to be transmitted or recorded has sufficient transitions must to a clock pulse signal that is used for detection and synchronization is necessary to generate from the string. Another requirement may be that certain Character strings in the information signal are avoided • should, because these sequences are reserved for special purposes, for example synchronization sequences. An imitation the synchronization sequence by the information signal affects the uniqueness of the synchronization signal and thus its suitability for this purpose. Another The requirement may be that the transitions are not mutually exclusive followed quickly to limit intersymbol interference.

In the case of magnetic or optical recording, this requirement can also be related to the information density be brought into connection with the recording medium, if at a certain minimum distance between two successive transitions on the record carrier the corresponding minimum time interval (T.) of the signal to be recorded can be increased the information density increases to the same extent. The minimum bandwidth (B.) That is required also depends on the minimum distance T. between transitions (Β. = -R = r ~ - ") together.

^min

min 2T

If information channels are used that do not have any Transmitting direct current, as is mostly the case with magnetic recording channels, leads to the Requirement that the character strings in the information channel have the lowest possible (or none at all)

Have direct current component.

A (2) Description of the state of the art .

A method of the type described at the outset is known from reference material D (i). The article relates

PHQ 80.007 ¥ λ 12-6-1981

altjii aiii "ßlooidcodleruugen, where it is assumed that d-, k- or (d, k) -limited q-valued blocks of characters and the blocks meet the following requirements:

(a) d-delimited: two type "1" characters are separated by a

Sequence of at least d consecutive type "O" characters separated;

(b) k-bounded: the maximum length of a sequence of consecutive ones Character of the type "0" is k.

A sequence of data bits is divided into immediately successive blocks of m data bits each. These blocks of m data bits are recoded into blocks of η information bits (n ^> m). Because η ^ m, the number of combinations with η information bits is greater than the number of possible blocks of data bits (2). If the request is limited to, for example, the to be transferred or blocks to be recorded information bits are set, the mapping of the 2 blocks of data bits to 2 blocks of information bits (from a possible Number of 2 blocks) is selected such that information bits are only mapped to those blocks that contain the meet the requirement.

Table I on page 439 from reference material D (i) shows how many different blocks of information bits there are, depending on the length of the block (s) and the requirements placed on d. There are 8 blocks of information bits with a length η = 4 under the condition that the minimum distance d = 1. Therefore, blocks of data bits with a length m = 3 (2 = 8 data words) could be reproduced by blocks of information bits with a length η = K , with two consecutive type "1" characters being replaced by at least one type "O" in the blocks of information bits. Characters are separated. the

The coding for this example is then (the .character <»

stands for mapping one block to the other and vice versa):

OO β & οοαο »ο β

β »<& ♦ ©« Q & β »» »Β

rape * »· * ft * OO» ο * «e

PHQ 80.007 K ß 12-6-1981

000 «.— * ■ 0000

001> 0001

010 * J 0010

01 1 * -— * 0100

100 -ί? 0101

101 «» 1000

110 4 »· 1001

11 1 « * 1010

In the case of closed information words, however, in some cases the "requirement (in the example the d requirement) cannot be met without further ado. In the article cited, it is proposed to insert separator bits between the blocks of information bits. In the case of the d-delimited ones Coding, a block of separating bits with d-bits of the type "0" is sufficient. In the example given above with d = 1, only one separating bit is sufficient (only one zero). Each block of 3 data bits is then marked with 5 (h + 1) Channel bits encoded.

A disadvantage of this type of coding is that the proportion of low frequencies (including direct current) at the frequency spectrum of the stream of channel bits is quite high. Another disadvantage is that the code converter (Modulator, demodulator) and especially the demodulator is involved.

With regard to the first disadvantage, it should be mentioned that reference material D (2) specifies that the direct current component of the (d, k) -limited codings can be limited by using a so-called inverting or non-inverting block to channel bits Link to be connected. The sign of the contribution of the current block. Channel bits to the direct-current component is the fact that the DC component of the preceding blocks of channel bits is reduced so selected _e Es (k d) request can be closed handeltsich here, however, a (d, k) -limited coding, the blocks of information without interfering with the which eliminates the need to add separator bits for this reason. B. Summary of the Invention.

PHQ 80007 X · _Α 12-6 + 1!

• β «

The object of the invention is to provide a method of the type mentioned at the beginning for coding a sequence of data bits into a sequence to create channel bits that have the low frequency spectrum properties of the signal to be derived from the channel bits and a simple demodulator enables.

According to the invention, this object is achieved by the following steps:
. Converting blocks of data bits containing m bits into blocks of information bits containing η bits;

2. The generation of several possible sequences of channel bits,

each at least one block of information bits and one Contain block separating bits and each block of information bits included, supplemented by only one of the possible bit combinations of the blocks separating bits;

3. Determining the DC component of each of the possible sequences of channel bits that was determined in the previous step became;

k. For each of the possible sequences of channel bits, the determination of the sum of the number of separating bits and the number of immediately successive information bits of the type "0" which immediately precedes a bit of the type "1" and the sum of the number of a bit of the type "1" follows, which forms part of one of the blocks of separating bits, and the sum of the number of separating bits and the number of immediately successive information bits of the type "0" which immediately precedes this block of separating bits, and follows;
5- The generation of a first display signal for the sequences of channel bits for which the value of the sums determined in the previous step are greater than d and at most equal to k;

6. Selecting the sequence of channel bits which have led to the first display signal of this sequence of channel bits, which minimizes the direct current component, from the sequences of channel bits for which the first display signal was generated.
C. Brief description of the drawings .

«A e> ο ft * * e> * «·

«* Q β ft · · ¥ 0-4 oo · · β

PHQ 80.007 ^ 12-6-1981

Exemplary embodiments are based on the drawings the invention and its advantages explained in more detail. Show:

1 shows a few bit sequences to explain an exemplary embodiment of the coding format according to the invention ;

Fig. 2 shows some further embodiments of the format of the channel coding, as is the case with the reduction the direct current component can be used according to the invention;

3 shows a flow diagram of an exemplary embodiment of the method according to the invention,

4 shows a representation of a block of synchronization bits for use in the method according to the invention,

5 shows an embodiment of an inventive Demodulator for decoding, according to the invention coded data bits,

6 shows an embodiment of the means for detecting a sequence of synchronization bits after the Invention,

7 shows an embodiment of a frame format for use in the method according to the invention.

Corresponding elements in the figures are given the same reference symbols.

D. Reference material .

(i) Tang, DT, Bahl, LR, "Block codes for a class of constrained noiseless channels", Information and Control Issue 17, No. 5, Dec. 1970, pages 4-36-461. (2) Patel, AM, "Charge-constrained byte-oriented (0,3) code", IBM Technical Disclosure Bulletin, Issue 19, No. 7, Dec. 1976, pp. 2715-2717.

E. Description of the exemplary embodiments .

F.g. 1 shows some bit sequences to explain the method for recoding a sequence of data bits (Fig. 1a) into a sequence of channel bits (Fig. 1b). The sequence of data bits is in closed and consecutive blocks BD divided up. Each block of data bits has rn data bits. as

PHQ 80.007 - * "/ JA 12-6-1981

Example is continued in the description and in the Figures m = 8 selected. Pur every other value of m applies but the same. A block of m data bits BD. generally contains one of 2 possible bit sequences.

Bit sequences of this kind are less suitable for direct optical or magnetic recording, for different reasons. If namely two data characters of the type "1", which are on the record carrier for example as a transition from one direction of magnetization to the other or as a transition to one Well recorded, each other immediately follow, these transitions cannot be too close together because of the mutual influence. The information density is limited thereby. At the same time, the minimum bandwidth B. enlarged that is required to to transmit or record the bit stream when the minimum distance T. between successive transitions (B. = 1 / (2T.) Is low. Another requirement that is often placed on systems for data transmission and optical or magnetic recording is made, is that the bit sequences have enough transitions to get out of the transmitted. Signal to recover a clock pulse signal with synchronization can be generated. A place with m zeros, which in the worst case is preceded by a word that ends on a number of zeros and followed by a word that starts with a number of zeros, the clock pulse extraction would endanger.

To information channels that do not have direct current transmitted, like magnetic recording channels In addition, there is a requirement that the Data stream has the lowest possible direct current component. In the case of optical recording, it is desirable that the low-frequency part of the data spectrum is optimally suppressed because of the servo controls. Besides that the demodulation is simplified if the direct current component is relatively low.

For the above and other reasons, so-called channel coding is applied to the data bits

PHQ 80.007 Ϋ A3 12-6-1981

before they are transmitted or recorded via the channel. In the case of block coding (reference material. L D (i)), the blocks of data bits that each contain m bits are coded as blocks of information bits that each contain η information bits. In Fig. 1 it is shown how the block data bits BD. into a block of information bits BI. is converted. As an example, η = 14 is chosen in the further description and in the figures. Because τι is larger than m, not all combinations that _{can be formed with Ii 1} bits are also used; those combina-. Functions that do not match the channel to be used are not used. In the example given, only 256 of the 16,000 possible channel words need to be selected for the required one-to-one mapping of data words to channel words. Some requirements can therefore be made of the channel words. One requirement is that between two successive information bits of a first type, the type '.' 1 ", within the same block of n .. information bits at least d immediately consecutive information bits of a second type, the type" O ", lie. Table I on page 439 of reference material D (i) shows how many binary words there are depends on the value of d. The table shows that for η = ~ \ k 277 words with at least two (d = 2) bits of the type "0" between successive bits (of the 'type " 1 "). When coding blocks of 8 data bits, of which

2 = 256 combinations can occur as blocks of 14 Channel bits, the requirement d = 2 can definitely be met.

A juxtaposition of the blocks of information bits BI. However, this is not easily possible if the same requirement for a d-limitation is not only made within a block of n ₁ bits, but also calculated across the boundary of two consecutive blocks. For this purpose, reference material D (i) proposes (page ^ · 51) »to include one or more separating bits between the blocks of channel bits. It is easy to see that if at least a number of Trenribits of the type "O" on-

PHQ 80.007 ST A1 {12-6-1981

is taken, which is equal to d, then the requirement of a d-limitation is met for the entire sequence of channel bits. In Fig. 1 it is shown that a block channel bits BC. from the block information bits BI. and a block of separating bits BS. consists. The block separating bits has n_ bits, as a result of which the block has channel bits BCi tl + n "bits. As an example, in the further description and in the figures, if not stated otherwise, n ″ = 3 is chosen.

In order to make the clock pulse generation as reliable as possible, the requirement can also be made that the maximum number of type "O" bits that are continuous between two consecutive type "1" bits within only one block of information bits may occur, is restricted to a certain value k. In. the given example with m = 8 and η = 14, from the 277 words, which correspond to the condition d = 2, for example those words are eliminated which are very large for k Have value. It turns out that k is on 10

can be restricted. Therefore, a sequence of 2 (generally 2) blocks of data bits of 8 bits each (generally in) mapped onto a sequence of likewise 2 (generally 2) blocks of information bits, which are also mapped by the request d = 2 and k = 10 (generally d, k - limited) selected from 2 (generally 2) possible blocks of information bits are. The assignment of each of the blocks of data bits to only one of the blocks of information bits is in itself still a free one Choice. In the reference material D (i) mentioned, the conversion of data bits into Information bits clearly determined. Although this conversion is basically usable, as will be explained in more detail below a different assignment is preferred.

Connection of the also ^ ^. limited Channel words BI. is, as was the case for only d-delimited blocks, only possible if separating blocks are between the Blocks of information bits BI. are provided. You can do this basically the same separator blocks of η bits each are used because the requirements d - limited and k- limited are not opposing but rather complementary.

3Ί25529

PHQ 80.007 VB At. 12-6-1981

Should · dalier be the sum of the number of bit values of the type "0", that precedes a particular separator block, the number that the separator block follows, and the n "bits of the separator block itself exceed the ¥ ert k, at least one of the bit values of type "0" of the separator block are replaced by a bit value of type "1", so that the sequence of zeros

is divided into episodes, each at the most k are long.

Except to ensure that the requirements the (d, k) limitation are met, the separating blocks can be dimensioned in such a way that they also can be used to minimize the direct current component. This is based on the knowledge that for some interconnections of blocks of information bits stipulate a certain format of the block separating bits However, in a large number of cases either no requirements or only limited requirements for the Format of the block separator bit can be set. The space created in this way is used to minimize the DC component used.

The development and growth of the direct current component can be explained as follows. The Infornia-r block tion bits BI according to Fig. 1b is set for example in the form of an NRZ mark format on the recording medium. In this format, a "1" is retained by a transition at the beginning of the relevant bit cell and a "0" recorded as no transition. The in BI. shown Bit sequence then assumes a form which is denoted by WF and in which this bit sequence on the record carrier is recorded. This sequence has a direct current component, because in the sequence in question the positive level is the negative Exceeds level in length. A measure that is often used for the DC component is the digital one Sum value, abbreviated DSW. The DSW is, provided that the levels of the waveform WF + 1 or -1, then equal to the running integral of the waveform WF and in the example shown in FIG. 16 is + C) T, where T is the length of only one bit interval. If such a

PHQ 80.007 y <Al » 12-6-1981

are repeated one after the other, the direct current component to grow. This DC component generally leads to and reduces the base line movement effective signal-to-noise ratio and thus the reliability of the detection of the recorded signals.

The block separating bits BS. is used to limit the DC component as follows. At a given moment, a block of data bits becomes BD. offered. This block of data bits BD. is converted into a block of information bits BI by means of a table stored in a memory, for example; A number of possible _{blocks containing (n 1} + n ") bits of channel bits are then generated. These blocks all contain the same block of information bits (bit cells 1 up to and including 14, FIG. 1b), supplemented by the possible bit combinations of the n _? Separation bits (bit cells I5, 16 and 17, Pig. 1b). Therefore, in the example according to FIG. 1b, a sequence of channel bits is produced, consisting of 2 ⁿ 2 = 8 possible blocks. The following parameters are then determined from each of the possible blocks of channel bits in any order:

a) determine whether channel bits for the possible block in question, taking into account the previous block the requirement of the d-limit and the requirement of the k-limit do not coincide with the format of the subject Blocks separating bits contradicts;

b) determine which of the DSW is channel bits for the relevant possible block.

For the possible blocks channel bits, which are in the requirement of the d-limitation and k-Be ~

firornÄiuif; densely wlderaprechen, a first display signal generated. The choice of the coding parameters ensures that such a display signal is generated for at least one of the possible blocks of information bits. Finally the possible blocks become channel bits for which a first display signal is generated, for example the block channel bits selected which has the smallest DSW in the absolute value. A better method, however, is the DSW of the previous one Blocks of channel bits to be saved and

PHQ 80.007 J £ 4 ^ 12-6-1981

nalbits that are to be transmitted next come into consideration to choose the block that contains the stored DSW can decrease in absolute value. The word selected in this way is transmitted or recorded.

One advantage of this method is that the separation bits that are already required for other purposes make it easy to use Way also used to limit the direct current component can be. Another advantage is that the interference in the transmitted signal on the blocks separating bits

^ is limited and does not extend to the blocks of information bits extends (regardless of the polarity of the waveform to be transmitted or recorded). The demodulation of the recorded signal read out then only needs to refer to the information bits. the

'5 separating bits can be disregarded.

Some further exemplary embodiments of the method are shown in FIG. 2. Figure 2a shows schematically the series of blocks of channel bits BC. , BC., BC. , . . . that contain a predetermined number (n ₁ + n _o ) bits. The blocks of channel bits contain blocks of information bits of η bits each and blocks of separating bits ... BS. , BS. , BS., BS. ... of n_ bits each.

In this exemplary embodiment, the glacial current component is determined over several blocks at the same time, both

^ ^{5, for} example, as also shown in Fig. 2a, over two blocks of channel bits BC. and BC. “The determination of the direct current component is carried out in the same way as in the exemplary embodiment according to FIG. 1 in the sense that for each superblock SBC. the possible formats super blocks are generated, ie the blocks information bits for block BC. and block BC. are used with all the possible combinations that start with the n “separator bits of the block BS. and the block BS. can be formed, supplements. From this amount that combination is then chosen which minimizes the glass current component. An advantage of this method is that the remaining direct current component has a smaller character because it is possible to see in advance which intervention is optimal over more than one block of channel bits. One

Kr <O * «r ♦ WW * #«

, * W * - w w tf w-w W *

to «· * *» «w β C · ν ν

PHQ 80.007 I ^ Λ & 12-6-1981

A favorable modification of this procedure differs in that the superblock is SBC. (Fig. 2a) after performed Minimization of the direct current imbalance by only one ßl.ock Kniialbiüs BC. is moved. This means that the block BC. (in Pig, 2a), which is part of the superblock SBC. forms, is processed and the following superblock

SCB. (not shown) the blocks BC. and BC. i + 1 i + i i

(not shown), thus making the one shown above Minimization of the direct current imbalance is carried out. The block BC. thus forms part of the Superblocks SBC. as well as the following block SBC. . It it is entirely possible that the (temporary) number for the separator bits in block BS. marked in the superblock SBC. of the final choice in the superblock SBC. deviates.

By using each block multiple times (twice in this example), the DC imbalance and so that the noise component is further reduced.

Fig. 2b shows a further embodiment, where the direct current component is determined over several blocks simultaneously (SBCj), for example, as shown in Fig. 2b, over four blocks of channel bits BCj ^ ¹ ', () (k)

(Ί) (k)
BCj ^v - 'and BCj ^v . These blocks of channel bits each contain a specific Αηζειίιΐ n. Information bits. The number of separator bits

(i) (2) (^) (k) the blocks separating bits BSj ^ ", BSj ^v; , BSj ^VJ '' and BSj ^v 'is included, but not the same for each block of channel bits. For example, the number of information bits can be 14, and the number of separating bits can be for the blocks

fiT (2) (i) '(k)

BSj ^V17 , BSj ^v ' and BSj ^VJ; 2 each and for block BSj ^v; 6. The direct current component is determined in a corresponding manner as has been described for the exemplary embodiment according to FIG. 2a.

An advantage of this procedure - besides the advantages already mentioned, which also apply in this case, that the availability of a relatively long block Separation bits increase the possibilities for limiting the direct current component. In particular, the remaining direct current component is a sequence of channel bits, with each block of channel bits having an equal number of e.g. 3 bits.

OO · C

PHQ 80.007

J * AS

3125529 12-6-1981

points, greater than the rest of the direct current component of a Sequence of channel bits, the blocks of which have separating bits on average, but distributed in 2-2-2-6 dits.

It should be noted that the described time sequences of functions and associated states of the method can be implemented in universal sequential logic circuits, as with commercially available microprocessors associated memories and associated peripheral devices. A flow chart of such an implementation is shown in FIG. 3. About the names of the blocks, explaining the functions and states of the coding method in time series include the following explanatory texts. The reference symbol is in column A and the designation of the geometric block in column B and in column C the explanatory text for the relevant geometric block indicated.

DSV i = 0 acc.

i: = 0

BD.

BI. (BD.) Χ ^v x '

JS = O

The digital sum value (DSV) of the previous one Blocks of channel bits received on Aiil'aiig of the procedure has the value zero. The first data word BD is given the number i = 0. It continues with the geometric one Block 2;

The block of data bits of m bits with the number i is selected from a memory. It continues with the geometric one Block 35

The block of data bits with the number · i (BD.) Is converted by means of a table stored in the memory into a block of information bits of η bits (BI.); the process continues with the geometric block k. A parameter j is initialized to a value 0; the parameter j is the number of one of the q blocks of channel bits of n .. + n _o bits, which may be considered for transmission or recording; it will go-

"Ν" β

PHQ 80.007

12-6-1981

5 j-i Q? driven with the geometric block 5; The parameter j is increased by 1; it follows 6th the geometric block 6. ¥ enn of all Q possible blocks channel 5 bits determines the relevant parameters are, "the process continues, by the geometric block 13 be is drawn. This is with the geometric j -. Block 6 with the connection N indicated. 10 BC: BI. + BS ^J If j is 4 Q, the process is continued i ^X drive through the geometric block 7 7th is specified; The j possible block of channel bits BC. will formed by the fact that the Informa 15th DSV ^J =? tion bits BI. with the j combination of Blocks separating bits BS is added; it follows 8th the geometric block 8; > k ^J ?
Max The DSW of the j. possible blocks of channel bits is determined; it continues with that 20th 9 geometric block 9; It is tested whether the j. possible block Channel bits when joining together with the previous block channel bits BC. the Requirement of the k-limitation fulfilled. ¥ ird 25th If this requirement is met, then proceed driven with the process caused by the geometric block 10 is indicated (ver bond Ν). Will not meet this requirement <d ^ '?
mxn is fulfilled, the previous one continues 30th passage that goes through the geometric block 11 O is indicated (compound Y). It is tested whether the j. possible block Channel bits when joining together with the previous block channel bits BC. the 35 D-limitation requirement met. Will if this requirement is met, it will be continued proceed with the process indicated by the geo metric block 12 is specified (Ver—

PHQ 80.007

12-6-1981

11

12th

DSV ^{VJ /} : = Max

DSC

acc

DSV

acc

^q (ι)

DSW ^V ''

16

BC

DSW: = DSW acc

(1) binding Ν). Will this. requirement not fulfilled, the process that is indicated by the geometric block 11 is also continued (Compound Y);

The DSW of the j. Blocks channel bits becomes such a high value; (Max) grants that this block can definitely not be chosen; the geometric block 12 follows;
The DSW of the j. Blocks channel bits (^ 'becomes the stored DS ¥ (DSW)

acc

of the previous blocks channel bits added to obtain a new stored value of the DSW (DSW ^ ³ ' ); the geometric block 5 follows; The minimum value of the DSW of the q possible blocks of channel bits is determined; it turns out that this is the DSW of the 1st block channel bits. It continues with the geometric block ^ k ',

The 1st block channel bits is selected from the q possible blocks; it will proceeded to the geometrical block 15;

The stored value of the DSW (DSW)

acc

becomes the stored value of the dsw of the selected 1st block information bits equalized; the geometric block 16 follows;

The number of the blocks of data and information bits is increased by 1. The process continues with geometric block 2; dor /.yklun mm, ίΙητπιπ 1 r .. will run through i'Ur the following, den (i + i). Block of data bits.

PHQ 80.007 I? 95 12-6-198I

The flowchart dividing the above is applied to the exemplary embodiment according to FIG. 1. The following apply to the exemplary embodiment according to FIG. 2, taking into account the changes already described, corresponding flow

In order to be able to make a difference between the information bits and the separating bits when demodulating the transmitted or recorded stream of channel bits, are in the stream of channel bits blocks (n + n,) synchronization bits recorded, namely n "synchronization information bits and n. synchronization separation bits. For example, after a certain number of blocks of information and separating bits, a block of synchronization bits inserted .. After this word has been detected, it can then be clearly determined at which bit positions information bits and at which bit positions separating bits are present. It must therefore be avoided that the synchronization word can be imitated by certain Bitfo.lgen in the information and separator blocks. This can include, for example a unique block of synchronization bits, i.e. not occurring in information and separating bit sequences to get voted. Consequences that do not meet the requirement of the d-limit or meet the k-limitation are less interesting because the information density or the self- clocking properties are then impaired. Within however, the set of sequences that meet the requirements of the (d, k) -limiting is very limited.

A different way is therefore suggested. The block of synchronization bits has, for example, at least twice in direct succession Sequence between two consecutive bits of the Type "1" has bits of type "0". Preferably s is equal to k. In Fig. 4, a block is synchronization bits SYN specified. The block contains a sequence 10000000000 (a 1 followed by 10 zeros), which is designated with SYNP or SYNP. This sequence can also occur in the stream of channel bits,

■ * · * · β α ο «. m _{% o Λ}

"*« ** · «Often ββ. _{Β ο}

■% 00 _& β » _β

PHQ 80.007> β "φ" *) 12-6-19H1

for sequences with k = 10. In order to avoid that the sequence occurs twice in direct succession outside the synchronization bits block, the first display signal is suppressed if the sum of the number of separating bits and the number of immediately consecutive information bits of type "0" that immediately correspond to a bit of type "1 ", which last-mentioned bit forms part of the block separating bits, is equal to k and also equal to the sum of the number of immediately consecutive information bits of the type" 0 "which follow the mentioned bit of the type" 1 "of the block of separating bits , is equal to. The other way already mentioned would be to use a sequence 100000000000 (a 1 followed by 11 zeros) twice. The block of synchronization bits also has a block of synchronization separation bits. The function of the blocks of separating bits corresponds to the above-described function of the block of separating bits between the blocks of information bits. (Therefore, they are used to meet the requirements of the (d _; k) limitation and the restricted DC component). The measures that have been taken to prevent the synchronization pattern from being imitated in the sequence of channel bits by occurring twice in immediate succession also prevent this pattern from occurring three times before or after the block of synchronization bits. The method described above, which is also referred to as modulating or coding, is greatly simplified in the opposite direction, that is to say during demodulation or decoding. The restriction of the direct current component has been achieved without influencing the blocks of information bits, so that the information in the separating blocks is irrelevant for demodulation. Furthermore, the choice made by the modulator as to which m-bit long block of data bits is assigned to which η-bit long block of information bits is important not only for the modulator but also for the demodulator. The complexity of the demodulator depends on this choice. In magnetic recording systems, the complexity of the

PHQ 80.007 # 9 2M 12-6-1981

Modulator and demodulator of equal importance, because in general both are present in the device. In systems for optical recording, the recording medium is of the "read-only" type ("fixed value"), whereby the consumer device only needs to receive a demodulator. In the latter case it is particularly important to minimize the complexity of the demodulator, even at the expense of the intricacy of the modulator.

5 shows an embodiment of a deruoduJ fitor darren toi J ü, which demodulates from blocks of 14 information bits dLo B.LcJcke of H data bits. Flg. 5a shows the block diagram of the demodulator and FIG. 5b shows a part of the wiring schematically. The demodulator contains AND gates 17-0 up to and including 17-51, each with one or more inputs. One of the 14 bits of the blocks of information bits is fed to each of the inputs, which may be designed to be inverted. In FIG. 5h , column C. indicates how this is designed. Column 1 represents the least significant bit position C ₁

of the 1-4 bits information block, column 14 represents the most significant bit position C. j and the intermediate columns 2 up to and including 13 represent the rest of their bit positions correspondingly significant bit positions. Lines 0 up to and including 51 relate to the ranking of the AND gate, ie line 0 relates to the input format of the AND gate 17-0, line 1 relates to the input format of the AND gate 17-1 etc. A character 1 in the i column on line j means that the j. AND gate 17 at a non-inverting input the content of the i. Bit position B. is offered. A character 0 in the i. Column on row j means that the j. AND gate at an inverting input the content of the i. Bit position (C.) is offered. Therefore (line θ) an inverting input of the AND gate 17-0 is connected to the 1st bit position (C ₁ ) and a non-inverting input is connected to the 4th bit position (C.); furthermore (line 1) a non-inverting input of the AND gate 17-0 is connected to the J. bit position (C) etc.

PHQ 80.007 / W 3.5 12-6-1981

The demodulator also contains 8 OR gates 18-1 up to and including 18-8, the inputs of which are connected to the outputs of the AND gates 17-0 up to and including 17-51. In Fig. 5b is given under column A. ting how this is achieved. Column A ₁ relates to AND gate 18-1, column A “relates to AND gate 18-2 ... and column A _g relates to AND gate 18-8. A letter A in the i. Column of j. Line indicates that the output of the AND gate 17-j is connected to the input of the OR gate 18-i.

The connection for AND gates 17-50 and 17-51 has been changed as follows. An inverting output of the AND gate 17-50 and 17-51 are each with one input connected to another AND gate I9. A. Output of the OR circuit 18-4 is connected to another input of the UXD gate 19.

The outputs of the OR gates 18-1, 18-2, 18-3 and 18-5 up to and including I8-8 and an output of the AND gate 19 are each connected to an output 20-i. At this The decoded block of 8 data bits is therefore available in parallel at the output.

The demodulator according to FIG. 1 a can also be designed by means of a so-called FPLA ("field programmable logic array"), for example the Signetics bipolar FPLA of the 82S100 / 82S101 type. The table according to FIG. 5b forms the programming table for this.

The demodulator of Fig. 5 is characterized by its simplicity quite suitable for systems for optical recording of the "readonly" type.

The block of synchronization bits can be detected by means which are shown in FIG. The transmitted or read out recorded signal is an input terminal 21 is supplied. The signal lies in that NRZ-M (ark) format. This signal is sent directly to a first input of an OR gate 22 and via a delay element 23 is fed to a second input of the OR gate 22. At the output of the OR gate 22, which is connected to the input of a shift register 24, there is then a so-called

PHQ 80.007 ä * e \ L I2-6-I98I

NRZ-I signal available. The shift register contains parts, each with a tap, the number of which corresponds to the number of bits that the block of synchronization bits has. In the example already used above, the shift register must have 23 parts in order to be able to contain the sequence 10000000000100000000001. Each tap is connected to an optionally inverting input of an AND gate 25. If the synchronization sequence is present at the inputs of the AND gate 25, a signal is generated at an output 26 of this AND gate which can serve as a display signal for detecting the synchronization pattern. With the help of this signal, the stream of bits is divided into blocks of (n + n _o ) bits. These blocks of channel bits are shifted one after the other into another shift register. The most significant η bits are read out in parallel and fed to the inputs of the AND gates 17, as indicated in FIG. 5a. The least significant η bits are irrelevant for demodulation.

The coded signal is recorded, for example, on an optical recording medium. The signal has a form given by WF in Fig. Ib. The signal is applied to the recording medium in a spiral information structure. The information structure has a profile of a number of super blocks, for example of the type shown in FIG. A superblock SB. contains a block of synchronization bits SYX. which is constructed as shown in Fig. k , and a number (33 in the exemplary embodiment) blocks of channel bits of each Cn ^ n ₂ ) bits BC ₁ , BC ₂ ... BC. A channel bit of the type "1" is represented by a transition in the record carrier, for example a transition to a recess; a channel bit of the type "0" is represented on the record carrier by the absence of a transition. The spiral information track is divided into unit cells, the bit cells. These bit cells form a spatial structure on the recording medium which corresponds to a division in time (period time of only one bit) of the stream of channel bits.

PHQ 80.007 * £ 2> 12-Ö-19S1

Regardless of the content of the information and A number of peculiarities can be recognized on the recording medium. The requirement of the Ic limitation means for the carrier that the maximum abscission between two successive transitions is k + 1 bit cells amounts to. The longest depression (or non-depression) thus has a length of (k + 1) bit cells. The requirement of the d-limit means that the minimum distance between two successive transitions is d + 1.

The shortest deepening (or part between two deepening ^ then has a length of (d + 1) bit cells. Continues to occur at regular intervals a deepening with the maximum length on with a subsequent (or previous) not recessed part with the maximum length. This structure forms part of the block of synchronization bits.

In a preferred embodiment, k = 10, d = 2 and contains a superblock SB. 588 channel bit lines. Of the Superblock SB. Contains a block of synchronization bits of 27 bit cells and 33 blocks of channel bit fields of 17 each (14 + 3) channel bit cells.

A modulator, a transmission channel, for example an optical recording medium and a demodulator can together form part of a system, for example a system for converting analog information (Music, speech) into digital information recorded on an optical recording medium. The information, on this recording medium (or a Copy thereof) recorded can be reproduced by using an arrangement capable of reproducing the Type of information is suitable that is on the record carrier is fixed.

The converter contains in particular an analog / digital converter for converting the analog to be recorded Signals (music, speech) into a digital signal of a certain format (source coding). Furthermore, the Converter part oines FcIiJ orkorrolctiii-syH (, «in« nnt: h: \ l Leu. In the converter, the digital signal is converted into a format

PHQ 80.007 23 afc 12-6-198t

converted, the errors, especially when reading out of the recording medium occur, can be corrected in the arrangement for reproducing the signals.

The digital fail-safe signal is then

S towards the above-described modulator (channel coding) for converting into one that is adapted to the channel properties digital signal supplied. At the same time the synchronization pattern and the signal is brought into an appropriate frame format. The signal obtained in this way is used to generate a control signal, for example for a laser (NRZ-Mark format), with the one spiral information structure in the form of a sequence of Wells of certain lengths is attached to the recording medium.

"The recording medium or a copy thereof can are read out with an arrangement for reproducing the information bits removed from the recording medium. the To this end, the arrangement contains a demodulator, which has already been described in detail, the decoder part of the error correction system and a digital-to-analog converter for recovery a reproduction of the analog signal that is offered to the converter-d.

Claims (1)

PHQ £ 80,007 / f 12-6-1981 PATENT CLAIMS: Method for recoding a sequence of data bits into a sequence of channel bits, the sequence of data bits being divided into consecutive blocks of m data bits each and these blocks being recoded into consecutive blocks of (n ₁ + n _? ) Channel bits (n + n _? ^ M) and the blocks of channel bits each contain a block of η information bits and a block of n ~ separating bits in such a way that successive blocks of information bits are separated by only one block of separating bits each, two successive channel bits of a first type, type "1", by at least d immediately successive bits of a second type, of type "0", are separated and the number of immediately successive channel bits of the second type is at most k, identified by _f the following steps: -1- converting the blocks of data containing m bits- <£ bits in _{blocks containing n 1} bits of information bits; -2- the generation of several possible sequences of channel bits, each at least one block of information bits and one Have block separating bits and each contain the blocks of information bits, supplemented by only one of the possible bit combinations of the blocks separating bits; -3- the determination of the direct current component of each of the possible Sequences of channel bits determined in the previous step; -k- for each of the possible sequences of channel bits the determination of the sum of the number of separating bits and the number of immediately consecutive information bits of the type "0" which immediately precedes a bit of the type "1", and the sum of the, number, which follows a bit of the type "1", which forms part of one of the blocks separating bits, and the sum of the number of separating bits and the number of immediately successive information PHQ 80.007 "& $% 12-6-1981 mntioiiFibl hs of dom type "0", ie every block of separating bits immediately precedes and follows; -5- the generation of a first display signal for the Values of the sums determined in the previous step are greater than d and at most equal to k; -6- selecting the sequence of channel bits that make up the direct current component minimized, from the sequences of channel bits at which the first display signal was generated. 2. Method according to claim 1, characterized in that that the fifth step also has the following substep: -5a- the suppression of the first display signal for that sequence of channel bits for which those in the fourth Step determined sum of the number of separating bits and the number of information bits immediately following one another of type "0" which immediately precedes a bit of type "1" of the block separating bits, equal to the sum of the number of separating bits and the number immediately determined in the fourth step successive information bits of the type "0" which immediately follows a bit of type "1" of the block separating bits and is equal to s; and the procedure further comprises the following steps: - 7- arranging a number of blocks of (n .. + n_) channel bits in immediately successive frames of ρ each Blocks;
-8- the insertion of a block of synchronization channel bits between two consecutive frames, the block of synchronization channel bits having a specific block of η synchronization information bits and this block having at least two immediately consecutive a sequence that is between two consecutive bits of the type "1" s bits of of the type "0" and furthermore has a block of n ^ synchronization separating bits and this block separating bits is determined by performing steps -2- up to and including -G- with respect to the block synchronization channel bits. PHQ 80.007 -26 3 12-6-1981 3. Method according to claim 2, characterized in that s = k. 4. The method according to any one of the "preceding claims, characterized in that the sixth step further has the following substeps: the determination of the stored direct current component of the preceding blocks of channel bits; - Determining the absolute value of the sum of the stored direct current component and the direct current component of each the sequences of channel bits that resulted in the first display signal. 5. Method according to one of the preceding claims, characterized in that the sequence of channel bits has four blocks of information bits of η bits each and four blocks of separating bits, that three blocks of separating bits have a first length n_ 'and one block has a length n _o " and that η " y η .. · is. 6. The method according to claim 5, characterized in that n ₁ = i4, η '= 2, n "" = 6 and m = 8. 7. The method according to any one of the preceding claims 1 to k, characterized in that the sequence of channel bits has a block of information bits of n bits and a block of separating bits of n bits. 8. The method according to claim 7 »characterized in that η = 14, n ₂ = 3" and m = 8. 9. The method according to any one of claims 1 - k, characterized in that the sequence of channel bits is formed by at least two blocks of channel bits and that adjacent sequences of channel bits relate to at least one block of channel bits together. 10. Demodulator for decoding the corresponding, the Method according to one of Claims 2 to 9 recoded Channel bits, characterized in that the demodulator the has the following means; - means for detecting the synchronization pattern; - Means for dividing the sequence of channel bits into blocks of (n + n ") channel bits each; - Means for separating the blocks of η information bits PHQ 80.007 ^ f M 12-6-1981 by don TJ, Ionic β η by rig Troimbibs; - Means for converting a block of n .. information bits into a block of m data bits. 11. Demodulator according to claim 10, characterized g indicates that the means for converting have AND gates, each with inputs for the parallel supply of the information bits, those from at least one specific bit position of the block originate from information bits, are provided, that the means continue to have OR gates whose inputs are connected (in a certain way) to the outputs of the AND gates and their output in parallel with the emit decoded m data bits. > 12. Record carrier with an information structure with sequences of channel bit cells that each contain a bit whose value is due to a level transition or a missing one Level transition is shown at the beginning of the bit cell, characterized in that the maximum distance between two successive level transitions equal in length of (k + 1) bit cells is that the minimum distance between two successive level transitions is equal the length of (d + 1) bit cells is that at most sequences of twice the maximum distance of (k + i) bit cells occur and that these sequences form part of a synchronization sequence. 13. Record carrier according to claim 12, characterized in that k = 10 and d = 2 and that the record carrier between two successive sequences with the maximum spacing has a frame with 561 channel bit cells, which contains 33 blocks of IJ channel bit cells each, and that the synchronization sequence has 27 channel bit cells. 14. Modulator for performing the method for Coding of a series of binary data bits into a series of binary channel bits according to one of Claims 1 to 9. 15. converter with a modulator according to claim lh. 16. Arrangement for reproducing the one transmission channel, in particular from a recording medium Information bits with a demodulator according to claim PHQ 80.007 10 or 20 25 30 ft * · «t» 4 * 9 > · »Ο« »ο Oc 12-6-1981 35