DE3049441A1 - Channel adaptor for handshake interface - is between data processors and avoids interrupts whilst preserving synchronisation - Google Patents

Abstract

The channel adaptor has two controls (2,8) between every two processors (1,11). The controls are connected together via their transfer input lines (STROBE) (4,9) and their ready-to-receive output lines (READY) (3,10) such that the transfer input line (4) of one control (2) is connected to the ready-to-receive output line (10) of the other control (8), and likewise for the remaining two lines (8,9). Each control comprises an inverter and a NAND-gate. The inverter's input is connected to the release signal output of the processor and its output to one input of the NAND-gate. The NAND-gate's second input is connected to the transfer input line and its output to the wait input of the processor.

Description

Description:

Channel adapter arrangement for the mutual connection of data processing processors, preferably via handshake interface The invention relates to a channel adapter arrangement for the mutual connection of data processing processors via their input / output channels, preferably via the handshake interface a plurality of ports, each with an input / output channel of one processor associated with it is connected by a plurality of processors, with a plurality from the connections associated control devices and a central unit and with a majority of external send / receive registers, preferably with tristate outputs as well as with connection circuits with each other for the optional production of various Data transmission links between the ports.

Such a channel adapter arrangement is described in DE-OS 28 31 261 has become known that relating to the connection of processors or data processing systems further publications and patents on the prior art via its I / O channels Technology contains.

With the usual data transmission, preferably via a handshake interface, the following protocol is adhered to: In the output mode, there is an output cycle started by an output command from the central processing unit. The write signal from the Central unit stores the data from the data bus in the output register of the addressed Channel. The write signal thus converts the ready flag of the status register thus indicating that the data is available. The ready message (READY) remains active until it is activated by a positive edge via the takeover input line (STROBE) has been deactivated and activated again; this will use the STROBE line indicates that the data has been accepted by the peripheral device. The positive edge of the STROBE signal generates an interrupt if this is allowed is.

In the input mode, when the STROBE line goes low, the Read data into the input register of the addressed channel. The next rising edge of the STROBE signal generates an interrupt if this is permitted is.

The ready message input (READY) is reset to indicate that that the input register is full and no more data can be accepted can. The central processing unit must therefore read the register in order to deal with the positive Edge of the read signal (REXC) to set the READY line.

Now two input / output channels can be combined to form a transmission link are connected by connecting the data lines together and the Handshake control signals are wired as follows: Channel adapter 1 to channel adapter 2 READY output is inverted and applied to STROBE input.

STROBE input is connected to the inverted READY output.

In this case, the software must be designed in such a way that an interrupt the writing microprocessor writes a new data byte into its channel adapter and the reading microprocessor reads a data byte from its channel adapter and processes it further.

The disadvantage of this technique is that synchronization on the transmission path is only possible via interrupt. at the Data transmission of many consecutive bytes, e.g. a text, must therefore an interrupt is answered after each byte and an interrupt routine is executed. Such interrupt routines naturally take time and are particularly critical in systems with distributed intelligence that are used for word processing, because with these the data transfers take up a considerable part of the system time to take. An interrupt could also be forbidden, but then it would be at random read and write the data, which is at best possible with completely identical types were. In any case, the system would become uncontrolled after a certain period of time.

The invention is based on the object of a channel adapter arrangement of the type mentioned at the outset to avoid interrupts and still achieve synchronization between processors.

The solution to this problem is that according to the invention between the two processors each have two control devices via their takeover input lines (STROBE) and their ready message output lines (READY) are connected to one another, such that the takeover input line of a control device with the Completion message output line of the other control device and the completion message output line the former is connected to the takeover input line of the second control device are.

The invention has the salient advantage of being essential with it increased transfer speeds when transferring large amounts of data of bytes, e.g. with word processing is possible. The synchronization is also running automatically from, whereby it is also possible to transfer data between different Exchange processor types. Furthermore, synchronization is advantageous even when exchanging data between processors at different speeds possible (different processors) or with the same processors with different Clock frequency. In addition, the software is simplified.

In a further embodiment of the invention, the control device consist of an inverter and a NAND gate, the input of the inverter to the enable signal output (rr or the processor and the output of the inverter are placed on one input of the NAND gate, the second input of which is the takeover input line and is thus the ready message output line of the other control device and the output of the NAND element is connected to the waiting input (WA-FT) of the processor and that the release signal output of the processor is simultaneously the ready message output line the control device and thus the takeover input line of the other control device forms.

In a further embodiment of the invention, the release signal output (#) of the processor must be applied to one input of two NOR elements, their other inputs with the read output (READ) or write output (WRITE) of the Processor are connected, the outputs of the NOR gates each to the activation inputs (em) the external send / receive register can be placed.

An example of the invention is shown in the drawing and subsequently described. 1 shows a block diagram with the READY and STROBE lines of the two control devices with each other connected crosswise and FIG. 2 shows an exemplary embodiment of the control device.

The channel adapter assembly shown in Figures 1 and 2 consists of for example two processors 1 and 11, which have different lines, for example are each connected to a control device 2, 8 via #MT>, WRITE, READ. the Ready message output line 3 (READY line) of the control device 2 is with the Takeover input line 9 (STROBE line) of the other control device 8, the Ready message output line 10 of the latter control device 8 is with the Takeover input line 4 (STROBE line) of the first-mentioned control device 2 connected. Furthermore, further output lines lead from the control devices 2, 8 to external send / receive registers 5, 6, 12, 13. The external send / receive registers 5, 6, 12, 13 are each via a data bus 7, 14 with the data bus of the associated Microprocessors connected; the external send / receive registers 5, 6, 12, 13 connected to one another by means of a data bus.

The mode of operation of the circuit shown is as follows: In the output mode an output cycle is triggered by a write command from the central unit in the transmit register, for example in the transmission register 5 started. If the STROBE input of the Control device 2 is not active, i.e. high, the central unit is via the WAIF input stopped. The READY output goes low and remains in this state, until a negative edge of the STROBE input of the control device 2 indicates that the data was taken over from the other processor. At this point also will the WAIT line of processor 1 inactive and the processor 1 can keep walking.

Entry mode: When the central unit tries to enter a receive register to read and there is no data, then the central unit will over the WAIT input stopped. The STROBE input becomes active (low) and the processor is stopped, then the hold state is canceled and simultaneously with the Rl.A!) Y signal angfE indicates that the data has been accepted. The STROBE input now becomes active (low), although the processor has not yet tried to transfer the data to read, the READY output remains high, i.e. inactive, to allow the writing To indicate to the processor that the data has not yet been accepted. As soon as then the receive register has been read, READY goes low to indicate that the data has been accepted to display. If STROBE is inactive and an attempt is made to read the receive register, then not only is the processor stopped, the READY line is also activated, to avoid unnecessarily stopping the writing processor.

This technique can be achieved simply by giving the handshake signals READY and STROBE of the two control devices are cross-linked will. Inversion is not necessary.

2 shows the two control units in an exemplary embodiment and their connection with each other via the cross-connection of their handshake signals READY and STROBE. The Cl: output of the microprocessor is connected to an input 14 of a Inverter 15 placed, the output of which is placed on an input 17 of a NAND gate 16 is.

The second input of this NAND gate 16 forms the STROBE line 18, which are cross-connected to the line 20 of the other control device is. The output 19 of the NAND gate 16 is on the WAIT input of the microprocessor placed. At the same time, the processor's CE output is on the READY line 25 the first control device placed, the READY line 25 crossed with the STROB # E line 26 is connected to the second control unit; the STRBE: line 26 forms one input of the NAND element 21 of the other control device, the second input of this NAND gate 21 being the output of the inverter 22.

At the same time, the output of the processor is always on the one Input of two NOR gates 23, 24 placed, the other inputs of these NOR gates connected to READ and WRITE of the processor. The outputs of the NOR gates 23, 24 lead to the activation inputs TS of the external send / receive registers, which preferably have tristate outputs. The mode of action in the output like in the input mode corresponds to the mode of operation shown above for FIG. 1.

Of course, the invention is not limited to bytes, but can can be implemented with any data word length.

Claims (3)

Claims: 1S channel adapter arrangement for mutual connection from data processing processors via their input / output channels, preferably via handshake interface, with a plurality of connections, each with an input / output channel of a processor assigned to it from a plurality of processors is connected to a plurality of control devices associated with the connections and a central unit and with a majority of external send / receive registers, preferably with tri-state outputs and with interconnection circuits for the optional establishment of various data transmission connections between the connections, characterized in that the two processors (1, 11) each have two control devices (2, 8) via their takeover input lines (STROBE) (4, 9) and their ready message output lines (READY) (3, 10) with each other are connected, such that the takeover input line (4) of the one control device (2) with the ready message output line (10) of the other control device (8) and the completion message output line (3) of the former with the takeover input line (9) of the second control device (8) are connected. 2. Channel adapter arrangement according to claim 1, characterized in that that the control device consists of an inverter (15, 22) and a NAND gate (16, 21), the input (14) of the inverter (15) being connected to the enable signal output (# or C§) of the processor and the output of the inverter on an input (17) of the NAND gate (16), the second input (18) of which is the takeover input line and thus the ready message output line (20) the other control device and the output (19) of the NAND gate (16) with the waiting input (WAIT-) des Processor is connected and the enable signal output of the processor at the same time the completion message output line (25) of the control device and thus the takeover input line (26) of the other control device forms. 3. Channel adapter arrangement according to claim 2, characterized in that that the release signal output (# or CS) of the processor in each case to the one input two NOR elements (23, 24) is placed, the other inputs to the read output (READ) or write output (WRIFE) of the processor are connected, whereby the outputs of the NOR elements to the activation inputs (S) of the external send / receive register (5, 6, 12, 13) are placed.