DE29621837U1 - Carrier element for semiconductor chips - Google Patents
Carrier element for semiconductor chipsInfo
- Publication number
- DE29621837U1 DE29621837U1 DE29621837U DE29621837U DE29621837U1 DE 29621837 U1 DE29621837 U1 DE 29621837U1 DE 29621837 U DE29621837 U DE 29621837U DE 29621837 U DE29621837 U DE 29621837U DE 29621837 U1 DE29621837 U1 DE 29621837U1
- Authority
- DE
- Germany
- Prior art keywords
- stiffening
- substrate
- chip
- film
- carrier element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07745—Mounting details of integrated circuit chips
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Theoretical Computer Science (AREA)
- Die Bonding (AREA)
- Bipolar Transistors (AREA)
Description
Trägerelement für Halbleiterchips
5Carrier element for semiconductor chips
5
Bei heutigen Chipkarten werden die Halbleiterchips mittels eines zumeist mit einem nicht-leitenden, flexiblen Substrat gebildeten Trägerelements in die üblicherweise aus Kunststoff bestehende Karte eingebracht. Auf dem Trägerelement ist nicht nur der Halbleiterchip sondern es sind auch die Kontaktflächen, mit denen der Halbleiterchip von einem Lesegerät kontaktiert werden kann, angeordnet. Hierzu wird üblicherweise eine oberflächenveredelte Kupferfolie auf das nicht-leitende Substrat laminiert und beispielsweise durch Ätzen strukturiert. In das nicht-leitende Substrat werden vor dem Laminieren Löcher gestanzt, durch die hindurch der Chip beispielsweise mittels Drähte in Wire-Bond-Technik mit den Kontaktflächen elektrisch leitend verbunden werden kann. Der Halbleiterchip und die Drähte werden dann durch eine schützende Vergußmasse abgedeckt.In today's chip cards, the semiconductor chips are inserted into the card, usually made of plastic, using a carrier element that is usually made of a non-conductive, flexible substrate. The carrier element not only houses the semiconductor chip, but also the contact surfaces with which the semiconductor chip can be contacted by a reader. To do this, a surface-treated copper foil is usually laminated onto the non-conductive substrate and structured, for example, by etching. Before lamination, holes are punched into the non-conductive substrate through which the chip can be electrically connected to the contact surfaces, for example using wires in wire bonding technology. The semiconductor chip and the wires are then covered with a protective potting compound.
Die Chipkarten müssen bestimmte, durch die Anwender vorgegebene Biegebelastungen bestehen können. Die hierbei auftretenden Biegekräfte müssen jedoch vom Chip ferngehalten werden, da dieser wesentlich spröder als das Kartenmaterial ist. Dies trifft insbesondere für Chips zu, die größer als etwa 10 mm2 sind. Aus der EP 0 484 353 Bl ist es bekannt, hierzu auf dem flexiblen Substrat einen Versteifungsrahmen vorzusehen, der eine wesentlich höhere Biegesteifigkeit aufweist als das fle-0 xible Trägersubstrat.The chip cards must be able to withstand certain bending loads specified by the user. However, the bending forces that occur must be kept away from the chip, as the chip is much more brittle than the card material. This applies in particular to chips that are larger than about 10 mm 2 . From EP 0 484 353 B1 it is known to provide a stiffening frame on the flexible substrate, which has a much higher bending stiffness than the flexible carrier substrate.
Die Figur 4 zeigt eine Ausführungsform gemäß der EP 0 484 353 Bl. Das nicht-leitende, flexible Trägersubstrat 1 ist mit Ausnehmungen 2 versehen. Eine metallische Folie 3 ist auf das Substrat 1 mittels eines Klebers 4 laminiert. Die metallische Folie 3 ist in durch Rillen 5 voneinander elektrisch isolierte Kontaktflächen strukturiert. Ein Halbleiterchip 6 ist aufFigure 4 shows an embodiment according to EP 0 484 353 Bl. The non-conductive, flexible carrier substrate 1 is provided with recesses 2. A metallic foil 3 is laminated to the substrate 1 by means of an adhesive 4. The metallic foil 3 is structured into contact surfaces that are electrically insulated from one another by grooves 5. A semiconductor chip 6 is on
GR 96 G 2608 DEGR 96 G 2608 EN
·· #··· #·
ft * · »*ft * · »*
das Substrat 1 geklebt und mittels Drähte 7 mit den Kontaktflächen 3 elektrisch verbunden. Zur Versteifung des flexiblen Substrates 1 ist ein Versteifungsring 8 auf das Substrat 1 geklebt. Das Innere des Versteifungsringes 8 ist mit einer Vergußmasse 9 gefüllt, um den Chip &bgr; und die Drähte 7 zu schützen.the substrate 1 is glued and electrically connected to the contact surfaces 3 by means of wires 7. To stiffen the flexible substrate 1, a stiffening ring 8 is glued to the substrate 1. The interior of the stiffening ring 8 is filled with a potting compound 9 to protect the chip β and the wires 7.
Das Aufbringen des Versteifungsrings ist problematisch, da relativ hohe Lagetoleranzen vorgegeben sind und außerdem spezielle, aufwendige Werkzeuge hierfür notwendig sind. Insgesamt ergibt sich eine sehr schwierige und aufwendige Prozeßführung. Außerdem wird durch den bekannten Versteifungsring die zur Klebung des Trägerelementes in die Karte nötige Fläche eingeschränkt.Applying the stiffening ring is problematic because relatively high positional tolerances are specified and special, complex tools are required for this. Overall, the process is very difficult and complex. In addition, the known stiffening ring limits the area required to glue the carrier element into the card.
Die Aufgabe der Erfindung ist es daher, ein Trägerelement anzugeben, das einerseits eine genügend große Biegesteifigkeit aufweist und andererseits einfach herzustellen ist.The object of the invention is therefore to provide a carrier element which, on the one hand, has sufficiently high flexural rigidity and, on the other hand, is easy to manufacture.
0 Die Aufgabe wird durch ein Trägerelement gemäß dem Anspruch 1 gelöst. Vorteilhafte Weiterbildungen sind in den Unteransprüchen angegeben.0 The object is achieved by a carrier element according to claim 1. Advantageous further developments are specified in the subclaims.
Die erfindungsgemäß ausgebildete Versteifungsfolie hat den Vorteil, daß zu ihrer Herstellung und Weiterverarbeitung dieselben oder ähnliche Verfahrensschritte durchgeführt werden wie bei der Herstellung des Trägersubstrates oder des bekannten Trägerelementes. Dies sind Stanz- bzw. Laminierverfahrensschritte. Da die Versteifungsfolie außerdem dieselbe Au-0 ßenabmessung hat wie das Trägerelement, können zum Laminieren dieselben Maschinen benutzt werden wie zum Laminieren der die Kontaktflächen bildenden Kupferfolie.The stiffening foil designed according to the invention has the advantage that the same or similar process steps are carried out for its production and further processing as for the production of the carrier substrate or the known carrier element. These are punching or laminating process steps. Since the stiffening foil also has the same external dimensions as the carrier element, the same machines can be used for laminating as for laminating the copper foil forming the contact surfaces.
Die Trägerelemente werden normalerweise in einem sehr langen 5 Band gefertigt, wobei mehrere Trägerelemente sogar nebeneinander liegen können. Das Band weist an seinen Rändern Perforationen auf, mittels derer es in der Fertigungsmaschine wei-The carrier elements are normally manufactured in a very long 5 strip, whereby several carrier elements can even be placed next to each other. The strip has perforations on its edges, which allow it to be further guided in the production machine.
GR 96 G 2608 DE . ..GR 96 G 2608 EN . ..
terbefordert werden kann. Wenn auch die Versteifungsfolie
diese Löcher aufweist, kann sie in gleicher Weise wie das flexible Trägersubstrat oder die Kontaktflächenfolie befördert
und verarbeitet werden.
5If the stiffening film also has these holes, it can be conveyed and processed in the same way as the flexible carrier substrate or the contact surface film.
5
Da der durch Tiefziehen und Stanzen entstandene Rahmen entlang des Randes der Ausnehmung in der Versteifungsfolie nur dieselbe Dicke hat wie die Kupferfolie selbst, bleibt im Bereich außerhalb dieses Rahmens genügend Platz für einen KIeber, um das Trägerelement in einer Karte befestigen zu können. Die Dicke der Versteifungsfolie kann abhängig von der gewünschten Gesamtbiegesteifigkeit sowie den Materialeigenschaften der verwendeten Folie gewählt werden.Since the frame created by deep drawing and punching along the edge of the recess in the stiffening foil is only the same thickness as the copper foil itself, there is enough space outside this frame for an adhesive to be able to attach the carrier element to a card. The thickness of the stiffening foil can be selected depending on the desired overall bending stiffness and the material properties of the foil used.
Die Erfindung wird nachfolgend anhand eines Ausführungsbeispieles mit Hilfe von Figuren näher erläutert. Dabei zeigenThe invention is explained in more detail below using an embodiment with the aid of figures.
Figuren die Verfahrensschritte zur Herstellung der erfin-Ia-Id dungsgemäßen Versteifungsfolie sowie eine Drauf-Figures show the process steps for producing the stiffening foil according to the invention and a top view.
0 sieht der fertigen Folie,0 looks like the finished slide,
Figuren das flexible Trägersubstrat, die Versteifungsfolie 2a-2c sowie die Verbindung dieser beiden Teile,
Figur 3 einen Querschnitt durch ein erfindungsgemäßes Trägerelement
und
Figur 4 ein Trägerelement gemäß dem Stand der Technik.Figures the flexible carrier substrate, the stiffening foil 2a-2c and the connection of these two parts, Figure 3 a cross section through a carrier element according to the invention and
Figure 4 shows a carrier element according to the prior art.
In der Figur la ist der Querschnitt durch eine auf die entsprechende Dicke gewalzte metallische Versteifungsfolie dargestellt. In der Figur Ib sind die durch einen Tiefziehvor-0 gang entstandenen Wannen 11 gezeigt. In einem Stanzvorgang werden die Böden der Wannen 11 entfernt, so daß lediglich die Wände der Wannen 11 als Rahmen 12, die einstückig mit der Versteifungsfolie 10 verbunden sind und entlang des Randes der durch die vormaligen Wannen 11 definierten Ausnehmung in der Folie verlaufen, stehenbleiben.Figure la shows the cross-section through a metallic stiffening foil rolled to the appropriate thickness. Figure lb shows the troughs 11 created by a deep-drawing process. In a punching process, the bottoms of the troughs 11 are removed so that only the walls of the troughs 11 remain as frames 12, which are integrally connected to the stiffening foil 10 and run along the edge of the recess in the foil defined by the former troughs 11.
GR. 96 G 2608 DESIZE 96 G 2608 DE
In Weiterbildung der Erfindung kann nur ein Teil des Wannenbodens ausgestanzt werden, um durch die verbleibenden, senkrecht
zur Wannenwand 12 verlaufenden Stege 17 eine zusätzliche Versteifung zu erzielen.
5In a further development of the invention, only a part of the tub bottom can be punched out in order to achieve additional stiffening by the remaining webs 17 running perpendicular to the tub wall 12.
5
Die Figur Id zeigt eine Draufsicht auf eine erfindungsgemäße Versteifungsfolie 10, die als langes Band ausgebildet ist. Entlang der beiden Ränder des Bandes sind Perforierungen 13 angebracht, die einen Weitertransport des Bandes mittels Zahnrädern erlauben. Die Folie 10 weist Ausnehmungen 14 auf, entlang deren Ränder die Rahmen 12 verlaufen. Strichliert ist der Schnitt dargestellt, der die Darstellung der Figur Ic bildet.Figure Id shows a top view of a stiffening film 10 according to the invention, which is designed as a long strip. Perforations 13 are provided along the two edges of the strip, which allow the strip to be transported further using gears. The film 10 has recesses 14, along the edges of which the frames 12 run. The section that forms the representation in Figure Ic is shown in dashed lines.
In Figur 2b ist diese erfindungsgemäße Versteifungsfolie nochmals gezeigt. Die Figur 2a zeigt das flexible Trägersubstrat 15, das aus einem Kunststoff gebildet sein kann, wobei heutzutage üblicherweise glasfaserverstärktes Epoxidharz verwendet wird. Auch das Trägersubstrat 15 ist als langes 0 Band ausgebildet und weist an seinen Rändern Perforierungen 13 zum Weitertransport und exakten Positionieren bei Weiterverarbeitungen auf. Das Trägersubstrat 15 weist Stanzungen auf, in die ein nicht dargestellter Halbleiterchip eingesetzt und durch die hindurch dieser Halbleiterchip mit nicht zu erkennenden Kontaktflächen auf der Rückseite des Trägersubstrates 15 elektrisch verbunden werden kann. In der Figur2c ist schließlich die mit dem Trägersubstrat 15 verbundene Versteifungsfolie 10 dargestellt. Die Stanzungen 16 des Trägersubstrates 15 befinden sich innerhalb des einstückig mit der Versteifungsfolie 10 verbundenen Rahmens 12, so daß ein nicht dargestellter Halbleiterchip problemlos in die zentrale Ausnehmung eingesetzt werden kann und durch die peripheren Ausnehmungen im Trägersubstrat 15 mit den auf der Rückseite des Trägersubstrates vorgesehenen, nicht zu sehenden, Kontaktflächen verbunden werden kann.This stiffening film according to the invention is shown again in Figure 2b. Figure 2a shows the flexible carrier substrate 15, which can be made of a plastic, whereby nowadays glass fiber reinforced epoxy resin is usually used. The carrier substrate 15 is also designed as a long 0 strip and has perforations 13 on its edges for further transport and exact positioning during further processing. The carrier substrate 15 has punched holes into which a semiconductor chip (not shown) can be inserted and through which this semiconductor chip can be electrically connected to contact surfaces (not shown) on the back of the carrier substrate 15. Finally, Figure 2c shows the stiffening film 10 connected to the carrier substrate 15. The punchings 16 of the carrier substrate 15 are located within the frame 12, which is integrally connected to the stiffening film 10, so that a semiconductor chip (not shown) can be easily inserted into the central recess and can be connected through the peripheral recesses in the carrier substrate 15 to the contact surfaces provided on the back of the carrier substrate, which cannot be seen.
GR 96 G 2608 DE .... ·. ·. .#GR 96 G 2608 EN .... ·. ·. .#
Figur 3 zeigt einen Querschnitt durch ein aus dem Band ausgestanztes
Trägereiement. Das nicht-leitende, flexible Trägersubstrat
15 weist in diesem Fall nur periphere durch Stanzung entstandene Ausnehmungen 16 auf. Auf seiner Rückseite ist eine
metallische Folie 20, die durch Rillen 22 in Kontaktflächen
strukturiert ist mittels eines Klebers 21 laminiert. Auf das Trägersubstrat 15 ist ein Halbleiterchip 23 angeordnet,
der mittels Bonddrähte 24 durch die Ausnehmungen 16 des Trägersubstrates
15 mit den Kontaktflächen 20 verbunden ist. Auf der dem Halbleiterchip 23 tragenden Vorderseite des Trägersubstrates
15 ist die erfindungsgemäße Versteifungsfolie 10
mittels eines Klebers auflaminiert. Der Bereich innerhalb des
mit der Versteifungsfolie 10 einstückig verbundenen Rahmens
12 ist mit einer Vergußmasse 25 zum Schutz des Halbleiter-Figure 3 shows a cross-section through a carrier element punched out of the strip. The non-conductive, flexible carrier substrate
15 has in this case only peripheral recesses 16 created by punching. On its back is a metallic foil 20, which is divided into contact surfaces by grooves 22
structured is laminated by means of an adhesive 21. A semiconductor chip 23 is arranged on the carrier substrate 15,
which is passed through the recesses 16 of the carrier substrate by means of bonding wires 24
15 is connected to the contact surfaces 20. On the front side of the carrier substrate carrying the semiconductor chip 23
15 is the stiffening film 10 according to the invention
laminated using an adhesive. The area within the frame integrally connected to the stiffening film 10
12 is coated with a potting compound 25 to protect the semiconductor
chips 23 und der Bonddrähte 24 aufgefüllt.chips 23 and the bond wires 24 are filled.
Wie im Vergleich mit der Figur 4 zu sehen ist, verbleibt beim erfindungsgemäßen Trägerelement eine größere Fläche im Bereich
des Randes des Trägerelementes um dieses besser in eine 0 Plastikkarte einkleben zu können.As can be seen in comparison with Figure 4, the carrier element according to the invention leaves a larger area in the area
the edge of the carrier element in order to be able to glue it better into a 0 plastic card.
Die Figuren 1 bis 4 zeigen ein nicht-leitendes Trägersubstrat 15 bzw. 1, das eine die Kontaktflächen bildende Metallkaschierung
20 bzw. 3 aufweist. Prinzipiell ist es jedoch ebenso
möglich, ein leitendes, beispielsweise metallisches, Trägersubstrat
zu verwenden.Figures 1 to 4 show a non-conductive carrier substrate 15 or 1, which has a metal lamination forming the contact surfaces
20 or 3. In principle, however, it is also possible to use a conductive, for example metallic, carrier substrate
to use.
Außerdem ist es ebenso denkbar, für das Material der Versteifungsfolie 10 Kunststoff zu wählen. Hierbei wären auch andere 0 Herstellverfahren als Tiefziehen und Stanzen denkbar.It is also conceivable to choose plastic for the material of the stiffening film. In this case, other manufacturing processes than deep drawing and punching would also be conceivable.
Claims (6)
dadurch gekennzeichnet, daß der nicht mit der Folie (10) verbundene Rand des Rahmens (12) mit einem etwa senkrecht zum Rahmen (12) verlaufenden, einstückig mit dem Rahmen (12) ausgebildeten Steg (17) versehen ist.2. Support element according to claim 1,
characterized in that the edge of the frame (12) not connected to the film (10) is provided with a web (17) running approximately perpendicular to the frame (12) and formed integrally with the frame (12).
Priority Applications (13)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE29621837U DE29621837U1 (en) | 1996-12-16 | 1996-12-16 | Carrier element for semiconductor chips |
| CNB971955042A CN1156002C (en) | 1996-06-14 | 1997-06-10 | Carrier element for semiconductor chips |
| RU99100202/28A RU2191446C2 (en) | 1996-06-14 | 1997-06-10 | Process of manufacture of supporting element for semiconductor chips |
| PCT/DE1997/001170 WO1997048133A1 (en) | 1996-06-14 | 1997-06-10 | Carrier element for semiconductor chips |
| BR9709717A BR9709717A (en) | 1996-06-14 | 1997-06-10 | Process for the manufacture of a carrier element for semiconductor chips |
| DE59706247T DE59706247D1 (en) | 1996-06-14 | 1997-06-10 | METHOD FOR PRODUCING A SUPPORT ELEMENT FOR SEMICONDUCTOR CHIPS |
| ES97925908T ES2171948T3 (en) | 1996-06-14 | 1997-06-10 | PROCEDURE FOR THE MANUFACTURE OF A SUPPORT ELEMENT FOR SEMI-CONDUCTOR CHIPS. |
| JP50106598A JP3498800B2 (en) | 1996-06-14 | 1997-06-10 | Method for manufacturing semiconductor chip support member |
| AT97925908T ATE212752T1 (en) | 1996-06-14 | 1997-06-10 | METHOD FOR PRODUCING A SUPPORT ELEMENT FOR SEMICONDUCTOR CHIPS |
| KR1019980710238A KR100358579B1 (en) | 1996-06-14 | 1997-06-10 | Carrier element for semiconductor chips |
| UA98126594A UA42106C2 (en) | 1996-06-14 | 1997-06-10 | Method of production of bearing element for semiconductor chip |
| EP97925908A EP0904602B1 (en) | 1996-06-14 | 1997-06-10 | Method of manufacturing a carrier element for semiconductor chips |
| IN1123CA1997 IN192422B (en) | 1996-06-14 | 1997-06-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE29621837U DE29621837U1 (en) | 1996-12-16 | 1996-12-16 | Carrier element for semiconductor chips |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE29621837U1 true DE29621837U1 (en) | 1997-02-27 |
Family
ID=8033377
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE29621837U Expired - Lifetime DE29621837U1 (en) | 1996-06-14 | 1996-12-16 | Carrier element for semiconductor chips |
Country Status (1)
| Country | Link |
|---|---|
| DE (1) | DE29621837U1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997040532A3 (en) * | 1996-04-24 | 1998-02-26 | Amkor Electronics Inc | Molded flex circuit ball grid array and method of making |
| US5852870A (en) * | 1996-04-24 | 1998-12-29 | Amkor Technology, Inc. | Method of making grid array assembly |
| WO1999011106A1 (en) * | 1997-08-25 | 1999-03-04 | Telefonaktiebolaget Lm Ericsson (Publ) | A chip supporting element and use thereof |
| WO1999019832A1 (en) * | 1997-10-15 | 1999-04-22 | Siemens Aktiengesellschaft | Carrier element for a semiconductor chip for installing in chip cards |
-
1996
- 1996-12-16 DE DE29621837U patent/DE29621837U1/en not_active Expired - Lifetime
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997040532A3 (en) * | 1996-04-24 | 1998-02-26 | Amkor Electronics Inc | Molded flex circuit ball grid array and method of making |
| US5852870A (en) * | 1996-04-24 | 1998-12-29 | Amkor Technology, Inc. | Method of making grid array assembly |
| US5859475A (en) * | 1996-04-24 | 1999-01-12 | Amkor Technology, Inc. | Carrier strip and molded flex circuit ball grid array |
| US5985695A (en) * | 1996-04-24 | 1999-11-16 | Amkor Technology, Inc. | Method of making a molded flex circuit ball grid array |
| US6124637A (en) * | 1996-04-24 | 2000-09-26 | Amkor Technology, Inc. | Carrier strip and molded flex circuit ball grid array and method of making |
| US6329606B1 (en) | 1996-04-24 | 2001-12-11 | Amkor Technology, Inc. | Grid array assembly of circuit boards with singulation grooves |
| WO1999011106A1 (en) * | 1997-08-25 | 1999-03-04 | Telefonaktiebolaget Lm Ericsson (Publ) | A chip supporting element and use thereof |
| US6011692A (en) * | 1997-08-25 | 2000-01-04 | Telefonaktiebolaget Lm Ericsson | Chip supporting element |
| WO1999019832A1 (en) * | 1997-10-15 | 1999-04-22 | Siemens Aktiengesellschaft | Carrier element for a semiconductor chip for installing in chip cards |
| US6719205B1 (en) | 1997-10-15 | 2004-04-13 | Infineon Technologies Ag | Carrier element for a semiconductor chip for incorporation into smart cards |
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