DE2948120C2 - Insulating gate field effect transistor with an island-shaped semiconductor layer on an insulating substrate and method for producing such an insulating gate field effect transistor - Google Patents

Description

The invention relates to an insulating-layer field effect transistor with an island-shaped semiconductor layer which is arranged on a main surface of an insulating substrate and one facing away from this Has surface, with a source and a drain region, leaving one between them lying channel zone in the island-shaped semiconductor layer from its surface diffused so far are that they reach the main surface of the substrate, with a source electrode on the source region, a drain electrode on the drain region and a gate electrode insulated by an insulating layer above the channel zone on a first surface area parallel to the main surface of the substrate Surface of the island-shaped semiconductor layer.

The invention also relates to a method for producing such an insulating gate field effect transistor.

An insulated gate field effect transistor (IG FET) of the type mentioned above is made of, for example Electronics, May 26, 1977 issue, pages 99-105. The invention is of particular advantage applicable to an IG FET with a silicon semiconductor layer on a sapphire or spinel substrate (hereinafter abbreviated as SOS for Silicon on Sapphire or Spinel) epitaxially grown ir.t

IG FETs of the aforementioned type have recently been able to be significantly improved in terms of their performance. Particularly for circuit integration, it has become an important technique to reduce the capacitance of wiring planes each connecting transistors or the like to each other by arranging a plurality of transistors isolated from each other on an insulating substrate of high resistance. On the other hand, the capacitance of the transistors must be reduced. To this end, a method of forming the source and drain regions in a process that is self-aligning with respect to the gate has generally been proposed. But even with this so-called self-aligning process, in which a gate electrode made of polycrystalline silicon is used as a mask to form the source and drain zones, the overlap between the gate electrode and the Source and drain zones become approximately equal to the thickness of the silicon layer due to lateral diffusion if the source and drain zones are formed so deep that they extend to the connecting surface between sapphire and silicon. The capacitance caused by this overlap therefore becomes large and the dynamic performance of the transistor deteriorates. It is only necessary, the silicon single crystal layer or the

To make the semiconductor layer thin to reduce such overlap due to lateral diffusion. However, the crystal properties of a semiconductor layer depend strongly on its thickness, as long as this thickness falls below a certain level In general, reducing the thickness below this certain level is recommended a deterioration in the crystal properties and, consequently, in the performance of the transistor operating under Use of such a semiconductor layer is built, cause. Zürn example must be according to today's ι ο Technique, a silicon crystal grown on a sapphire substrate can be at least 200 nm thick, and im in general, silicon layers with a thickness of 500 nm to 1 µm are used. In addition, in the case GaAs layers grown on semi-insulating GaAs substrate limit thickness reduction with regard to zones with variable concentration of impurities, traps on the boundary layer, uniformity the thickness of an epitaxial layer, reproducibility, etc.

If, on the other hand, the source and drain regions are formed so that they, around the Reduce the overlap between the gate electrode and the source and drain zone, not down to the insulating level Substrate then becomes the capacitance of the pn junction between the lower part of these areas and the semiconductor layer is enlarged.

Since recently the realization of a transistor with a gate length of about 500 nm, the a high switching speed has become possible the above-mentioned increase in capacity must be avoided.

The invention is based on the object of providing an IG FET of the type mentioned at the outset, which has a the smallest possible overlap between the gate electrode and the source or drain zone at the same time the lowest possible capacitance of the pn junction between these zones and the semiconductor layer and easy to manufacture, especially in large numbers in integrated circuits, allows.

An insulated gate field effect transistor is used to solve this problem of the type mentioned according to the invention characterized in that the surface of the island-shaped semiconductor layer in the area of the source and drain zone next to the first surface area lying second surface area that is at a smaller distance than the first surface area run parallel to the main surface of the substrate, as well as the first and second surface areas connecting side surfaces, and that the source and drain regions through the second surface regions and the side surface regions so are diffused in that they are the main surface of the substrate below the second surface areas reach.

This has the advantage that the island-shaped semiconductor layer has a smaller thickness in the areas where the source and drain zones are diffused and the source and drain zones can therefore reach the substrate before it becomes too large due to lateral diffusion Overlap with the gate electrode has arisen, while on the other hand a sufficiently large layer thickness is available below the gate electrode for the formation of sufficiently good t> 5 crystal properties.

Since the semiconductor layer ei in terms of their crystal properties;. J thickness of 200 nm or must have more, the distance i \ of the main But hexes of the insulating substrate to the surface of the channel region and the surface should be the first parts of the source and drain regions 200 nm or to be taller. Further, when the distance between the main surface of the insulating substrate and the surface of the second parts of the source and drain regions is represented by fj, the effective range of the thickness ratio should be 3> t 1> 5 . This ratio is derived from the fact that with a view to the present state of lithography for VLSI (very large scale integration) the overlap should be about 100 nm, and that if the thickness C _{2 is} too small, the resistance to the channel zone increases becomes large, while on the other hand, if the thickness becomes too large, the effect of reducing the capacity of the overlap does not become effective.

According to a preferred embodiment of the According to the invention, the lateral surface areas have an inclined course, and that due to the diffusion the source and drain zones en '-, iandene pn junction in the semiconductor layer: bounce! to this inclined lateral surface areas.

The invention also provides a method for producing an insulated gate field effect transistor the preferred embodiment mentioned above, in which on the main surface of a The insulating substrate has a silicon layer in the form of an island, on it a gate insulating layer, on this a gate electrode layer and over this an etching mask layer are formed, the etching mask layer, Gate electrode layer and gate insulating layer selectively etched away to expose the silicon layer are, impurities in the exposed silicon layer to form the source and drain zone in such Diffused to the extent that they reach the main surface of the substrate, and on the source and Drain zone source and drain electrodes are applied. Such a method is according to the invention characterized in that the silicon layer is formed such that its surface in a (ICO) -plane runs, and that the exposed silicon layer with a selective etchant whose etching speed is greater for {100 (planes than for (i 11) planes) is, is etched to form a mesa shape of the silicon layer, so that a first surface area in the {lOOf level below the gate insulating layer, second surface areas in the {100J plane, on both sides of the first surface area and with closer than this from the main surface of the insulating substrate, as well as side surface areas in the {11 if plane, which is the first surface area connect to the second surface areas are formed.

In the following, the invention is illustrated by means of exemplary embodiments with reference to the Figures explained in more detail.

F i g. 1 and 2 each show a cross section through an IG FET in SOS construction of a conventional type;

F i g. 3A is a top plan view of a first embodiment of the present invention;

F i g. Figure 3B is a cross section taken along line P-B 'of Figure 3 . 3A in the direction of the arrows;

Figures 4 to 7 are cross-sections resulting from a sequence of Show manufacturing steps of an IG FET according to the first embodiment of the invention;

Figs. 8 through 11 are each cross sections showing a second to show fifth embodiment of the invention.

F i g. 1 and 2 show IG FETs of conventional construction in which an island is formed by a semiconductor layer of one conduction type on an insulating substrate 16, 26, in which island a source zone 14, 24 and drain zone 13, 23 each of the> Another conduction type are formed by a self-aligning method by using a gate insulating layer 12, 22 and a gate electrode 11, 21 made of polycrystalline silicon as a mask. A channel zone 15, 25 of the one conductivity type lies between the source zone and the drain zone.

In the conventional structure of FIG. 1, the depth of the pn junction is chosen to be shallow in order to reduce the capacitance of the overlap /. Between Gale electrode 11 and source and drain zones 14 and 13 / u. But as from ι; F i g. I can be seen. there is a zone of a conductivity among the zones 13 and 14, and thus the capacitance of the pn junction between the regions 14 and 13 and the zone of the one conductivity becomes large.

On the other hand, in the conventional _> n Construction of FIG. 2 the zones 23 and 24 were so shaped that they the insulating substrate 26 reach, and so the capacitance of the pn junction between zones 24 and 23 and zone 25 is strong reduced compared to the conventional type from Fig. 1, but in contrast to the conventional construction from F i g. 1, the gate overlap over the source and drain is increased.

First execution

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The F i g. 3A and 3B show a first embodiment according to the invention in which a semiconductor layer 30 of a conduction type is formed in an island shape on the main surface of an insulating substrate 36. and in this semiconductor layer 30 has a source zone 34 and a drain zone 33 each of the other conductivity type are formed by using a gate insulating layer 32 as a mask. Λ as can be seen from these figures is compared to the height f. of the first parts 34 'and 33' of FIG Source and drain zone, which lie on the channel zone 35, the thickness i2 of the second parts 34 ″ and 33 ″ of these Zones connected to wiring layers 38 and 39 are thinner. Therefore, despite the fact that these zones reach the insulating substrate, the extent of the lateral diffusion is so small that the Overlap between the source and drain zones and the gate electrode 31 is reduced and so is the Capacity is reduced. In addition, in this embodiment of the invention, since the IG FET has a Manufacturing method, as described later, the gate electrode 31 is its lateral length /, as seen in Figure 3B. narrowed compared to Insulating layer 32, and so the overlap capacity becomes even smaller.

In the IG FET shown, the length / of the gate insulating layer 32 is 1.6 μm and, since the dip gate electrode is etched away by 0.3 μm laterally in the manufacturing process, the lateral length / of the gate electrode 31 is 1.0 μm. Since the source and drain zones are diffused 0.4 μm under the M) insulating layer due to the side diffusion during their manufacture, the respective overlap between the source or drain zone and the gate electrode is 0.1 μm. Since the thickness ti of the semiconductor layer 30 is 0.6 μm, the overlap length of 0.1 μm is quite a small value. The capacity of this! G FET was 0.003 picofarads in the case of a channel width W of 4 μm. On the other hand, in the case of the IG-FET of Fig. 2 where the other conditions including the length of the gate insulating layer were kept the same, the capacitance was 0.006 picofarads. Also in the case of the IG FET of FIG. I, where the length from the end of the gate electrode to the end of the source and drain zone is 5 μm and the other conditions are kept the same, the capacitance was 0.008 to 0.013 picofarads. Therefore, good high-frequency properties can be expected from an IG FET according to the invention in comparison with conventional IG FETs. A delay line of 15.5 nsec was observed for a ring oscillator made of IG FETs of conventional design with 31 stages, while the delay time was reduced to 8.7 nsec for a smooth ring oscillator made using IG FETs according to the invention . The method for producing the ICi FF.Ts according to the first embodiment according to the invention will now be described with reference to FIGS. 4 to 7 are described.

The SOS substrate that is used in the first embodiment is a sapphire zinc crystal 36 of approximately 400 μm thickness and has a 11 lOij-Ebciu ; is bred. which is η-conductive and has a specific resistance of 100 Ωcm or greater. Πργ silicon single crystal is selectively etched by a conventional process and has the shape of an island 30. Subsequently, a suitable impurity, boron in the embodiment shown, is introduced into the island-shaped silicon layer 30 so that the average impurity concentration is approximately 3x10 ^lb atoms / cm ^! Furthermore, a silicon oxide layer 32 for use as a gate insulating layer is produced on the silicon layer 30 by thermal oxidation with a thickness of 50 nm. Then polycrystalline silicon is evaporated over the entire surface of the chip to a thickness of about 400 nm in a CVD process (chemical vapor deposition) to form a polycrystalline silicon layer 31, which is used as a gate electrode, the surface part up to one Depth of about 10 nm is oxidized to form a silicon oxide layer (shown in Fig. 4 as the lower part of the undifferentiated layer 44). A silicon nitride layer (in FIG. 4 the middle part of layer 44) is grown on the silicon oxide layer in a CVD process to a thickness of approximately 200 nm, and this silicon nitride layer is further thermally oxidized to form a silicon oxide layer (in FIG upper part of layer 44) approximately 30 nm thick on the surface of layer 44. This composite layer 44 serves as an etching mask. A schematic cross section through the semiconductor wafer produced in this way is shown in FIG. Next, the polycrystalline silicon layer 31 is patterned by using the photoresist 45 as a mask in accordance with the conventional lithography technique, ie the layer 44 and the polycrystalline silicon layer 3J are etched away one after the other -Direction of the single crystal silicon layer 30 lies In the embodiment shown, the structure was aligned within ± 1 ° with respect to the <110> direction. After these process steps, the more exposed silicon oxide layer 32 is removed by etching. The state of the flaking at this point in time is ir, F i G. 5 then an anisotropic etching of the silicon is carried out in the embodiment shown

was heated to 60 ° C ± 2 ° C Hvdrazine hydrate used. With this etchant, the etching speed is for a (100) plane of silicon approximately one hundred times as large as for a {1 11} plane and is about 1 µm / min. If silicon is etched with this etchant for about 20 seconds, the exposed Silicon layer about 300 ηm thick and the lower surface in the | 100) plane becomes parallel to the Surface of the sapphire substrate. Between this lower surface and the part that passes through the gate insulating layer 32 is covered, occurs as a result of the etching .Seitenoberfhkhe in the (III) plane. the with respect to the (100 plane is inclined by 5 <Γ 44 ', and so the silicon layer becomes the mesa type. During this period the silicon layer 31 is also polycrystalline exposed to the etchant, but in this etching process there is no dependence on crystal faces and consequently, the polycrystalline silicon layer 31 is etched away by about JOO nm from each side. This condition of the plate is shown in FIG. 6 shown.

Next, the composite layer 44 on the polycrystalline silicon layer 31 is removed by etching, and then phosphorus is introduced into the silicon layer 30 as an impurity to form source and drain regions with the aid of ion implantation at a low Fnergic of about 20 keV and an ion density · <Y. , .-. about 1 χ ΙΟ ¹⁵ atoms / cm ² . During this process, the acceleration voltage is selected so that no phosphorus can penetrate into the silicon layer 30, which is covered by the gate insulating layer 32. The impurities are also introduced into the polycrystalline silicon layer 31. In the following, the sample is subjected to a heat treatment in order to achieve a deep diffusion of the phosphorus, so that the through-diffused zones reach the main surface of the substrate under the lower surface in the | 100} plane and partly from the side surfaces in the jlllJ plane extend under the edges of the gate electrode 31. In the embodiment shown, a depth diffusion of about 0.4 μm is achieved under the influence of an oxygen atmosphere at 1000 ° C. for 30 minutes. As a result, source and drain zones have an impurity concentration of 1 χ 10 ¹⁹ atoms / cm ³ , the gate electrode has a similar impurity concentration and the overlap length between gate electrode and source or drain zone is 0.1 μίτι. A cross-sectional view of the sample at this point in time is shown in FIG. 7. A source wiring layer 38, a drain wiring layer 39 and a gate wiring layer 40 with a source zone 34 are formed with the aid of the conventional processes of vapor deposition of a silicon oxide layer 37 with the aid of CVD, etching of contact holes, vapor deposition of a conductive aluminum layer and structuring , Drain zone 33 and gate electrode 31 are connected through openings 42, 43 and 41, respectively. After that, the IG FET. as shown in FIGS. 3A and 3B, completed

Second embodiment

! Layer 85 is formed with Teiiur as: In the second embodiment in Fig.8 86 having doped therein iron of 150 μπι thickness having a resistivity of ⁴ ohm-cm or higher Ixio an n-GaAs Ieitende Sc is on an insulating or semi-insulating GaAs substrate Doping and an Störsieilenkonzentration of 3 χ 10 ^{! 5} atoms / cm ³ and a thickness of 1 μπι, a gallium oxide layer, produced by anodic oxide

tion, is used as the gate insulating layer 82, and a metal such as molybdenum, platinum, etc. is used because of its low resistivity is used as gate electrode 81. As can be seen from Fig.8, the height is the surfaces of the parts of the source zone 84 and drain zone 83, which create the connection to the wiring layer, deeper than the height of the semiconductor layer, on which the gate insulating layer is formed, and consequently the junction capacitances be reduced. In addition, despite the fact that the source and drain regions 84 and 83 can up to Surface of the insulating substrate 86 reach the overlap between the zones 83 and 84 and the Gate 81 can be decreased and consequently there is a decrease in both the junction capacitance of Source and drain as well as the capacitance due to the overlap between gate and source or gate and Drain achieved what was difficult to achieve conventionally. Also protrude in this embodiment the gate insulating layer 82 and the gate electrode 81 beyond the parts of the source and drain zones which lie on the channel zone. In this embodiment isotropic etching is used to etch the semiconductor layer and the doping of the source and drain zone thermal diffusion.

Third embodiment

A third embodiment according to FIG. 9 uses the same materials as the second embodiment. except that the gate electrode 91 is formed from polycrystalline gallium arsenide. How out 9, this embodiment similarly solves the difficulties of the prior art Manner like the first and second embodiments described above. It should be noted that in this Embodiment of the protrusion of the gate part, as it could be seen in the second embodiment. not is present and consequently i-ine further reduction of the Coupling capacitance between gate and source and between gate and drain it can be calibrated.

Fourth embodiment

In the fourth embodiment of Fig. 10, the gate electrode 71 is made of tungsten and the gate insulating layer 72 formed from silicon dioxide. The silicon single crystal layer 75, in the source and drain regions 74 and 73 are formed on a sapphire single crystal substrate having a j 1 ^ (surface, has a {100} plane as the main interface. The inclined surfaces of the regions 73 and 74, which extend towards the end of the gate insulating layer are {111 (faces, and the gate 71 is arranged so that its edges are directed parallel to the {110) direction of the silicon layer. In In this embodiment, the semiconductor layer is etched with the aid of an anisotropic etching process As can be seen from FIG. 10, in this embodiment addresses the difficulties of the prior art in a manner similar to that in FIGS previous embodiments can be solved. In addition, compared to the above-described second and third embodiments have the advantage that the fluctuations in structure are small, since the inclined side surfaces of the zones 73 and 74 are determined by the crystal structure.

Fifth embodiment

In this embodiment according to FIG. 11 has the Source or drain zone 64, which in a semiconductor

layer 65 is formed on an insulating substrate 66, a so-called niche shape, produced by lowering the surface of the gate electrode 61 and gate insulating layer 62 adjacent point and increasing again Ηργ surface! · '· ¹¹ ? at one end part for

10

same height as the canal zone. Even with one of those Arrangement of the source and drain zones can have the same effects and advantages as in the previous ones! Embodiments can be achieved.

In addition 5 sheets of drawings

Claims (5)

Patent claims: 1. Insulating-layer field effect transistor with an island-shaped semiconductor layer which is arranged on a main surface of an insulating substrate and has a surface facing away from it, with a source and a drain zone which, leaving a channel zone between them, enter the island-shaped semiconductor layer of whose surface are diffused in so far that they reach the main surface of the substrate, with a source electrode on the source zone, a drain electrode on the drain zone and a gate electrode isolated by an insulating layer above the channel zone on one to the main surface of the substrate parallel first surface area of the surface of the island-shaped semiconductor layer, characterized in that the surface of the island-shaped semiconductor layer (30) in the area of the source and drain zone (34,33) next to the first surface area lying second surface areas, which in a smaller distance (t ₂ ) as the first surface region are parallel to the main surface of the substrate (36), and have side surface regions connecting the first and second surface regions, and that the source and drain regions (34, 33) are diffused through the second surface regions and the side surface regions in such a way that they reach the main surface of the substrate (36) below the second surface areas. 2. Isolierschicht-Bvldeffek .transistor according to claim 1, characterized in that the distance (t \) between the main surface .he of the insulating substrate (36) and the first surface area of the semiconductor layer is 1.5 to 3 times greater than the distance ( tfi between the main surface of the insulating substrate (36) and the second surface areas of the semiconductor layer (30). 3. insulating layer field effect transistor according to claim 1 or 2, characterized in that the Side surface areas are inclined. 4. insulating layer field effect transistor according to claim 3, characterized in that the through the Diffusion of the source and drain zone (34,33) resulting pn junctions in the island-shaped semiconductor layer (30) essentially parallel with the inclined side surface areas run. 5. Method of manufacturing an insulated gate field effect transistor according to claim 3 or 4, wherein on the major surface of an insulating substrate a silicon layer in the form of an island, on top of it a gate insulating layer, on top of this a gate electrode layer and over this an etching mask layer, the etching mask layer, gate electrode layer are formed and gate insulating layer are selectively etched away to expose the silicon layer, Defects in the exposed silicon layer for the formation of the source and drain zones in such To the extent that they reach the main surface of the substrate, and on the source and drain zone source and drain electrodes are applied, characterized in that the silicon layer is formed in such a way that its surface runs in a (100} plane, and that the exposed silicon layer with a selective etchant, the etching speed for (100) planes is greater than for (I H (levels, for training a mesa shape of the silicon layer is etched, so that a first surface area in the (100} -plane below the gate insulating layer, second surface areas in the {100j plane, on both sides of the first surface area and at a smaller distance than this from the main surface of the insulating substrate are, as well as side surface areas in the (lll} -plane, the de-> connect the first surface area to the second surface areas, are formed.