DE2853517A1 - MULTI-LEVEL LOGIC CIRCUIT - Google Patents

Description

BLUMBÄCH · WESER E £ RCEEH · KRAMER

PATENT LAWYERS IN MUNICH AND WIESBADEN

^: · ■ ■■ -3-

Patentconsult Radeckestraße 43 8000 Munich 60 Telephone (089) 883603/883604 Telex 05-212313 Telegrams Patentconsult Patentconsult Sonnenberger Straße 43 6200 Wiesbaden Telephone (06121) 562943/561998 Telex 04-186237 Telegrams Patentconsult

Western Electric Company, Incorporated Cooper, J. A * 4-16 Broadway "" ""

New York, N.Y. 10038, U.S.A.

Multi-level logic circuit

The invention relates to a multi-stage logic circuit at least a first and a second stage, which in the are connected in series and -The following have: an output node connected between a supply voltage and a reference voltage is connected and can supply an output signal to the next following stage, a logic network that, in response to input signals, the Output node selectively connects to the reference voltage via a switch, and a load element connected between the output node and the supply voltage is switched.

A typical semiconductor circuit, such as an integrated one Logic circuit, contains an output node which, during operation, often switches to high and low voltage states (H and L) is brought. The node is connected to a reference potential, typically ground potential, via a logic network ~

Munich: R. Kramer Dipl.-Ing. . W, Weser Dipl.-Phys. Dr. rer. nat. · P. Hirsch Dlpl.-Ing. · H. P. Brehm Dipl.-Chem. Dr. phü. nst. Wiesbaden: P. G. Blumbach Dipl.-Ing. ■ P, Bergen Dipl.-Ing. Dr. jur. · G. Zwirner Dipl.-Ing. Dipl.-W.-ing.

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Werk connected, which contains a group of logically interconnected transistor switches and an active element. The network is able to ground the node depending on logical input signals (i.e. a voltage transition of H to L) when the active element is activated. The node is also connected to a supply voltage via a load element connected to raise the level of the node when the switch is off.

Typically a passive load is used in the supply circuit and a current flows through the load when the active element is switched to its switched-on state (the active element is accessed). When the load element is passive (is an impedance or an unswitched active element), the load element must have a poorer conductor than the logic network and be the active element to achieve the voltage transition from H to L, so that the speed of the circuit during the transition from L to H is limited by the low conductivity of the load element. It is common knowledge.

A frequently used solution attempt to increase the speed consists in the use of an active load that is switched in push-pull to the active element. As the exit node via the active load with the supply voltage connected (i.e., "pulled up" to its high voltage level

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is), if there is no access to the circuit, then only transitions of the output voltage need when the circuit is accessed from H to L because of the high conductivity of the logic network and the active element go faster. A disadvantage of such a circuit is that that for multi-stage circuits separate clock signals are necessary for the individual stages, so that stages further behind are not activated before the steps ahead logical operations have ended, i.e. a voltage transition from H to L or no voltage transition has taken place. Otherwise faulty transitions from H to L can occur the stages further back occur if such a signal is due to the logic output signal of the preceding stage Transition should not take place. The clock signal requirements mean additional components and result in a slower one Way of working. The invention is accordingly directed to the problem to create a multi-stage circuit in which the voltage is pulled up through the use of active load elements is removed from the access period without the need for separate clock signals for the individual stages.

To solve the problem, the invention is based on a multistage Logic circuit of the type mentioned and is characterized by a signal device for closing the switch assigned to each stage in response to the same signal and a delay device which

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early and accordingly unwanted switching on of the output node the second stage to the reference voltage before the selective Connection or non-connection of the output node of the first stage to the reference voltage is prevented.

Generally, according to the invention, inverters and / or are grounded Delay elements between the different stages of a multi-stage circuit is used so that a single clock pulse is used to activate all active elements of all stages can be in such a way that further back steps are not activated unintentionally. Pulling up the exit nodes each stage takes place in non-access intervals of the circuit using, for example, switching Load elements instead, which are operated in phase opposition to the active elements. It is important to have a multi-level Logic circuit according to the invention responds to a single clock pulse so that the improved operating speed, which is made possible by avoiding pulling-up processes during access, can be used to advantage.

Since a parasitic capacitance is always assigned to each output node in such a logic circuit, this Capacity used to advantage to keep the output node at a high voltage level during access, if it is not pulled from H to L via the logic network and the active element. Accordingly, includes a logic circuit of the type in question here an output node that

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Via an active load with a supply voltage and through an active element is connected to a reference potential via a logic network. The active load is before activation of the active element switched on. The output node is caused by the parasitic capacitance before activation of the active element brought to H and held there. Consequently, the active element, the logic network and the Load capacity the access speed depending on one single clock pulse. Since there is no transition from L to H for the Output node is necessary, higher speeds can be achieved achieve. An important feature of the invention is that the high speed that the circuit can achieve can be realized by a multi-stage arrangement in which all active elements are switched simultaneously instead of by a sequence of clock pulses. Each such stage contains one Inverter or a delay circuit to avoid premature transitions of the node from H to L in the next following level before completing the logical operation in the previous stage.

The invention is explained in more detail below with reference to the drawing described. Show it:

Fig. 1 shows the circuit diagram of a multi-stage combinatorial Logic arrangement according to the invention;

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FIG. 2 shows the circuit diagram of part of the arrangement according to FIG. 1.

1 shows an exemplary embodiment for a sequential integrated logic circuit which is arranged on a semiconductor plate 10. The circuit has a plurality of stages S .., S _{2 nn are} switched. The network and the load element are designated by 12 and 13 for the level S. The source connection of the component 15 is connected to ground and its gate connection is connected to a clock pulse source 16.

The stage Sp holds an inverter 20 having a P-channel component 21 and an N-channel component 22, their drain connections to one another are connected. The source connection of the component 21 is at the voltage Vj-m. The source connection of the component 22 is connected to a reference voltage, suitably earth. The gate connections the components 21 and 22 are connected to the node. The drains of components 21 and 22 are connected to an input of an N-channel network 25 of the stage Sp. The network 25 is connected to the drain connection of the N-channel component 15 and is in series with, for example an active load 26. This is a P-channel component, the source of which is connected to the voltage connected is.

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The gate connections of the components 13 and 26 are connected to the gate connection of component 15. In this way, the same, single clock pulse from source 16 switches P-channel components 13 and 26 in phase opposition to the N-channel component 15.

Figure 2 shows portion 40 of Figure 1 with the details of N-channel networks 12 and 25. Each of these networks includes electrically parallel paths 42 and 43 or 44 and 45 between the drain connection of the P-channel component 13 (or 26) and the drain of N-channel device 15. Path 42 includes two N-channel components 47 and 48, v / above the source connection of component 47 is connected to the drain connection of component 48. Correspondingly, paths 43, 44 and 45 contain the Components 50, 51 or 52, 53 or 54, 55. The gate connections all of the components 47, 48, 50, 51, 52, 53, 54 and 55 have each an entrance.

Let it now be the mode of operation of the circuit according to FIGS considered. An initial state is assumed for which the Component 15 is turned off and components 13 and 26 were turned on to the nodes 23 and 61 together with the to charge associated parasitic capacitances on V ™}. if the components 13 and 26 are switched off, no current flows, and the nodes 23 and 61 remain at H. Since the node 23 is on Is H, inverter 20 brings node 36 to L. If that is Component 15 is activated, the load components 13 and 26 are switched off.

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The inputs (gate connections) of the components in the N-channel networks input signals are carried, some from external sources (not shown) and some during the normal operation originate from previous stages, as the drawing shows. It is assumed that the component 15 to a is switched on at a certain point in time while the input signals are applied, and the components of the N-channel networks are activated or not activated depending on the input signals. Switching on component 15 prepares the network. Either there is an electrical path to earth via the N-channel network 12 present or not. If not, node 23 remains at H, node 36 remains at L and component 52 remains remains switched off. If there is a path, node 23 is "pulled down" (goes L), the node 36 goes to H and component 52 switches on. If to at this point in time the component 53 due to other input signals is switched on and the components 54 and 55 are switched off, the output 61 goes to L, but only depending on the function the previous stage via the inverter 20. In the absence of the inverter, the output 61 would be immediately when the Component 15 went to L. It can be seen accordingly that the multi-stage circuits according to FIGS. 1 and 2 on a single one Respond clock pulse to generate an output signal at a time determined by the pull-down speed the voltage instead of the relatively slow active load elements or the frequency of the clock pulse train is determined.

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Note that Fig. 1 is a step S ^ similar to the stages S ₁ and S _2, which contains an N-Kanäl network 79 and a P-channel load member 80 ~. The stage S ^ also has a delay circuit 81. A delay circuit is used when an inverter such as inverter 20 cannot be used due to circuit or processing requirements. The gate terminal of the load element 80 is connected to the gate terminal of the element 15 'in order to ensure an anti-phase peeling operation. In the circuit, the active element 15 ', which speaks to the element 15, is activated to actuate the "stage" S, after a delay long enough to allow the logical operations of the previous stage to be carried out to enable.

Circuits according to the invention can be made with inverters, Delay circuits or both (as shown) can be implemented. If only inverter between the stages of a multi-stage Arrangement according to the invention are used, of course only one component 15 needs to be used. One component 15 ' is used for any stage that requires a delay circuit.

The invention has been described with reference to an integrated circuit. However, such a circuit need not be used will. The invention can be used with PMOS, IMOS, CMOS, PNMOS or bipolar components, relays or even vacuum tubes can be realized.

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Claims (3)

BLUMBACH · WSSER .BERGEM · KRAMER ZWIRNER - HIRSCH - BREHM PATENT LAWYERS IN MUNICH AND WIESBADEN * OQOOI I Patentconsult Radeckestraße 43 8000 Munich 60 Telephone (089) 883603/883604 Telex 05-212313 Telegrams Pateniconsult Patentconsult Sonnenberger Straße 43 6200 Wiesbaden Telephone (06121) 562943/561998 Telex 04-186237 Telegrams Patentconsult Western Electric Company, Incorporated Cooper, J, A. 4-i6 Broadway New York, N.Y. 10038, U.S.A. Claims Multi-stage logic circuit (10) with at least a first and a second stage (S ₁ , Sp), which are connected in series in the order mentioned and each have the following: an output node (23, 6i) connected between a supply voltage (VjyrO and a reference voltage switched and provide an output signal to the next following stage can, a logic network (12, 25) which, in response to input signals, selectively connects the output node to the reference voltage via a switch (15), and a load element (13, 26) which is connected between the output node and the supply voltage, characterized by a signal device (16) for closing the _{switch (15) assigned to each stage (S 1} , S ₂ ) in response to the same signal Munich: R, Kramer Dipl.-Ing. · W. Weser Dipl.-Phys. Dr, rer. nat. · P. Hirsch Dipl.-Ing. · H.P. Brehm Dipl.-Chem. Dr. phil. nat. Wiesbaden: P. G. Blumbach Dipl.-Ing. . P. Bergen Dipl.-Ing. Dr. jur. · G. Zwirner Dipl.-Ing. Dipl.-W.-Ing. 909825/0772 and a delay device (20 or 81) which premature and therefore unwanted connection of the input node (61) of the second stage (Sp) to the reference voltage before the selective connection or non-connection of the output node (36) of the first stage (S.) to the reference voltage. 2. Multi-stage logic circuit according to claim 1, characterized in that each of the logic networks has the same switch (15) can be connected to the reference voltage, so that all Networks are operated simultaneously by the signal, and that the delay device is a signal inverter (20) having the output node (36) of the first stage (S.) with the input of the logic network (25) of the second stage (Sp) connects. 3. Multi-stage logic circuit according to claim 1, characterized in that each stage (S ₂ , S,) is assigned a different switch (15, 15 '), and that the delay device delays the signal so that the switch of the second stage ( S,) is only reached after the logic operation performed by the first stage (Sp) has ended. 909825/0772