DE2818529A1 - Automatic tuning of TV or radio receiver - has oscillator output digitally compared with reference to provide adjustment of frequency - Google Patents

Abstract

A fully automatic timing system for television or radio receivers is based upon a timing-remote-digital(TRD) technique. The output of the timing oscillator (1) is divided by a ratio of 2,048 over two stages (4, 6) and changes the state of an up-counter (18) to provide a measured value for comparison (14) with the required frequency provided by a ROM (16). An arithmetic unit (15) provides a signal difference that is converted by a D/A (10) to control the oscillator (1) to lock onto the required station.

Description

Voting procedure for the fully automatic voting of a

Television or radio receiver The invention relates to a Tuning process for the fully automatic tuning of a television or radio receiver with fully automatic station search in a tuning remote digital (= TRD) system, in which the actual oscillator frequency has a divider, a time gate and another Prescaler is fed to a counter in which the timer is controlled by a clock is controlled during a measuring time on passage from the oscillator to the counter and the tuning DC voltage required to tune the tuner from a digital-analogue Converter is obtained, the input signals for a turn to larger or smaller values changing DC tuning voltage from output circuitry during a the evaluation time following the measuring time is retained, in which the Operating device via a ROM from this a signal in binary coded Shape, e.g.

corresponds to the video carrier frequency in the new desired channel, is delivered.

Such a voting method is based on the following prior art from: GB-PS 1,168,438 shows an arrangement similar to US-PS 3,857,107. It is known from these publications to tune an oscillator by hand, for example. These two cited patents then show a circuit arrangement that stores the oscillator frequency once tuned, and another circuit arrangement, which keeps this oscillator frequency stable, i.e. with the help of a clock the The current oscillator frequency is constantly queried and compared to the stored value compared to the first set oscillator frequency. A measured difference is determined and fed to a follow-up control system that restores the oscillator tunes to the first frequency.

In contrast to these hand-tunable oscillators, in recently fully automatic voting systems known, which work with fully electronic coordination and also a fully automatic one Have station search. Such a circuit arrangement is e.g. in DE-OS 26 25 741, but the so-called tuning remote digital, hereinafter referred to as TRD system called, was built into numerous television receivers by the applicant and was Subject of the following publications: Lecture by Mr. Dipl.-Ing. M. Kalthoff with the title §'Integrated digital technology for voting and operating systems in the entertainment electronics "'held at the exhibition Electronica, Munich from 25.11. until 1.12.1976, article by Messrs Seidler and v. Vignau with the title Digital voting system, published in FUNKSCHAU 1976, pages 166 to 170, Furthermore, publication of the Valvo in "Development Communication" with the title TflD-System remote-controlled digital tuning and storage system for television receivers, output April 1976 and finally Valvo "Development Notifications" with the title TRD system with high capacity and flexibility ", No. 70 of November 1977.

This last-mentioned publication serves as a starting point and hence as prior art for the present invention.

In this publication is on pages 33 to 35 under 2.2.2.2. the tuning circuit SAB 2024 for picture carrier frequencies with a picture 28 that is a Function block diagram of the tuning circuit SAB 2024 shows, for explanation this Invention not sufficiently described here, so that below with reference to the attached Fig. 1 once again in detail the known TRD system with regard to its Voting procedure should be described.

The circuit arrangement shown in Fig. 1 also corresponds with respect to of the voting procedure, more details as given in Valvo "Development Notices" 70 from November 1977, page 34, Fig. 28 is shown, but in a slightly different representation.

The circuit arrangement or the voting process, as it is also shown in Applicant's television receiver circuitry is used as follows: The tuner, designated in Fig. 1 with the position 1, is on a tuned to a certain frequency. The used as a measure for this tuned frequency Oscillator frequency fO. . Now the TV receiver should be on a different channel be matched.

To do this, the operator operates a keyboard, such as the one mentioned above Valvo "Development Announcements" No. 70 on page 3, picture 1 shown. So that will the keyboard on the operating device, which is designated in Fig. 1 with 2, operated and thus an "address" is applied to the downstream ROM 16 according to FIG. A signal with the oscillator sequence appears in binary-coded form at the output of the ROM 16 of the new desired channel, i.e. a target signal that is binary-coded from this corresponds to the new desired oscillator frequency in the new desired channel. This setpoint signal is sent to an up / down frequency counter 17 from 10 bits and sets this counter 17 accordingly, i.e. it sets it Counter 17.

The tuner oscillator frequency f0 is determined by a divider 256: 1, i.e. from 47 to 890 MHz, 300 kHz to 3.6 MHz become a clock switch via a time gate and a further prescaler 8: 1 as a counting clock in serial form to another Input of said frequency counter 17 given.

Since the time gate only opens for 2.048 msec, the so-called measurement time, you can only during this time of the tuner oscillator actual frequency fO proportional pulses get to the counter and count it backwards. After the first 2.048 msec the counter at a certain value. Since he has zero detection circuitry it can be counted in a counting time of 1.024 after the measuring time msec denotes a clock from a clock generator, which is shown as such in FIG. 1 / is given to the counter via the clock switch, record: This clock with a The counter counts up periods of 16 / usec in the VHF and 4 / usec in the UHF range Zero. Then it stops. The clock is shown in Fig. 1 with the position number 3, the first divisor 256: 1 with position number 4, the time gate has that Reference number 5, the divider 8: 1, the reference number 6 and the clock switch consists of parts 7 and 8, as will be explained below.

Only during the specified cycle time, i.e. the counting or evaluation time, which follows the measurement time, a signal runs at the same time to a so-called Output, denoted by 9 in Fig. 1, from which a digital-to-analog converter DAU, in Fig. 1 with the reference numeral 10, is controlled, at the output now also during this time the output DC voltage to detune the Varicap diode in tuner oscillator 1 changes. A third time, the so-called setting time of 1.024 msec is used to enable tuner oscillator 1 to adjust. In order to a new cycle begins.

So that the voting direction can be determined, is behind the counter a so-called overflow (flip-flop), in FIG. 1 with ü or the reference numeral 11 provided, switched on. Since the counter only counts backwards during the measuring time, depending on the actual oscillator frequency f0, either zero is reached or exceeded been or not. Only when zero has been exceeded does the counter give its Output to overflow 11 from a pulse, i.e. the actual frequency fO was higher than the desired new frequency. If the overflow 11 receives an impulse, it gives the Output 9 the command to open minus den / output, i.e. the DAU with the reference number 10 emits a falling DC voltage during the above-mentioned counting time. Corresponding the Plus output is switched on when the overflow does not emit a pulse , i.e. the counter 17 has not reached the zero position and the actual frequency fO was therefore lower than the new desired target oscillator frequency.

At the same time, the overflow 11 gives a signal from its output the clock switch at 8, namely when the counter has run backwards above zero is, in the now immediately following counting time the counter counts up to zero will.

With this type of setting for the tuner oscillator frequency, the is Time for setting directly proportional to the counting time, i.e. also including the counting times, because there can be several.

The change in DC voltage for the tuning voltage UA at the output of the DAU with the reference number 10 is now directly proportional to the counting time, i.e. the Number of clocks that come from the clock generator 3 and count the counter to zero.

But now the tuning characteristic of a capacitance diode, i.e. the Characteristic curve C = f (UA), non-linear. That is, in the lower DC voltage range for UA a large C change is planned, e.g. for L UA it is six times greater at + 3V + 0.5 V than at +28 V + 0.5 V.

This has the following effect: Is e.g. in the lowest UHF range on the Adjacent channel switched, e.g. 7 clocks with 4 usec are then 7 MHz. Will against it switched to the adjacent channel in the uppermost UHF range, 7 cycle times are 4 / usec but only 0.5 MHz in the oscillator frequency change. Therefore, for example, there are twelve sitter tuning cycles required.

The object of the invention was therefore to avoid this disadvantage, because with acquaintances in the so-called steep part of the so-called tuner characteristic was voted too quickly and therefore the vote sometimes became uncertain and because, on the other hand, tuned far too slowly in the upper range of the tuner characteristic became.

In the case of the acquaintance, 1000 MHz divided by 256 in the first corresponded to Divider about 4 MHz. These were again divided by eight in the prescaler, i.e. about Q.5 MHz is at the counter input. This corresponds to a period of approximately 2 / usec, so that the counter has approximately 1000 periods during the measurement time of 2.048 msec can count. A 10 bit counter can therefore also handle the largest frequency difference that occurs record in the UHF range.

The invention is based on this prior art mentioned.

The above-mentioned task becomes the at the beginning in a voting procedure mentioned type according to the invention solved in that during a first measuring time the actual oscillator frequency is fed to the counter connected as an up counter that counts from zero and one obtained in this way and the actual oscillator frequency corresponding value in binary coded form as actual signal in a reference register gives that from the control device the new desired station in one of the Setpoint oscillator frequency corresponding value via a ROM in binary coded form is entered as a nominal signal in a differential circuit arrangement, which this setpoint signal with the actual signal from the reference register in a the measuring time compares the subsequent evaluation time, then the positive or negative measured difference is to a computer, which thereupon a positive or negative direction corresponding lead impulse of a certain duration as control impulse to the output, so that via the digital-to-analog converter at its output a changing in positive or negative direction during the time of the leading pulse DC tuning voltage arises and the oscillator readjusts, for which purpose the evaluation time a setting time and the time gate during these two times is locked that the computer is designed such that it then a fixed Number of control pulses emits as follow-up pulses, the length of each individual follow-up pulse by the in the immediately preceding measuring time and subsequent evaluation time measured difference between the actual and the target signal is determined.

In a further embodiment of the invention, the lead pulse can be a Have a duration of 16 / usec and the fixed number of follow-up pulses can be four be.

With such a voting process it is now possible, depending to effect the tuning of the tuner characteristic, the computer being designed in this way it must be that he always knows which average frequency change in the last Control signal step was performed.

An embodiment of the invention is shown in the drawing and is described in more detail below. 1 shows the known circuit arrangement for the Abstiamverfahren according to the TRD system, Fig. 2 the new circuit arrangement for a modified TRD system employing the invention, FIG. 3 is a graph Representation in which the dependence of the oscillator frequency on the tuning DC voltage to explain the invention drawn for an example tuner characteristic is.

1 was already mentioned above in the known prior art described. From this Fig. 1, only the following parts are used in the invention: The tuner 1, at the output signal of which the frequency f0 occurs, is the first divider 256: 1 with the reference number 4, then the time gate 5, the so-called prescaler 8 : 1 with the reference number 6, / operating device 2, the so-called ROM 16, which is connected downstream of the operating device, a clock generator 3, the outputs but are now performed differently, the output with the reference numeral 9 uni the digital-to-analog converter 10.

All other parts have been changed according to the invention.

In the circuit arrangement according to FIG. 2, the forward = REckvzärts = payer 179 so the 10 bit counter of Fig. 1, only as a forward payer 18 The binary coded signals can be connected directly to them via line 12 are removed and are now fed to a reference register 13. Farther there is differential circuitry 14 and a calculator 15. The clock 3 is only needed to open the time gate 5 in the cycle of 2.048 msec and then to close again in the same subsequent time of 2.048 msec. In addition, it gives a clock to the computer 15.

The clock in the circuit arrangement of the Invention no longer. The circuit arrangement according to FIG. 2 works as follows: The system be tuned to a certain frequency fo. The actual frequency f0 is in the counter during the measuring time of 2 & 048 msec. Now counted up, from zero the end. Then the actual frequency appears at the counter output in binary coded form as so-called actual signal and is entered in the reference register 13 and sets this a, i.e.

it is stored here.

When a new channel needs to be tuned in, the operating device 2 come a signal on the ROM.

The ROM is set to a new value and from this ROM a binary coded signal runs, which is the nominal signal, in the differential circuit arrangement 14th

This differential circuit arrangement also receives the actual signal from the reference register 13 and compares these two signals with each other and then gives at its output the command to a computer via the lines drawn with the (+) and minus (-) lines to emit another impulse in the plus or minus direction.

Since the computer of the differential circuit arrangement already two receives different signals, he knows whether the new desired channel in frequency is above or below the previous actual value for f0. The calculator is calculating now, as will be described in more detail below, a forward pulse of e.g. 16 / usec duration and gives it to the output in the correct direction. the The setting starts according to this 16 / usec pulse, i.e. only during this Time appears at the output of the digital analog converter 10, a tuning DC voltage in the relevant positive or negative direction, i.e. a falling or rising Tuning DC voltage UA. A so-called response time then starts. she is exactly as with the previous TRD system 1.024 msec long, so that the measuring time 2.048 msec. A so-called evaluation time then follows.

This is followed by the response time again with a duration of 1.024 msec. After the second measuring time, the actual frequency is determined again and again entered into the reference register 13, according to the following scheme: It should the The measured actual oscillator frequency is 860 NHz is given by the operating device, should e.g. be 440 MHz. The lead pulse be 16 / usec duration, i.e. a retuning in the lower UHF band is e.g. based on 16 / usec duration, 4 MHz, in the lower VHF band 1 MHz, in the upper UHF band only 0.5 MHz and in the upper VHF band only 200 KHz These different Attitudes come because, as already stated above, for a specific DC voltage step another frequency step takes place due to the curvature of the so-called Tuner characteristic, which is shown in Fig. 2 and which is described in more detail below will. The differential circuit arrangement 14 now gives the direction to the computer 15 before. The lead pulse creates e.g. 0.5 MHz at 860 MHz, so it is practically none Change has been noted. The computer now divides the rest, i.e. the remaining one Frequency difference, by four, if it is arranged to have more four steps, i.e. emit four follow-up pulses until the target frequency is reached will. The computer 15 thus divides about 420 MHz: 4, which results in 105 MHz. Done were due to the 16 / usec lead pulse only 0.5 MHz, i.e. the computer is calculating now 105: 0.5 MHz = 210 x 16 / usec.

The first follow-up pulse must therefore be 3370 / usec or 3.37 msec long be.

Because of the curvature of the characteristic, however, this first follow-up pulse now creates not the 105 MHz, but 200 MHz, because it now tunes down and down the characteristic comes into areas of greater steepness. The next frequency, i.e. the The next actual frequency fO,, of the oscillator is called: 859.5 MHz - 200 MHz = 659.5 MHz. The difference up to the solo oscillator frequency is then still 219.5 MHz. now the computer 15 notices that it was too much and it knows that it is now an average Slope of 0.5 MHz / 16 / usec was not achieved, but an average one Slope of about 1 MHz / 16 / usec.

The next follow-up impulse from the computer will be there too There are still three steps to be taken: 219.5 tÇHz: 3 / approx. 70 MHz calculated in advance. the The slope was about 1 MHz on average, so the second tracking pulse must be 70: 1 = 70 and now with 16 / usecmultiPlizieit = 1120 7usec or = 1.12 msec long be.

Now the steep branch of the tuner characteristic is controlled.

The real retuning was not now 70, but it was 159.5 MHz. The new actual frequency f0 is then 500 MHz. The 16 / usec step so was on average not 1 MHz, but even 2 MHz.

The computer notices this again. The new difference is now only 60 MHz. There are only two steps left.

It calculates 60 MHz: 2 = 30 MHz. 2 MHz was the last average for the average step, so the next pulse must be 30: 2 = 15 and this Number must be multiplied by 16 / usec, so this results in the third follow-up pulse one of 241 / usec duration.

The characteristic of the tuner is now about the same steep. So it will be not 3G but 40 MHz reached, i.e. the slope is now 3 MHz / 16 / usec step. The new actual frequency is now called 460 MHz. One step remains to be taken, so a 20 MHz step. That is then 20: 3 = 6.67 and this amount with 16 / usec multiplied results in the fourth and last follow-up control pulse of 106 / usec Duration.

The computer 15 therefore always calculates the actual frequency reached in 16 / usec steps and determines from the difference which average step per 16 / usec is done, i.e. how large the frequency step of the actual frequency for 16 / usec was, and it now calculates how much for the next follow-up control pulse Steps of 16 / usec up to the target frequency are required, divided by the number still following impulses.

The computer 15 according to the invention can therefore access the difference between emit pulses adapted to the actual and setpoint frequency and thus create the circuit arrangement according to the invention according to the new tuning method an adaptation to the tuner characteristic. It doesn't matter whether you tune in the lower or upper channel area, whether one channel is tuned to the adjacent channel or from one channel over several Channels is tuned, and it does not matter whether from the lower to the upper range is tuned towards or from the upper to the lower area. Every time are after The computer emits a fixed number of follow-up pulses to the lead pulse, and these follow-up pulses are, as described above, adapted to the characteristic curve.

This is again based on FIG. 3 for an oppositely running one Example described: FIG. 3 shows the oscillator frequency fg as a function of the DC input voltage UA in volts. It shows the typical curvature of a tuner characteristic. Point A is the starting point, namely point 1 on the frequency coordinate is equivalent to i.e. the current actual frequency. A 16 / usec pulse now runs first. As a result, the oscillator frequency f0 slips from 1 to 2, the DC voltage becomes changed from A to B. Then there is a division into four equal parts, with the first step getting bigger. The first step therefore corresponds to a DC voltage to point C, with which point 3 is reached. Then points D and E and finally the point F is reached, and it is in the ordinate, i.e. in frequency, recognizable that the distances from 2 to 3, 3 to 4 and 4 to 5 and finally from 5 to 6 become smaller and smaller, although the tension steps are not significantly different reduce and in this way a fast, safe, but adapted Approaching the desired frequency is possible, whereby the time difference from Point in time at voltage A to the point in time when voltage F is reached, always is the same whether from A to C, from E to F or from A to F or from F is tuned to A, i.e. from one to the other channel or via an or across multiple channels.

The numerical example given above clearly shows that when measured in the PunkrF and there would only be a single impulse corresponding to reaching the point A given, i.e. only one single step done, the frequency change would be a lot too large. Therefore, several steps have to be created so that always in the new one Measuring point a new adjustment to the steepness of the tuner characteristic can be made.

The computer 15, the heart of this invention, is designed in such a way that that it initially has a larger, i.e., in terms of frequency seen time gives up and as a result is a bit too big a step in itself, but after that then take place that are getting smaller and smaller. It has emerged from numerous attempts and Series of measurements show that one pre-run step and four post-run steps are obvious are optimal and the advance step should have a length of 16 / usec.

Compared to the known TRD system, as described for FIG. 1 and was explained in more detail in Valvo Development Bulletin No. 70, just to give an example to give a 500 MHz distant new channel tuned in at the same time as with the acquaintance an adjacent channel. The vote on larger frequency differences is much faster with the new system, and with smaller frequency steps, So tuning in the steep range of the tuner characteristic from one to the other channel, is about the same speed as the known system, but safer.

Claims (3)

PATENT CLAIMS: Voting process for fully automatic voting a television or radio receiver with fully automatic station search in one Tuning remote digital (= TRD) system in which the actual oscillator frequency is controlled by a Divider, a time gate and a further prescaler is fed to a counter which the time gate by a clock generator during a measuring time on passage from the oscillator is controlled to the counter and the tuning DC voltage required to tune the tuner is obtained from a digital-to-analog converter, the input signals for a DC tuning voltage changing to greater or lesser values from output circuitry received during an evaluation time following the measuring time, in which continues from the operating device via a ROM from this a signal in binary coded form Shape that corresponds, for example, to the video carrier frequency in the new desired channel, is output, characterized in that the actual oscillator frequency during a first measuring time is fed to the counter connected as an up counter, which counts from zero and a value obtained in this way and corresponding to the actual oscillator frequency in binary encoded form as an actual signal in a reference register that from the operating device the new desired transmitter into one of the target oscillator frequency Value via a ROM in binary coded form as a target signal in a Difference circuitry is entered, which this setpoint signal with the actual signal from the reference register in an evaluation time following the measurement time compares, then sends the positive or negative measured difference to a computer, which then generates a lead pulse corresponding to a positive or negative direction given duration as a control pulse to the output, so that via the digital-to-analog converter at its output a positive or negative direction during the time The tuning DC voltage that changes the lead pulse is generated and the oscillator readjusts, for which purpose the evaluation time is followed by a setting time and the time gate it is blocked during these two times so that the computer is designed in such a way that that it then emits a fixed number of control pulses as follow-up pulses, where the length of each individual tracking pulse by the in the immediately previous measuring time and subsequent evaluation time measured difference between the actual and the target signal is determined. 2. voting method according to claim 1, characterized in that the Leading pulse has a duration of 16 / usec. 3. Voting method according to claim 1 or 2, characterized in that that the fixed number of follow-up pulses is four.