DE2758218C3 - Electronic cash register - Google Patents

Description

The present invention relates to an electronic cash register according to the preamble of Claim 1.

In general, in an electronic cash register, an amount is entered for each commodity via an input keyboard is entered, and then a department key corresponding to the department to which the sold goods heard activated The data entered are processed, sorted and accumulative in Storage devices are stored which are designed to add up the sales amounts and the item quantities for each department, as well as for Total amount formation for the day in question and the total sales for each employee. At the end of On the working day, the cash register is put into a reset mode one after the other to print out various data stored in the corresponding memories, and then these memories are deleted. These sorted sales data are used for management purposes

A cash register of the type mentioned is already known from the company copy: The National Cash Register Company, Dayton, Ohio, USA, Class 230-101 Electronic Cash Register, 1972. With the known cash register, special data can be evaluated, for example information about sales in certain departments, etc. However, the known cash register does not offer the possibility of providing time-dependent sales data, so that differentiated analysis of this data is possible. It is desirable to have data available that provide precise information, for example about times of high sales within a given sales period. It is not possible to record such data with conventional cash registers.

DE-OS 19 45 515 discloses a mechanical cash register with two payment mechanisms that go through an electric time clock is added. In the first Counter are all entered via the keypad Amounts totaled. That at any time setting The clock's adjustable stamping mechanism automatically prints the times and those set during the Period of time added by the second counter amounts on a widened control strip off, the second counter zeroing each time

will. In an alternative embodiment takes place the printing of the time and a subtotal when a combined timestamp and subtotal key is pressed. In the latter embodiment, the operator or the supervisor ensure that the key is pressed at the correct time each time; otherwise the printed ones are Data worthless for sales statistics. For the embodiment with automatic printing of the Time and the intermediate sum is not a reworkable ι ο Teaching indicated. Another disadvantage of the known AiiuiuiiUiig that the journal strips of an entire Day have to be evaluated, which is especially troublesome when monitoring over the Duration of several days or weeks should take place. The separate printout of the subtotals distributed over periods requires a widened or a second control strip with a correspondingly widened one Printing unit. Another difficulty with the known arrangement is that the Time clock must be added to the cash register in such a way that on the one hand the time on the Control strips printed out and otherwise: a control between the time clock and the cash register should be possible

The invention is based on the object of providing an electronic cash register of the type mentioned at the beginning which provides a clear breakdown of sales according to time periods with simple means

The object is achieved by the features of the characterizing part of claim 1

With the electronic cash register according to the invention, the desired time periods can be set by simply entering it on the cash register's keyboard. Since sales for the respective periods are not printed out immediately but saved separately, exists once the possibility of printing out these values in list form at any time and on the other hand to extend the evaluation over a longer period of time for weeks or months.

Advantageous further developments of the electronic cash register according to the invention are set out in the subclaims marked.

In the cash register according to the invention, a sales period, for example a sales day, is divided into several time intervals or time zones. If a registration is made, the comparator determines the time zone in which the registration process falls, and depending on this result, the registered amount is stored in a memory location that is assigned to the respective time zone. In this way, the collected data can be evaluated extremely efficiently from a business point of view at a later point in time. So z. B. The stored data provide information about sales peaks, extremely quiet business hours, etc. Such Dau-n ν for the management of a company äuOeisi wer'vo'i, thnn on their basis can be escaped, 'mgen trr ^f :> n about the personnel Use at certain times

In addition, the time function is based on years. Extended months, weeks and days, one can Operator pre-setting the time period for the entire amount formation, e.g. B. for a week, * 5 one and a month, or a period of two days, or the like. Accordingly, the aggregation for a period longer than a day, resulting in a substantial Improvement of the total amount formation of the cash register leads.

In the following an embodiment of the invention is explained in more detail with reference to the drawing E ¹ shows

Fi g. 1 eme keyboard of an electronic cash register,

F i g. 2A and 2B collectively show a block diagram of the entire cash register;

Fig. 3A is a circuit diagram in the circuit according to FIG. 2 central unit used,

F i g. 3B is a circuit diagram showing a memory and a timer shown in FIG. 2 shows

F i g. 4 a memory overview of the memory,

5A and 5B memory overviews of the time memory in the clock,

F i g. 6A and 6B are a flow chart illustrating the operation of the circuit in FIG Time counting,

7 shows a data overview of the data stored in ό "η time memory of the time clock,

F i g. 8A to 8C, data stored in the time memory and the register in time counting, and

F i g. 9A and 9B a schematic representation for Illustrate the process of printing successive lines and dates.

F i g. 1 shows the arrangement of a keyboard 10 of an electronic cash register (ECR). Numeral 11 denotes amount keys for entering numerical values such as. B. Price and quantity of goods, 12 denotes a department key for registering goods by group, 13 denotes a clear key for clearing numerical data entered from the amount keyboard 11. A function keyboard provided with the reference number 14 consists of individual keys which represent a non-addition (#) for providing the preselected time, as well as a space key (Vo), a multiplication key '©), a percent key (%), and (+) - and (-) keys, which are used to display the increase or decrease in percentages. «. Numeral 15 denotes an employee key for inputting the responsible person. A sales keyboard 16 includes Hnzelr.e keys, each of the receipt (Rc), payment (Pd), total net (Nt), balance (Bl), no sales (NS). Represent credit (Cr) and stress (Ch). Numeral 17 denotes a subtotal key (ST) for obtaining intermediate results in a calculation process. A balance key 18 (Ca / AMT) is used to issue a receipt to receive the total amount and / or the change amount. A time button 19 is v for providing the time ve ^r ': friend. 19a denotes an operation key for providing an operation period. 19b provides a time range for the overall somatic formation. 19c designates an alarm button (AL) for providing an alarm. The χ keys 19a to 19c represent the time keypad 19. A control lock 20 can be switched over to the operating speed (OFF). (Pr), (REG). (X) ur.d (7) to count. The operating / u <tan <l (OFF) is used when the electronic cash register is out of order; the operating state (Pr) is used for presetting data! the state (R ^ G) is used in normal registration, o operating state (X) is used in read operations without the stored data being lost; the operating state (Z) becomes

Reset used to clear data after the stored data has been read.

The following description relates to the internal configuration of the electronic cash register according to the present invention. Numeral 31 denotes an input / output controller (I / O) that controls the keyboard 10 and a printer part 33. The I / O controller 31 supplies the keyboard 10 with a scanning signal. When a key on the keyboard IO is operated, the scanning signal is selected in response to the key operation and supplied to the I / O controller 31 as a key input signal. Upon receipt of the key input from the keyboard, the I / O controller 311 loads the key input into an input buffer register (not shown) for temporary storage therein. The printer part 33 comprises a receipt director 36 and a single tape printer 37. The printers 36 and 37 are provided with platen 38 and 39 which are coaxially arranged and have numerical characters on their surfaces, receipt tape 41 and a single tape 42 are tightly on the platen 38 or 39 arranged. Opposite the print rollers 38 and 39 with the receipt strip 41 and the individual strip 42, print hammers are arranged, in front of which there are ribbons (not shown) certain angles of rotation of the rollers to emit detector signals. The detector signals are supplied to the I / O controller 31 via an amplifier 45. When the print position detection signal and the print data coincide, the I / O controller 31 supplies a drive signal via a driver 35 to the print hammer that the print type is facing at that time to drive the hammer. When the print rollers 38 and 39 complete one revolution, the printing of one line is completed, and the receipt slip 41 and the individual strip 42 are advanced by one line. As the printing progresses, the receipt strip 41 is led to the outside so that the printed section can be torn off after the printing process has ended. For example, "Your receipt - thank you" can be printed on the receipt strip 41. The same print data that is printed on the receipt slip 41 is recorded on the individual slip 42, which is picked up by a shaft 46, in order to obtain the net total. A memory 47 and a timer 38 are connected to a central processing unit (hereinafter central unit) 34 ^M. An energy source 49 is connected to both the memory 47 and the timer 48 in order to keep them always ready for use. The timer 48 is also connected to a reference frequency oscillator, which can be a crystal oscillator 50, for example. The memory 47 and the timer 48 are formed on a single chip. The CPU 34 generates a chip enable signal CEi to specify the memory circuit 47 and another chip · select signal ^Μ CE2 to specify the timer 48. A read / write signal R / W from the memory 47 indicates the read or write operation of the memory. The timer supplies current time data and daily data which are read out by the central unit 34, if necessary. The time data is used as time stamp data when totalizing is performed at a given point in time. The central processing unit 34 performs the receipt slip output in response to a key input signal from the keyboard. The processing data at this time are supplied as thumbnails data to the I / O controller 31 and, via a display driver 51, to a display section 24, where they are made visible.

Figures 3A and 3B together illustrate the details of the central processing unit 34, memory 47 and the timer 48. The central processing unit 34 will be explained first. An address circuit 61 specifies the address of a Control section 62. The control section 62 comprises a microprogram that controls the operations of the respective Controls circuit parts. The microprogram is stored in read-only memory (ROM). Of the The control section comprises output lines 63 to 66. The output connection 63 provides a Cuüegciiciäiui-Beicni, the output line 64 a given timing signal, the output line 65 various commands, e.g. B. a Register specification signal, a transfer command, a digit shift command, and the output line. G 66 provides the next address itself. The code generator command from output line 63 is transmitted to a code generator circuit 67. A timing signal from output line 64 is on a master transmitter circuit 68 is given. The commands from the output line 65 become a command decoder 69 transferred. The next address output on line 66 is sent to an address circuit 61 to set the next address. A timing signal from a timer signal generator 80, which is provided in the central unit 34, is sent to the code generator circuit 67, the timer circuit 68 and the command decoder 69 given. The code generator circuit 67 converts given the time 4-bit parallel data output from the control section 62, for example to be converted into a serial code. The output of the code generator circuit 67 is via a gate circuit 70 fed to an adder / subtracter 71. The timer circuit 68 sets the timing of the operation the registers, as well as their digit handling according to the timing signal that is transmitted via the Output line 64 is supplied from the control section 62. The output signals are saved as Enable or disable signals to the corresponding gate circuits within the central unit 34 led, so z. B. to the gate circuit 70 and the AND gates 72 and 75. The outputs of the UN J elements 72 and 75 are sent via OR gates 76 to an input / output register 78a within the register group 77 routed The command decoder 69 decodes a command issued by the control part 62 to the To control activities in the corresponding parts of the central unit 34, such as the determination of the Register within the register group 77, and it issues a read / write command to the memory 47 and the Timer 48. The outputs of the timer circuit 68 and the command decoder 69 are called Control signals to the display driver 51 and to the I / O controller 31 includes the X register as input / output register 78a as well as other registers 786 to 78n starting with Y to N The output of the register group 77 is connected to the adder / subtracter 71 via an OR

Link 70 connected. The output of the X register 78a is fed to an AND gate 72 via a circuit 79a, the circuit 79a being a memory with the capacity of one digit. The output signal of the adder / subtracter 71 is fed to the AND gate 74. The key input signal from the keyboard 10 is fed to the AND gate 74 via the I / O controller 31. The decoded data from the memory 47 and the timer 48 are passed to the AND element 75. The outputs of the register X to N are 786 / j to 78 η directed by register 79b to 79n b to gate circuits 81 to 81, wherein the registers 796 to 79n each having a storage capacity of a digit. The output signal of the adder / subtracter 71 is also fed to the gate circuits 81 b to 81 π. The outputs of the gate circuits 816 to 81 /? are applied to the X through N registers 786 through 78n. The output variables of the X register 78a are supplied as display data or printouts to the display unit 5i and the I / O controller 31 and a chip selection circuit 82. In accordance with an instruction given from the control section 62, the chip selection circuit reads

82 from the chip selection data in the X register 78a and generates the chip enable signals CE 1 and CE2 according to the contents of the register, in order to thereby drive the memory 47 or the timer 48. The outputs of the adder / subtracter 71 are loaded into the A register 83 for addressing. The data docied by the A register 83 is given to the adder / subtracter 71 through the gate circuit 70 and divided into two addresses; an address RA represents a row address and an address CA represents a column address. These addresses are supplied to the memory 47 and the timer 48. Data and carry signals output from the adder / subtracter 71 are supplied to a judging circuit 84. The judging circuit 84 judges whether or not there is the data or the carry from the circuit 71 and passes the result of the judgment to the address circuit 61. At this time, the subsequent address is output through the output line 66, and the detection signal is logically summed up so that the next address is changed.

The memory 47 comprises a memory unit 91 and an address determination circuit 92 into which the Read / write command R / W from command decoder 69 and the row and column addresses from the A register

83 are loaded. The address determination circuit 92 and the gate circuit 93 are enabled by the chip enable signal CE1 output by the chip selection circuit 82. The data read out from the memory unit 91 via the gate circuit 93 are fed to the AND element 75 of the central unit 34, as has already been mentioned above. The output signal of the X register 78a in the central unit 34 is passed as write data to the memory unit 91 via a gate circuit 93. The memory unit 91 has a capacity of nx8, as in FIG. 4 is shown. The columns B 1 to B 8 are defined by the column address CA while the rows 1 to η are defined by the row address RA . The memory unit 91 is divided into three sections: a first section comprising the 91/4 columns Bl to BA, a second portion 91 comprises the columns B and BS 56, and a third section 91C comprises the columns Bl to BS. In the first

Section 91/1 save the first through the sixteenth Address the department total corresponding to department key 12. The seventeenth address stores the total sales between times 71 and 72. The eighteenth address stores the Total sales in the specified time range between 72 and Γ3. Stores the nineteenth address the total turnover in the time range between points in time 73 and 74. Below the twentieth Address, the total amount received is saved. Thus, this memory area is considered to be time-related Denotes total sales storage area. In the second area there is the item or article count stored under addresses 1 to 16. The sales counts between the specified times Π and 72, 72 and 73, and 73 and 74 are in the memory area under the addresses 17 saved to 19. The reception count is stored in the twentieth address. Preset item prices in the appropriate departments are at the first to sixteenth address within the Section 91 Cab saved.

According to FIG. 3B, the timer 48 is equipped with a time memory 100 which is used to store the day data, the current time data and preselected time data and the like. The time memory 100 is addressed by the addresses RA and CA of the rows and columns in the address determination circuit 101 via the A register 83 in the central processing unit 34, and the read and write operations are effected by R / W commands sent by the Command decoder 69 are supplied. A control part 110 of the timer 48 supplies an address code signal and the R / W command to the address determination circuit 101 for addressing the time memory 100. The data output from the time memory 100 is passed through a gate circuit 102 to a buffer register 103 and a gate circuit 104 given. The output of the buffer register 103 and a one-second clock pulse from a frequency divider 105 are fed to the gate circuit 104. The frequency divider 105 works as a function of a crystal oscillator 50 and, in addition to the one-second pulse, generates a timer signal which controls the timing of the operation of the corresponding parts in the control part 110. The gate circuit 104 selects an input signal in accordance with a control signal from the control part 110 and feeds this to a computing circuit 106 embodied as an adder / subtracter. The arithmetic circuit 106 carries out an addition or subtraction in accordance with a command issued by the control part 110 and forwards the result of the calculation as write data via the gate circuit 107 to the time memory 100 , are fed to the judging circuit 108 in order to judge the memory status of, for example, 60 or 24 size and timer matches. The result of the assessment by the assessment circuit 108 is sent to the control part 110, which in turn generates a control signal for the next processing on the basis of the assessment result.The data read out from the time memory 100 are passed via a gate circuit 109 to the AND gate 75 in the central unit. The gate circuits 107 and 109 and the address determination circuit 101 are enabled by the chip enable signal CE2 from the chip selection circuit 82.

The gate circuits 102, 104, 107 and the arithmetic circuit 106, as well as the assessment circuit 10f, are controlled by a signal emitted by the control part. The gate circuit 107 is controlled by the chip enable signal CE2 and the signal from the control part 110. The time memory 100 has a storage capacity of four rows by eight columns, which can be seen, for example, in FIG. 5A. The corresponding columns B1 to BS are identified by the column address CA , while those in corresponding rows are identified by the row address signal RA . Rows 1 to 3 store time data such as B. Hours and minutes for two columns each, ie Bi-BT, S6-B5, 04-ß3, and B 2-Bi. In addition, time data for clearly defined total sums TO 1 to TO 4 are stored in the first row. Time data AL 1 to AL 4 are stored in the second row, and time data for an operation time 5V1 to SV4 define the total time range; the time data AL i to AL 4 define a: r, alarm time, and the time data SVI to SV4 define the operation time of a price reduction and the like, the columns store in the fourth row B 8-57 flag I and FLAG 2, the correspondence between.. display the current time and the specified time; columns ß6 to 54 store the year, month and day of the relevant date; the columns B 3 to Bi the hour, the minute and the second of the current time. In the memory location of the fourth row under column B1 of the time memory 100 for storing w the flag 2, a binary "1" is stored in the first bit b \ if the current time is between Ti and T2 , while a "1" is in the second Bit b2 is stored if the current time is between Γ2 and Γ3; A “1” is stored in the third bit b3 if the current time is between T3 and 74.

In operation, the timer 48 operates in accordance with a reference signal supplied by the crystal oscillator 50. The reference signal emitted by the crystal oscillator 50 · * ο is applied to the frequency divider 105, which generates the one-second pulse and various timing pulses. The one-second pulse of the frequency divider 105 is fed to the computing circuit via the gate circuit 104. The control section 110 sets the row address RA = 4 to define the fourth row of the time memory 100 and reads the content of the memory location addressed in the time memory 100 via a gate circuit 102 in order to then load it into the buffer register 103. The gate 104 selects the output of the buffer register 103 and the one-second pulse of the frequency divider 105 and supplies them to the arithmetic circuit 106, thereby adding the one-second pulse to the second data of the column B 1. The output signal of the computing circuit 106 is fed to the time memory 100 via the gate 107 and is written into the fourth row. In this way, the contents of the multiple rows of memory 100 are always "refreshed". The output of the arithmetic circuit 106 is supplied to the judgment circuit 104, where it is judged whether the result of addition reaches a predetermined value or not, and the judgment result is determined, the control operation in the control portion Specifically, when the addition of the Sekundeniiapulses the number B 1 of the fourth Column reached, d. k, when the second amount reaches 60, this condition is determined by the judging circuit 108, and the control section adds "1" to the content of column B 2 of the four rows, that is, to the minute amount, while at the same time clearing the second amount . A similar operation of the transmission control is repeated below to accommodate the setting for minutes, hours, months and years.

When initially setting the timer 48, the date and time must be correctly set. When setting the control switch 20 in Fig. 1 is set to Pr, and here the amount key 11 is operated accordingly to indicate the sizes for the year, month, day, hour, minute and second. In this case, the "#" key is depressed every time data is entered into the electronic cash register. The input data entered by the corresponding keystrokes via the keyboard 10 are fed via the I / O control 31 to the central processing unit 34, where they are entered into the X register 78a via the AND gate 74 and the OR gate 76 shown in FIG will. The input data stored in the X register 78a is transferred to the timer 48 where it is loaded into the intermediate sections of the fourth row of the columns S 6 to B 1 via a gate circuit 107. In this way, the data and time data are loaded into the time memory 100 of the timer 48, and after the seconds amount loading is finally completed, the above-mentioned timing operation is carried out.

If the time data for the temporal totalization, the time data for the service time and the time data for the alarm time are written into the time memory 100, this is done by using the amount key 11, the 7b key 19ft, the SV key 19a and the y4L- Button 19c accomplished 1st z. If, for example, the time date for the hour is entered using the amount key 11, the minute amount is entered using the Γο key 19Z ». After pressing the 7b key 19 /? the time sequence specifying the date "1" is entered by the amount key 11 to address the area of the first row in the columns' θ 7 and B 8, so that the hour and minute of the time date Ti are loaded into it. If the above operation is performed using the SV keys 19a in place of the Γο key 196, the time data for the service time is loaded into the memory 100 in the third row sections under the columns B 7 and BS. Pressing the i4L key 19c writes the time data for an alarm in the sections of the second row under columns B 7 and B 8.

The amount key If and the department key 12 is pressed with the control switch 20 switched to the position Pr. Here, the key input data in the memory unit 47 via the X register 78a. In the memory 47, the key input data written at the first to the sixteenth address in the third memory of the memory unit 91, which is done via the gate circuit S3

When processing the sales of goods, the control switch 20 is set to REG, and the item prices of the sales goods are entered using the amount key 11. Then that department key will be 12 " actuated, which by the printer part 33 on the receipt strip 41 or the individual strip 42 is printed out. At the same time, the input data

are displayed on the display 24 to which the input data are brought through the central processing unit 34 and the output driver 51, and the data are accumulated in the central processing unit 34. ^{Furthermore, data corresponding to the address specified by the r} > department key 12 are read out from the memory 47 to the central processing unit 36, where they are added to the input data, and the result of the addition is written in the memory 47 at the specified address. Now the price is added to a particular row of the first area 91/4, and the lot or item count is added to a particular row of the second region 91B. In this way, the operation similar to that described above is repeated by operating the amount key 11 and r> of the department vaste 12 for each good sold. Once the prices of all goods sold have been entered and the department has been specified, the balance key 18 is actuated in order to output a receipt with the total amount and / or the change amount. The total amount thus obtained by the central unit 34 is made visible in the display part 24 and fed via the I / O control 31 to the printer part 33, where it is printed out on the individual strip 42 and the receipt strip 43. If the 2> processing is carried out using the department preset key for each department in the manner explained above without entering the prices of the goods, the above process is similarly carried out with the input data of the preset data of that address which corresponds to the department key 12 by only pressing the department key 12.

The operation of the temporally predetermined total sum formation is described below with reference to FIG. 1 to 8. If data relating to goods sold are entered, the key input signal is passed on via the I / O control 31 to the central processing unit 34 and set in the register 78a. The balance key 18 is then actuated so that the data from the X- Register 78a can be transferred to Y register 786 as shown in FIG. 6A is shown in step A, the data flow is at this time so that the flowing out of the X register 78a of data by the gate 70, the adder / subtractor 71 * and the gate 816 in the Y-register 786 reach. In the next step 6, the control section 62 reads out the chip determining data in order to set the time memory 100 in the timer 48 and loads this value into given digits of the X register 78a. The control section 62 issues an operation command to the Cnip selection circuit 82. After receiving the operation command, the Qvip selection circuit 82 reads the chip-determining data from a given digit of the X register 78a and generates the chip enable signal CE2 to the Time memory 100 to be specified. Thereafter, the control section 62 generates addresses RA = 4 and CA = 57 in order to set the intermediate section of the fourth row under the columns B 7 of the time memory 100. The «> addresses are converted into serial codes by the code generator circuit 57, then Jer converted Cod? supplied by the general adder / subtracter 71. The addresses RA and CA output by the adder / subtracter 71 are entered into the Α register S5, where they are converted into parallel data, which in turn are the addressees ISi within the time clock 48 were supplied. A read command from the control section 62 is set via the command decoder 69 therein. That is, the chip enable signal CE 2 specifies the timer 48, and da ¹ ; ί! ag 2 addresses the time memory 100. By addressing in step b , the flag 2, which is stored in the memory location of the fourth row and the memory location BI (4, B 7) of the time memory 100, is read out, and the readout signal is transmitted via the AND gate 73 and the OR gate 76 to the X-Regisiej- ''"ia. When the current time is read from the time memory 100 into the buffer register 103, the timer 48 successively reads the time data of the time Total sum formation 7 * 1 to 74 from the time memory 100 and feeds them via the gate 104 to the arithmetic circuit 106 in order to compare these data with the current time stored in the buffer register 103. The comparison result is fed to the assessment circuit 108 the service time, ie Tl to 72, 72 to 73 or 73 to 74, to which the current time belongs is searched, and the binary code "1" is stored in the corresponding bit of flag 2 memory location b \ to 6 3 of the time memory 100 is loaded.

Assume that the time 71 is preset to 10 a.m., 72 a.m. to 12 p.m., 73 to 2 p.m. and 74 to 5 p.m. As described above, the memory location M (4, BT) time memory 100 is addressed and the content of flag 2 is read from the time memory 100 into the output register 78a. The current time 1030 o'clock falls in the time range 71 to 72, ie 10:00 am to 12:00 pm, and the binary "1" is written to the first bit b 1 of flag 2, so that flag 2 has the value "0001". As can be seen in step c of FIG. 6, the content "0001" of the flag 2, which has been read into the register 78a, is passed to the judgment circuit 84 via the gate 70 and the adder / subtracter 71. whether any of the bits of the flag 2 contains a "1" or not, as shown in step d if the result of judgment is nO, d. In other words, if the current time does not fall within the time ranges, the total time is not calculated and the acknowledgment is issued immediately. If the assessment is {Λ, i. If the current time falls within one of the time ranges, the process continues at step e in FIG. 6 continued. In this step, the control section 62 causes the chip determination circuit 82 to generate a chip enable signal CEi and addresses the memory unit 47 to address one of the addresses 17 to J9 in accordance with the contents of the flag 2. In this case, the current time falls within the time range 71 to 72, so that the seventeenth address of the memory 47 is determined. Then the transition to step / in Fig. 6A takes place. The contents of M (RA, CA), for example the article nunsier "20" in the time range between 71 and 72 and the intermediate amount "i 13,200" in the same range, are then read out into the X register 78a. The contents of "£ 13,200" in the X-Register 78a and the sales data, e.g. B. "£ 700" which m the Y-Register 781; are stored, are fed to the adder / subtracter 71 via the gate circuit 70. In the circuit 71, these values are added. Furthermore, the Artüusizahi * 20 "in the time range Ti to 72 to the adder / sabotage 7 J", where s; e a K- ^ Ti.: ";: -. Is thrown. Dsnacb is the

Total amount “^ 13300” is stored in the time range TX to T2 and the number of articles “21” in the same time range at the seventeenth address of memory 47

The sequence of step e according to FIG. 6A is shown in detail in FIG. 6B. In step e 1, it is determined whether or not a "1" is present in the first bit b 1, i. k, whether the content of flag 2 has the value 0001 or not. If bit b 1 contains a "1", step e2 loads the chip enable signal ir. the X register 78 and also the row address RA = 17 and the column address CA = 01 are loaded into the A register 83. If no “1” is set in bit 61 in step e 1, step e 3 is carried out to see whether the binary “1” is set in the second bit b 2 or not. If the “Ί” in bit 62 is set, a step e4 loads the chip enable signal CE1 into the X register 78a and sets the row address RA = 18 and the column address CA = 01 in the A register 83. If no "!" Is stored in the bit b 2 ! TR step e 3, a next step e5 is carried out. This step loads the chip enable signal CE 1 into the X register 78a and the row address RA = 19 and the column address CA = BWr the A address register 83.

F i g. 8B shows the case when the sales process is done at 11 30 am

If the conversion processing after 12.00 happens, for example, 12.10Uhr, as shown in Figure 8C wherein the total summation is performed and a receipt is issued, the memory locations in the eighteenth row are β under columns 6 to B \ of memory 100 specified because at this point in time the second bit b2 of flag 2 is set to "1" and therefore its content is "0010". If this sale is the first one after 12 noon. so the contents of the eighteenth row under columns B 6 to B 1 are all "0". Correspondingly, the article number in the time range 72 to T 3 is stored in the memory locations of columns 06 to 01 and the eighteenth row with the total amount within the same time range, for example "4,450". of the sales amount is loaded at this point in time. Thereafter, the data aggregation with respect to the storage locations of the eighteenth row under the columns 05 to 01 of the memory 100 up to the time Γ3. i.e. 2:00 p.m. continued

After 2:00 p.m., the data relating to the memory locations is in the nineteenth row under columns 06 to 01 through time TA. that is, by 5:00 p.m. in this case, totaled. In this case, the amount of money and the number of items are totaled, and the operation goes to step g . In this step, this sales data (the above-mentioned total amount) stored in the Y register 78i> the register group 77 is transferred to the X register 78a and then to the I / O controller 31, where the data in the output Buffer registers (not shown) are stored. The I / O controller controls the printer section 13 based on the data stored in the output buffer register, and prints out the data, as in step Λ of FIG. 6 is shown. In step h , the one shown in FIGS. 9A and 9B are completed in addition to printing out the data. At the end of the data printout, the following number is printed out, as in step h 1 of FIG. 9 can be seen. At this time, the microprogram read out from the control section 62 sets the Chip designation data to specify memory 47 and X register 78a. Then, the micro program transfers the control portion 62 an operation command to the smart determination circuit 82. '■ - receipt of Operationsprogranuns reads the chip-provisions; Mining circuit 82 extracts the chip-determining data from X register 78a in order to generate a chip enable signal CE1 and to define memory 47. Thereafter, the control section generates an address code to set the memory locations of the seventeenth row and the; Columns 07 and 08 of the storage unit 91 to ξ: specify. After that, the address code is represented by the || Code generator 67 converted into a serial code | 3 The converted serial code is then passed to the adder / subtracter 71 via the gate 70.The data output by the adder / subtracter 71 is loaded into the A register 83, where it is converted into parallel data to be supplied to the addressing circuit 92. A ϊ read command fetched from the control section 62 by the command decoder 69 is provided in the addressing circuit 92. B. "3400", read out from the memory unit 91, and then the successor number is passed via the AND gate 75 and the OR element 76 to the X register 78a. The successor number read from the X register 78a is transferred to the output Buffer registers in the I / O controller 31 are transferred, together with "NO", as shown in FIG. 9 A is shown. The data in the output buffer register control the operation of the printer part 33 so that it prints the successor number "NO 3400" on the receipt. The successor number "3400". which was read from the X register 78a is fed to the adder / subtracter where it is increased by one. As a result of this addition, the successor number receives the value “3401”, which in turn is loaded into the memory sections of the seventeenth row and columns 08 and 07 within the memory unit 91.

When the printing operation of the sequential number is completed, the CPU 34 issues a paper feed command to the I / O controller 31. Accordingly, the paper is fed by N columns on the receipt as in step h 2 in FIG. 9A is shown.

Thereafter, the CPU 34 transmits a stamp printing command to the I / O controller 31 so that. as can be seen in step Λ 3 in Fig. 9A "Your receipt - thank you" is printed out.

Is the stamp printing is completed, the operation proceeds to the state "data printout," so that the central unit 34, a chip-determination for the timer 48, as well as addressing the date for the time memory 100 durchfut 'That is, Jie Center ^"one standardized 34 transmits a code that designates the chip of the timer 4f, i.e., the value "0010". 7 "to the X register 78a while simultaneously issuing an operation command or the chip designating circuit 82 through the control part 62 Receipt of the operation command *, the chip-determining circuit 82 reads the chip-determining code “0010” from the X register 78a and generates the chip selection signal CE2 in order to determine the chip of the timer 48.

Thereafter, the control section 62 transfers the address data through the gate circuit 70 to the address register 83 and to the adder / subtracter 71. The address data specifies the storage locations in the fourth row of the columns 06, B5 and BA. the

If)

Address data are transferred from the address register 83 to the addressing circuit 101 in the timer 48. In the address determination circuit 101, a read command, which is supplied from the control part via the command decoder 69, is set. Accordingly, the date on November 20, 1976 becomes e.g. B. "76 11 20", read from the memory locations of the fourth row of columns BS, B 5 and S 4 of the memory 100, as can be seen at step Λ5 in FIG. 9B. The data read out are transferred to the X register 78a via the gate 109, the AND gate 75 and the OR gate 76. The data read from the X register 78a is transferred to the output buffer register in the I / O controller, together with the segment code, as shown in step Λ 6 in FIG. 9B can be seen. The I / O controller 31 controls the printer part 33 in accordance with the data stored in the output buffer register to print out the data as shown in step Λ7 in Fig. 9B. The Bclegausgabevorgang takes place in the manner described above. The stamp printout "Your receipt - thank you" and the printing of data are carried out for the subsequent receipt slip. Therefore, the stamp printing and data printing are arranged in the upper part of the issued receipt

In the embodiment explained above, the time and data are set by setting the control switch 20 is set to Pr and by alternately pressing the amount key U and the non-adding key »j.«. However, year, month, day, hour, minute and second can be entered one after the other by using the amount key 11 and then the non-addition key are actuated for the same pulse. if the time for the total sum is set, hours and minutes can be entered continuously using the amount key 11, then by pressing the Γσ-grand total key 19f> is pressed, different from the example described above. Since the To total key 194 »is provided separately.

it can always be settable, regardless of the state that is set by the control switch 20. Will desired that the 7b grand total key 19f> is replaced by another key, the ST key 17 or another may be used on condition that the control switch 20 is in, for example the state Pr is switched.

In the above embodiment, the sales amount and sales count are within a predetermined Time added up each time the balance key 18 is pressed, however, is the storage space for Saving the total amount and the count provided for each department so that they can be added up be carried out for each department. In this case, the totaling is performed each time the Department key carried out In addition, there are memory spaces for storing the total amount and the counts are provided for each deal, the total amount and the count amount be added together for each transaction. In this case, the Sales key 16 a totaling carried out. There is also space to save the Total amount and counts provided for each employee key, so can for each employee the total sales and the count are added together within a given time. In this In this case, a total is carried out every time the register key, such as. B. the Complete key 16, the department key 12 or the sub-amount key 17 are operated.

The amounts and the counts can not only be within a certain time, but also within of the date can be added together. In this case, storage spaces are provided for Saving the total and counts of the predetermined date, and each time a Registration is done, the preset date is compared with the date of registration at the Store the total amount and the count accumulatively in a given memory location.

In addition 12 sheets of drawings

Claims (10)

Patent claims: 1. Electronic cash register, with one »· input keyboard, a memory having several memory locations for storing accumulated sales amounts, and a central processing unit for processing data entered via the keyboard, characterized by a time clock (48) counting time data, a time memory (iQOB) for Saving the time data, a time memory (100A) for storing predetermined time interval data entered using the input keyboard (10), a comparator (108) for comparing the counted time data with the time interval data stored in the time memory (100A) , the central processing unit (34) has a device which, as a function of the comparison result, writes data inputted after completion of a data entry into that memory location of the memory (47) which is determined by the comparison result 2. Electronic cash register according to claim!, Characterized in that the storage locations of the Memory include a memory area assigned to the time interval, which is used to store the Total sales amount depending on the comparison result, which is used at the conclusion of the Registration was obtained by pressing a balance key (18). 3. Electronic cash register according to claim 1, characterized in that the storage locations of the Memory "Itn allocated to time intervals Include memory areas that are used to store total sales amounts of respective departments depending on the comparison results obtained by comparing when registering by pressing Department buttons (12) takes place 4. Electronic cash register according to claim 1, characterized in that the memory locations of the memory are assigned to the time intervals Include memory areas that are used to store total sales amounts of corresponding business transactions depending on the comparison results serve which are obtained from the comparator when the cash register is operated by from sales keys (16). 5. Electronic cash register according to claim 1, characterized in that the timer (48) with a pulse generating circuit (105). a computing circuit (106). are formed a control part (HO) and the time memory (100), the memory (47) for storing sales totals, and the central processing unit (34) for adding up sales amounts on a single chip 6. Electronic cash register according to claim I. characterized in that the timer (48, 50) comprises a frequency divider (105) for dividing .on frequency He / iig <, signals, a computing circuit (106) for successive addition of Time pulse signals of the frequency divider circuit (105), the time memory (100) for storing time data of the arithmetic circuit (106) and a control part (110) for controlling the time counting operation of the arithmetic circuit (106). 7. Electronic cash register according to claim 5, characterized in that the time memory (100) has a memory area for storing time data for time intervals within which sales amounts are added up. 8. Electronic cash register according to claim 5, characterized in that the time memory (100) contains a memory area for storing an alarm time 9. Electronic cash register according to claim 5, characterized in that the time memory (100) has a memory area for storing a "flap" which indicates a result delivered by the comparator with regard to the current time and the time data 10. Electronic cash register according to claim 1, 2, 3, 4 or 6, characterized in that the time memory (100) has memory areas for storing the sales start time and sales end time