DE2744245A1 - Primary clock pulse correction circuit for plesiochronous TDM system - has comparator controlling VCO in phase locked loop and connected via dividers to two pulse adaptors - Google Patents

Abstract

The circuit for blending pulses into and out of a pulse sequence corrects the primary clock timing of a plesiochronous TDM system employing positive/negative stuffing. The incorrected clock pulses (f1) are passed to a first pulse adaptor that extracts these pulses on receipt of an extraction command (C-). The corrected clock pulses (f2) are applied to a second pulse adaptor that inserts these pulses on receipt of an insert command (C+). The outputs of both adaptors are freq. divided and compared (Pk). The result is used to control the phase-locked vco that generates the correct clock pulses.

Description

The invention relates to a circuit arrangement for

and masking out of pulses in a pulse train, especially for Purpose of clock correction of the primary clock of a plesiochronous time division multiplex system according to the positive-negative stuffing technique.

For the clock adjustment of plesiochronous multiplex systems exist two possibilities used in practice.

The so-called positive stuffing technique is used on the broadcast side made sure that the primary clocks by an amount above the frequency of the receiving side required primary clock. At the receiving end, single pulses are masked out the continuously faster rate than the required primary rate accordingly the separately transmitted clock adjustment information is slowed down to the correct value. Circuit arrangements that have the task of fading out pulses in the positive-stuffing technique solve are known. This also includes the use of an oscillator with a phase-locked loop (Phase Locked Loop) to recover the primary clocks from the multiplex clock for State of the art (telecommunications technology, 15 (1975) H. 2, pp. 56-58. VEB-Verlag Technik).

The second correction method does not require a specific clock increase on the sending side. With her every clock increase of the transmitting-side clock generator A special correction signal is also transmitted beyond the target cycle as with a cycle lowering below the target cycle.

This positive-negative stuffing technique "offers the advantage that on the one hand with it bit, word or frame-wise nesting is possible, and on the other hand at the transition the channels for the clock adjustment information on a synchronous network and the marking of the start of the superframe can be used for other tasks.

in the case of dcr "positive-negative stuffing technique", compared to d <r positive stuffing technique the more difficult task to be accomplished, not just individual ones Fade out pulses from a clock pulse sequence, but also from a transmission-side fade in negative clock deviation in the clock pulse sequence.

Two methods are known for solving this problem.

In the first method, an oscillator is used to prepare the clock assumed that must generate a multiple of the primary clock frequency. The Einfiig and the correction pulses are masked out at this high clock rate. These are very Fast Schottky TLt circuits are required, which are operated at their upper limit frequency Need to become.

Despite this effort, there is also a relatively high proportion of jitter higher clock adaptation frequencies available (DT-AS 20 23 656).

Another method requires a very complex circuit, to regain the clock with little jitter.

However, this circuit arrangement is in series connection multiple systems multiplexer-demultiplexer no longer usable (Bylstra, J.A .: A Technique for Smoothing Justification Jitter in Digital Systems with Low Justification Rates. Report No. 6982; Telecom Australia, Research Laboratories).

Based on the aforementioned prior art, it is the task the invention to specify a circuit in which in particular the insertion from individual clock pulses to the clock to be corrected almost just as easily lets how the fading out of clock pulses in the positive stuffing technique. This should the clocks recovered in this way have the lowest possible jitter and the circuit should not require too much effort.

This object is achieved by the circuit arrangement specified in the claim solved. By using two identical pulse adapters with a downstream Divider, one in the clock feed and the other in the feedback loop a phase control loop is switched on, the result is a very simple circuit, which can also be used for purposes other than clock correction.

With the circuit arrangement according to the invention, the fade-in command initially active pulse suppressed in the feedback circuit of the phase locked loop. the The phase-locked loop overcompensates this frequency reduction at its input, in which they set the output frequency f2 from the voltage-controlled oscillator increased by exactly one clock pulse.

The advantage of the circuit arrangement is that only pulses suppressed and no needle pulses have to be inserted into a Pularreihen and that a frequency that is many times higher is no longer required. The circuit arrangement works regardless of the frequency and the alternation of positive and negative Timing adjustment information; also works with the series connection multiple systems multiplexer-demultiplexer. The clock jitter is already few hertz (depending on the low-pass filter TP) is suppressed sufficiently so that no bit errors due to excessive jitter levels in the transmission equipment mr to be expected are. For the use of the circuit arrangement fitr the clock recovery is of Meaning that for multiplex systems 1st and 2nd order low-power Schottky TLL circuits which have low power consumption and large Allow degree of integration.

In the following the invention is based on a block diagram and two pulse diagrams explained in more detail.

Figure 1 shows a circuit arrangement for recovery in a block diagram of the plesiochronous clocks of the subsystems of a time division multiplex system of a higher order from the multiplex clock rm and the clock adjustment information C + or C-Die circuit arrangement according to the invention is the essential, but not the only part of the block diagram.

From the received multiplex clock fm is shown in the part of the Demultiplexer with the help of a first phase locked loop PLL 1 a clock frequency f1 is formed, which corresponds to the clock frequency of the multiplexer-demultiplexer system, if no stuffing commands have been sent, i.e. if the clock frequency f1 des Subsystem of 2.048 Mbit / s directly from the multiplex frequency fm of 8.448 Mbit / s can be derived. The first phase control level is not part of the Invention and is therefore only in a common circuit block PLL 1 schematically shown. It consists in a known manner of divider stages, which the multiplex clock frequency fm = 8.448 Mbit / s and the frequency of the associated quartz stabilized Divide the voltage-controlled oscillator to a common frequency. About one The voltage-controlled oscillator then becomes a phase comparator and a low-pass filter set to the synchronous frequency £ 1 = 2.048 Mbit / s of the subsystem the output of the phase control circuit connected pulse adapter 1 leaves the clock pulses fi pass unhindered until a fade-out command C- indicates that the clock frequency of the demultiplexer must be reduced. A clock pulse is then generated in the pulse adapter 1 turned off. This process is shown in the timing diagram in Figure 2, bottom line. over the divider 1, which divides the new clock frequency by the factor m and over a phase comparator PK with a subsequent low-pass filter TP in very low cutoff frequencies. a second phase-locked loop PLL 2 is now controlled. It exists alongside that already mentioned phase comparator PK and the low-pass filter TP with a very low cutoff frequency from a crystal-stabilized voltage-controlled oscillator VCO with a large capture range. The pulse adapter 2 with its divider 2 is now in the feedback loop of the phase locked loop PLL 2 between the voltage controlled oscillator VCO and the phase comparator PK looped in. In pulse adapter 2, something similar happens as in pulse adapter 1. Must the pulse adapter 2 the clock pulses f2 generated by the voltage-controlled oscillator VCO unhindered by. If the clock has to be increased (C +), as with the fade-out command, a Pulse deleted from cycle f2. This process is shown in Figure 3, bottom line. The pulse series f2 ', reduced by one pulse, becomes in the downstream divider 2 divided by the factor n.

At the phase comparator PK f1 '/ n and f21n become one another compared and control the phase-locked loop so that the masking of a pulse in the The feedback loop of the phase control loop increases the output frequency f2 of the voltage controlled oscillator VCO by one pulse.

The following table shows the dependence of the output frequency f2 on the clock frequency f1 of the subsystems and the clock adjustment information C + and C-. C- C + f2 0 0 = f1 0 1> f1 By deleting individual pulses in the direct path of the frequency f1 to be corrected to the phase comparator PK, a lower frequency f2 is set in the phase locked loop PLL 2 and by deleting individual pulses in the feedback branch of the phase locked loop between the voltage-controlled oscillator VCO and the phase comparator PK, a higher frequency is achieved f2 set. The pull range of the phase locked loop PLL 2 must correspond to the maximum possible frequency change of the subsystem.

The circuit arrangement according to the invention can be used anywhere where individual pulses have to be added to or removed from a pulse train.

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Claims (1)

Circuit arrangement for fading in and out of pulses in a pulse train Circuit arrangement for fading in and out of pulse n in one Pulse sequence, especially for the purpose of clock correction of the primary clock of a plesiochronous Time division multiplex system according to the positive-negative; pot technology, characterized that two identical pulse adapters with each, only suitable for masking out pulses a divider in series at each input of a phase comparator (PK) are switched so that the first pulse adapter controlled by the fade-out command (C) is in the clock feed of the uncorrected clock (f1) is switched on and in known Way a clock decrease causes the second, controlled by the fade-in command (C +) Pulse adapter in the feedback circuit one from the phase comparator (PK), one Low-pass filter (TP) with a very low cut-off frequency and one at the corrected clock frequency (2) vibrating voltage controlled oscillator (VCO) existing phase locked loop (PLL2) is switched on, so that the fade-in command in the feedback circuit initially caused a pulse to fade out the voltage controlled oscillator to one Increase the output clock frequency (f2) by one pulse.