DE2706964A1 - Electric synchronisation device for several drives - has input stage connected to pulse generator and to various actuators through logic circuits - Google Patents

Abstract

The motor drives are preferably intended for hoisting tackle. A control unit allocated to a motor, has an input stage connected to a pulse generator and acting as a pulse shaper. This input stage is connected through interlinked AND and OR circuits to several stores switching on and off delays and electromagnetic switches. Preferably the input stage has two pulse input lines for control inputs for selective coupling of a pulse generator of npn or pump, type. It has two pulse output lines one for the store AND circuit, and the other one for the store setting input of this AND circuit. The store output may be coupled to the second input of the AND circuit.

Description

"Electronic control arrangement for the

Synchronization of two or more motorized drives "The invention refers to an electronic control arrangement with which the synchronism of two or several motorized drives, especially on jacks, automatically controlled will.

Synchronization controls for drives and lifts are available in different Versions, e.g. from DT - PS 394 662, CH - PS 375 426 and DT - OS 2 157 758, became known.

The known synchronization controls, however, are not only susceptible to failure a large number of mechanically or electromechanically actuated contacts has the disadvantage on that they are only designed for a certain number of drives that are in practical use no longer changeable or adaptable to special circumstances is.

The object of the invention is to provide an arrangement for controlling the synchronization two or more motorized drives, in particular on lifting jacks, to create the under Avoidance of mechanical switching parts in a simple and safe way depending on the path the synchronism of the drives is monitored, compensation in the event of synchronism disturbance to the Synchronizes, monitors the joint travel of the drives, a synchronization control enables a change of direction of rotation and an automatic one Shutdown (shutdown) in the event of malfunctions within the drive system, whereby at any time from two to further drives depending on the operating conditions can be expanded.

A compact component should be provided as a control unit for each drive be that with the other s control unit # a simple and safe electrical Connection has.

According to the invention, this object is achieved by what is stated in the main claim Design features solved, with the design features listed in the subclaims advantageous and beneficial development of the features of the main claim and of the task solution are.

The subject matter of the invention does not only extend to the features of the individual claims, but also on their combination and on all described and details and features shown in the drawing.

The synchronization control according to the invention enables in s, c, 'erer simpler, yuna permanent automatic monitoring and adjustment of the synchronism two or more drives (lifting jacks), monitoring of the common journey (Running), a regulation of the synchronism when changing the direction of rotation and a shutdown in the event of malfunctions in the electrical switching elements or

in the entire propulsion system.

The synchronization control works depending on the path, i.e. for a certain Distance (stroke) a certain number of pulses must be registered in the control be, through which the synchronism is recorded or, if the synchronism is not synchronized, one or several drives stop the leading drives, and until all drives have covered the same eg and then the pulses can be entered into the control again from zero up to a maximum.

The synchronization control works without mechanical switching parts and without electromechanical counters, is therefore largely trouble-free.

A previously common copy counter is no longer necessary because the End positions can be entered directly into the control via limit contacts, and the even and odd numbers are stored directly via an input stage through memory (St 1 - 2 - 3 - impulse - pause - impulse).

The use of certain OR elements (o3) in the control are linked to each other, as well as the use of a certain switch-on delay (46) enables the function monitoring of the input pulse generator.

The use of the switch delay device (44, 45) means that a memory is not required for the extinguishing function in the primary control unit (system).

The synchronization control according to the invention can be carried out without great effort retrofitted in existing drive systems as well as in new systems be fully planned.

Without any additions, the system can be changed from two to any number of drives expand; all drives to be controlled have the same control boards equipped.

Furthermore, the synchronization control enables a simple one Single travel (only one drive is running) and an intended, regulated non-synchronism.

The drawing shows an embodiment according to the invention shown. 1 shows a circuit of two control units of the synchronization control, 2 shows an additional circuit of the synchronization control for changing the direction of rotation of the drives.

In Fig. 1 of the drawing, two interconnected control units sid (Control devices) 40, 40 'of the synchronization control according to the invention shown, the for the synchronization of two motorized drives such as lifting jacks, linders or other, in a vertical or horizontal or inclined direction a part (load, Slide) by means of a pulling or pushing element (spindle) moving machines, are provided.

The control unit 40 controls one drive (jack 1) and the second Unit.4o 'the second drive (jack 2).

D3 both control units 40, 40 'are constructed essentially identically are, in the following only one unit 40 and partly the second unit 40 ' and the same reference numerals are used for both units 40, 40 '.

The control unit 40 (40) has a pulse generator 41 which is connected to a Power supply 42 and is connected to an input stage 43 as a pulse shaper.

g This input stage 43 is interposed with one another linked and and or elements (their arrangement is described in more detail below is) with several, preferably three stores Sp 1 Sp 2, Sp 3, several, preferably three switch-on or switch-off delays 44, 45, 46 and electromagnetic switches 47.48 in connection.

The input stage 43 is with two input lines 49.50 with the Inputs 18,2o provided; depending on the design of the pulse generator 41 (npn or pnp) in the line 49 or 50 entered the pulse.

In the present example, the pulse generator 41 (npn): it is his Output 20 connected to input 20 of line 50 as a pulse line. 15th is the connection for the supply from the power pack 42 and 3o, 31 is zero volt.

The input stage 43 has two output lines, one alternately Give off impulse. The line 51 is connected to a line 53, on the one hand to the memory SP 1 (set input S) and on the other hand to a memory Sp 3 assigned And - element U 1 is connected, the output of which is connected to the set input (S) of the memory Sp 3 is connected.

The line 52 is connected to an AND element U 2 of the memory Sp 2; A line 54 runs from the output of the memory Sp to this AND element U 2 1 and the output of the AND element U 2 is connected to the memory Sp 2 (set input S) tied together.

A triple-or element ol is assigned to the memory Sp 1, the its output is connected to the memory Sp 1 (reset =).

A bridge 55 is at an entrance of the triple-or-link ol and to an input of a quadruple-OR element assigned to the switch 48 o2 connected.

From this bridge 55 a line 56 goes to a memory Sp 2 assigned and with its output connected to the memory Sp 2 (reset = R) Or - member o5, a second line 57 to an OR member o3 and a third Line 58 to a triple-OR element o4 of switch 47.

The two OR elements ol and o5 are connected to one another by a bridge 59 and the OR element ol is linked to the AND element U 1 by a further bridge 60.

The output of the memory Sp 3 closes with a line 61 to the Line 57 on and the output of the memory Sp 2 is through a line 62 with an input of an AND element U 3 in connection, from this line 62 in front of the AND element U 3 a bridge 63 to the third input of the Or - link o1 branches off.

All three memories Sp 1, Sp 2, Sp 3 are shared by a line 64 connected to the power supply 42.

A connecting line goes from the bridge 59 of the switching unit 40 65 to the bridge 59 of the control unit 4o 'and to this connecting line 65 a delay 44 is connected from each control unit.

To the AND element U 3 and to an And assigned to the memory Sp 3 - Member U 4 is used to set the memory Sp 2 and to meet the non-requirement in both AND terms U 3, U 4 when a signal arrives a 0-volt Leu do 66 connected.

The output of the AND elements U 3, U 4 of the control unit 40 is through one line 67, 68 each with an input of the AND elements U 3, 4 of the control unit 40 'and the output of the AND elements U 3, U 4 of the control unit 40' is connected by a line 69.70 with a retarder 44.45, from which the delay 44 is connected to the connecting line 65 and the delay 45 to a reset line 71 between the two memories Sp 3 of the two control units 40,40 'is connected.

The output of the OR element o3 of the control unit 40 is through a line 72 with an input of the OR element o3 of the control unit 40 'in Connection and the OR element o3 of the control unit 40 'is connected to its output through a line 73 to one of the two delays 46 of the two control units 40,40 'connect line 74, each delay 46 having a Line 75 is connected to one input of the two OR elements o4 and o2.

The switch 47 is used to switch on for the movement "up" or "Forward" and the switch 48 for "Down" or "Back".

The switch 47 is connected to an AND element U 5 through a line 76 with the Control input 17 or 10 and through a line 77 lat the output of the AND element U 5 in connection.

The switch 4 ° is through a line 78 to the output of an AND - Link U 6 connected, which is connected by a line 79 to the control gears 19 or 14 is connected.

An OR element o4, o2 assigned to each switch 47,48 is connected to the second input of the AND element U 5, U 6 connected by a line 80, 81 and the OR element o4 is connected to the line 75.

The second input of the AND element U 4 is through a branch 82 connected to line 57.

Synchronization: By pressing the "Open together" button, the switch 47 via its control input t7 or 1o and the AND element U 5 switched on and the drive is running.

In the drawing Fig. 1, the control for two jacks is shown, so that both switches 47 are switched on when the "Open together" button is pressed will.

The pulse generator 41 Uer two control units 40,40 'are through the Control input 18 or 20, in the present case by 20, a pulse over the line 50 to the input stage 43, which forms the corresponding pulse and converts it as 1.

Impulse through line 51 into line 53 gives - the impulse causes the operation "set" in memory Sp 1 and is also at the same time on the AND element U 1, which, however, still remains inoperative.

The set memory Sp 1 gives a signal via line 54 the AND - element U 2 of the memory Sp 2.

Storage tank Sp 1 is set and storage tank Sp 2 is in the position in both control units 40, 40 ', from the pulse generator 41 in turn a pulse in enter the input stage 43, which converts the pulse and now it as the 2nd pulse through the line 52 to the second input of the AND element U 2 emits - there on This AND - term U 2 already stood before the 1st impulse, the lack of demand is through the 2nd impulse fulfilled and the AND element U 2 sets the memory Col 2.

The memory Sp 2 outputs a signal via its output line 62 the And - member U 3, its lack of demand by the 0 - volt line as well is satisfied.

The output line 67 of the AND element U 3 gives the signal to the And - element U 3 of the control unit 40 ', in which also the signal from the memory Sp 2 of the control unit 40 ', so that the output line 69 of the AND element U 3 via the delay 44 (block 2) and the line 65 the memory Sp 2 of the control unit 40 'set back.

At the same time, the signal after the delay 44 is on the line 71 and 65 run to reset the memory Sp 2 of the control unit 40, so that both memories Sp 2 are reset.

In addition, the signal from memory Sp of the control unit has at the same time 40 from the output line 62 via the rce 63 and the der - element ol the memory Sp 1 reset.

Now the zinUangsstufe 43 is again the 1st impulse to set the Memory Sp 1 and for preparing the memory Sp 2 and then the 2nd impulse for setting the memory Sp 2 and for resetting the memories Sp 1 and Sp 2.

This setting and resetting of the memories Sp 1, Sp 2 of both takes place Control units 40, 40 'evenly, then there is synchronism.

Synchronization fault: When jack 1 moves forward and with it the accumulator Sp 3 is set by switching unit 40 - this can happen because the AND element U 1 is the signal from memory Sp 2 in line 6c and by the pulse in line 53 and the requirement is met - the signal from memory Sp 3 only up to the And -'-member U 4 of the control unit 40'- here the undoing becomes not fulfilled, since memory Sp 3 has not yet been set by control unit 40 '.

As a result, the signal goes from memory Sp 3 to control unit 40 above the line 57 and the bridge 55 to the memories Sp 1, Sp 2 of the control unit 40 and resets it and at the same time this signal runs from the bridge 55 into the OR element o4 (o2) and thereby the switch 47 (48) is switched off and the drive is stopped.

Compensation for synchronism: The advancing jack 1 is switched off and the jack continues to run until the memory Sp 3 of the control unit 40 ' has been set. Memory Sp) then sends its signal via lines 6t, 75 to the AND element U 4, on which the signal from the memory Sp 3 of the control unit 40 is pending, so that the AND requirement is fulfilled at this And member U 4 and the signal from the AND element U 4 on the one hand via line 70, the delay 45 and the line 71 for resetting the memory Sp 3 from the control unit 40 ' and on the other hand behind the delay 45 via the line 71 to the memory Sp 3 of control unit 40 is running and also resets this.

Now, in both control units 40, 40 ', all memories Sp 1, Sp 2 and Sp 3 have come and also been reset and now both drives can start up again and their synchronization is achieved by setting the memory at the same time Sp 1, Sp 2 monitored.

Shutdown (stopping the jacks): Due to a malfunction in one Elektr.Teil is, for example, the memory Sp 3 of the control unit 40 'continuously set (so he always receives setting pulses), so that the jack 2 is constantly runs.

However, since there is no signal from the memory Sp 3 of the control unit 40, the AND requirement on the AND element U 4 of the control unit 40 'is not met and the signal from memory Sp 3 goes over lines 61 and 57, through the OR - Member o3, the line 73 in the bridge 74 of both switching units 40,40 'and through whose delay 46 in line 75 via the OR elements o4 (o2) and switches the Switch 47 (48) of both control units 40, 40 'so that both Lifting jacks 1,2 are stopped.

Monitoring of the joint journey: Is a lifting jack running, for example Bock 2 does not start due to a fault in an electrical part when switching on, like this the storage tanks Sp 1, Sp 2, Sp 3 are set one after the other in the case of lifting jack 1. However, since the set memory Sp 3 of the control unit 40 the undrequirement at the AND element U 4 of the control unit 40 'due to the non-set memory of block 2 do not meet the signal coming from the memory Sp 3 is sent via the lines 61 and 57 the OR elements o4 (o2) and switches off the corresponding switch 47 (48), so that the jack 1 is stopped and the malfunction on the jack 2 can be eliminated can.

At 85, a further control unit is referred to, which in Fig. 2 of Drawing is shown and for the change of direction of rotation and the synchronization control is integrated in a control unit 40 or 40 '. For every group of jacks that is connected to a common synchronization control is only one control unit 85 required.

This control unit 85 is composed of two memories Sp 4 and Sp 5 and a monoflop 86 together, for example the memory Sp 4 for right-hand rotation and the memory Sp 5 is designed for counterclockwise rotation (or vice versa).

To the memory Sp 4 is a set line 87 with terminal P2 and on the memory Sp 5 is connected to a set line 88 with connection P1 and the outputs both memories Sp 4, Sp 5 are connected to one another by a bridge 89, of which a line 9o branches off to the monoflop 86, which has an outgoing line 93 with a connection P3 owns.

Both memories Sp 4, Sp 5 are each through one from the output to the reset input running line 91,92 alternately connected.

This control unit 85 is connected to the connections with its connections P1, P2, P3 P1, P2, P3 of the control unit 40, (40 ') connected.

When changing the direction of rotation of the drive from "Up" to "Down" or vice versa both drives of frame 1 and frame 2 are deliberately or automatically stopped and then reversed.

For example, if Bock 1 has now run higher, so that at Bock 1 memory Sp 3 has already been set, but memory 2 has only been set for block 2, then the control unit 85 comes into operation, namely in which via the memory Sp 4 or Sp 5 (depending on the direction of reversal) the monoflop 86 detects the preceding memory Sp 3 clears from block 1 to 0, so that the previous block 1 becomes the follower will.

Now Bockl sends 3 impulses when going down, namely from memory Sp 1 to memory Sp 3 off, while Bock 2 only has one pulse, namely from memory Sp 2 to storage Sp 3, so that afterwards both blocks 1 and 2 are on the same again Height in their movement and synchronization by setting all memory Sp 1, Col 2, Col 3 is reached.

The connections 4,6 of the control units 40,400 are reset inputs, which are connected to the line 64 and a zero - setting the memory Sp 1, Enable Sp 2, Sp 3; This zero setting option means that a single trip is also possible each drive (lifting jack) possible by deactivating the synchronization control.

Connections 5 and 7 of the control units 40, 40 'are used to lock the entire system and enable the connection of limit switches for the travel limitation.

The synchronization control provided in Fig. 1 is for 2 jacks intended.

Should several jacks, e.g. 3, 4 or 6, as a group (System) are connected to the synchronization control, so forms the control unit 40 the controls for the first. and the control unit 40 'controls the last block and between these two control units 40,40 'is for each additional A control unit 40 is connected to the desk and all control units are connected to one another connected to the synchronization control.

The individual electr. and electronic components of each control unit 40, 40 'with lines are fixed on a control board 94 so that each control unit forms a complete component.

It is within the scope of the invention, the memory Sp 1 - Sp 3 also by to replace a counter with a decoder or a shift register.

Claims (1)

Claims 1) Electronic control arrangement for synchronism two or more motorized drives, in particular on lifting jacks, characterized in that that each control unit (40, 40 ') assigned to a drive motor with one a pulse eber (41) connected input stage (43) as a pulse shaper and this input stage (, J under bv: isch circuit of interlinked and and Or elements (U1 to U6 / 01 ois o5) with several memories (Col 1 to Col 3), On and off delay devices (44,45,46) and electromagnetic switches (47,48) connected is. ) expensive arrangement according to claim 1, characterized in that the Input stage (43) .wit two pulse input lines (49,3c) -it the control inputs (18,20) Provided for optionally connecting an npn or pnp pulse generator (@ 1) and is designed with two pulse output lines (51,52), of which the line (51) to one with the set input of the memory (Sp 1) and one input of the memory (Sp 5) associated and uliedes (U1) connected line (53) connected and the line (52) to an input of an ae memory (p 2i associated AND element (U2) is performed. 3) control arrangement according to claim 1 and 2, characterized that the output of the memory (Sp 1) via a line (54) to the second input of the AND element (U2) of memory (Sp 2) is connected and the reset input of the memory (Sp 1) is preceded by an OR element (01) which is connected via a bridge (6c) rit the second input from the AND element (U1) and over a second bridge (55) with an input of an OR element (o5) assigned to the memory (Sp 2) and two switches (47,48) associated OR members (04.02) connected is 4) control arrangement according to claims 1 to 3, characterized in that the output of memory (Sp 2) through a power (62) with an input of a And - member (U3) is connected, from which a line (67) to the AND - member (U3) the control unit (40 ') and the output of this AND - element (U3) over a line (69) and a delay (44) to the OR elements (o1, o5) of memory (Sp 1, Sp 2) of the control unit (40 ') runs. 5) control arrangement according to claims 1 to 4, characterized in that that the two OR elements (o1, o5) are connected to one another by a bridge (59) and a connecting line from the memory output line (62) to the bridge (60) (63) is branched off. U control arrangement according to claims 1 to 5, characterized in ee; daa from the OR link bridge (59) of the control unit (40) over a delay (44) a signal line (65) to the link bridge (59) of the control unit (40 ') is placed. 7i control arrangement according to claims 1 to 6, characterized in that da3 the output line (61) of the memory (Sp 3) to one of the bridge (55) outgoing Line (57) is connected to an OR element (o3) and another Line (82) runs to an AND element (U4). 8) control arrangement according to claims 1 to 7, characterized in that that the AND element (U4) of the control unit (40) and its output line (68) is led to the second input of the AND element (U4) of the control unit (40 '), that with its output line (70) via a delay (45) and a line (71) connected to the reset input of memory (Sp 3) of the control unit (40 ') is. 9) control arrangement according to claims 1 to 8, characterized in that that the output line (72) of the OR element (o3) the control unit (40) is led to the OR element (o3) of the control unit (40 '), the output line of which (73) to a connecting line (74,75) between the OR elements (c4, o2) of both Control units (40, 40 ') with retarders (46) inserted therein is connected. 10) control arrangement according to claims 1 to 9, characterized in that that the reset line (71) of the memory (Sp 3) of the control unit (40) via each a delay (45) with the reset input of the memory (Sp 3) of the control unit (40 ') is connected. 17) control arrangement according to claims 1 to 10, characterized in that that a switch (47) of each control unit (40, 40 ') as a switch for the movement "On" or "Forward" and the other (48) for the movement "Down" or "Back" is provided and each switch (47, 48) has a AND - element (U5, U6) connected to a control input (1?, 1o / 14,19) and to an OR - Link (o4, o2) is connected. 12) Control arrangement according to Claims 1 to 13, characterized in that that to the two AND elements (U3, U4) of the control unit (40) a 0-volt line (66) is connected. 13) control arrangement according to claims 1 to 12, characterized in that that at connections (P1, P2P3) of a control unit (40 or 40 ') one when the direction of rotation is changed the control unit (85) regulating the synchronization with its connections (P1, P2, P3) is connected, which is made up of a clockwise memory (Sp 4) with the set Connection (P2), a counterclockwise memory (Sp 5) with the set connection (P7) and one through a line (9o) to an output bridge (89) of both memories (Sp 4, Sp 5) connected monoflop (86) with the connection (P3) composed, both Memory (Sp 4, Sp 5) alternately with one another through a reset line (91, 92) connected 0 14) control arrangement according to claims 1 to 13, characterized in that each control unit (40, 40 ') has control inputs (4,6) for resetting the memory (St 1, St 2, St 3) to zero, control inputs (5,7) to block the synchronization control and control inputs (4,6) for the jack - Single trip is equipped. 15) control arrangement according to claims 1 to 14, characterized in that that each control unit (40,40i) is designed as a compact component and thereby the electrical components (41, 42, 43, Sp 1 to Sp 5, 44, 45, 46, 47, 48, 86, o1 to o5, U1 to U6) and their electrical connecting lines are arranged.