DE2705757C2 - Dynamic read-write memory - Google Patents

Description

(a) two of the memory cells (Tr, Cs) are arranged symmetrically next to one another between two data lines (DL) ,

(b) the gate electrodes (23Λ, T3B) of the MOS-FETs (TrI, Tr2) of each pair are connected to one another by a second conductor (23) which is connected to the capacitor electrodes (22/4. 22ß ^ and a first conductor ( 22) jo and du. Cn an insulating layer (30) is arranged separately from this,

(c) for each memory cell pair (Tr, Cs) a single contact hole (26) ei ^ he the memory cells overlapping and address lines (27, removing insulating layer (25) belongs, which the associated address line (27, AL 1) with the second conductor ( 23) and the gate electrodes (23 / 4,23S; connects.

2. Dynamic read-write memory according to claim 1, characterized in that the side ·? The distance between the gate electrodes (23Λ, 235; and the capacitor electrodes (22/4, 22B) m of each memory cell has a dimension of the order of 1000 Å.

3. Dynamic read-write memory according to one of claims 1 to 2, characterized in that that the second conductor (23) consist of polycrystalline silicon. so

4. Dynamic read-write memory according to one of claims 1 to 3, characterized in that that in each memory cell pair the capacitor electrodes (22/1, 22fl) as parts of the only one first conductor (22) are executed.

5. Dynamic read-write memory according to one of claims 1 to 4, characterized in that the contact hole (26) through which the second conductor (23) is connected to the address line (27, AL I), in the axis of symmetry memory cells (Tr, Cs) belonging to the memory cell pair are arranged.

6. Dynamic read-write memory according to one of claims 1 to 5, characterized in that that the second capacitor electrode and the other electrode of the MOS-FET's through an inversion layer (28,29) are formed in the semiconductor substrate (24).

7. Dynamic read-write memory according to one of claims 1 to 5, characterized in that that the second capacitor electrode and the other electrode of the MOS-FET's through the diffusion are formed by dopants in the semiconductor substrate (24).

8. A method for producing a dynamic read-write memory according to one of claims 1 to 7, characterized in that the memory cells (Tr, Cs) in pairs with common, side by side on the semiconductor substrate (24) between the gate electrodes (23 / 1, 235) of the MOS-FEPs (TrI, TrI) provided first capacitor electrodes (22/4, 22B) are formed, and that the gate electrodes (23/4, 23S; of the MOS-FETs of each pair are formed as a common conductor, of which the gate electrodes (23Λ 23B) connecting the central region is guided like a bridge and isoliertjiber the capacitor electrodes (Z2A, 22B), and that of (23Λ 23 B) having conductors (23) covering the gate electrode with a contact hole (26) having insulation (25) through which the conductor (23) is contacted with the address line (AL, 27).

9. The method according to claim 8, characterized in that the capacitor electrodes (22Λ 22B) temporally before the gate electrodes (23Λ, 23 B) of the MOS-FETs are formed that the surfaces of the outer ends of the capacitor electrodes (22/4, 22B) in an insulating layer are converted, and that the second conductor (23) forming the gate electrodes are formed laterally adjacent to the converted end regions of the capacitor electrodes.

10. The method according to claim 9, characterized in that the insulating layer resulting from the conversion of the end regions of the capacitor electrodes (22/4, 22B) is formed with a thickness of approximately 100 Å.

11. The method according to any one of claims 8 to 10, characterized in that the capacitor electrodes (22Λ, 225) of a memory cell pair (Tr, Cr) are formed together as areas of a conductor (22).

12. The method according to any one of claims 8 to 11, characterized in that the gate electrodes (23/4, 23A) in each memory cell pair (Tr, Cr) are produced together with the second conductor (23) and are essentially in the plane the capacitor electrodes (22Λ, 22ß) are located above the semiconductor substrate (24).

13. Verfahrennach one of claims 8 to 12, characterized in that to form the Gate electrodes (23/1, 23fl) of the conductor (23) made of polycrystalline Silicon is evaporated.

The invention relates to a dynamic read-write memory on one equipped with MOS FETs Semiconductor chip of a first conductivity type with a multiplicity of data lines which are in the substrate are formed as doped diffusion layers of one of the first opposite conductivity, with a plurality of address lines and a plurality of Eiri Tränsistör memory cells each one Have capacitor for storage and a MOS-FET for input and output of the information, wherein

a first capacitor capacitor opposite the Semiconductor substrate is separated by a thin insulating layer and one of the electrodes of the FET with a Daicnleitung is connected, while the other electrode in the vicinity of a second capacitor electrode is provided, and the gate electrode is connected to one of the address lines.

In general, the areas occupied by the individual memory cells of a read / write memory constructed on a semiconductor substrate take up almost the entire area of the semiconductor chip. In the latest memories created according to the MOS principle, a structure known as a dynamic one-transistor memory cell system has been used in many cases to increase the memory capacity. In memories structured in accordance with this system, the space occupied by a single memory cell is small and in the Au ain Building simple. The bits each provided for one memory cell "consists ehtspre to IEEE Journal of Solid-State Circuits, Vol SC-1 is the 320 8, No. S, Okiober 1973.5 310-323, Fig, of a transistor... and a capacitor.

One made of just one transistor and one The existing capacitor memory cell has a MOS-FET for the input and output of the information and a capacitor connected in series between the MOS-FET and a voltage source for information storage. An address line is connected to the gate electrode of the MOS-FET. A data line is connected to a first electrode area of this transistor. The ones from Transistor off controlled input and output of the data bits is through the charging and discharging of the Condenser accomplished.

According to the methods known heretofore, manufacturing a one-transistor memory cell includes the following Single steps:

The creation of a gate electrode from polycrystalline silicon belonging to the MOS-FET over two diffused .. electrode areas of a semiconductor substrate, one of these electrode areas being connected to the data line. the by diffusion has been fabricated from coating agents into the semiconductor substrate;

forming a capacitor electrode by forming an insulating layer near the polycrystalline silicon of the MOS-FET on the semiconductor substrate between the electrode and the semiconductor substrate;
and finally the application of a high voltage to the electrodes of the capacitor, whereby an inversion layer is formed in the semiconductor substrate which forms both the other electrode region of the transistor and the second electrode of the capacitor; an address line made of aluminum disposed over the insulating layer is connected to a contact part of the gate electrode.

This connection between the address line and the gate electrode is made through a to this electrode leading contact hole made so that for each

Furthermore, in this manufacturing method, the gate electrodes of the MOS-FETs and one each Electrode of capacitors made in the same operation, by first covering the entire surface a layer of polycrystalline silicon is applied, and the electrodes are then etched be exposed again. This means that there is a correspondingly clean separation between the gate and the Capacitor electrode is guaranteed, there must be a distance between the two electrodes after the etching process of at least 5 μηι be present, which is the lowest with the currently given etching technique, below Using a mask is achievable distance. This relatively large distance between the electrodes within the memory cells further limits the packing density that can be achieved in the memory.

It is already known to increase the packing density, by forming a transistor below the associated capacitor (IBM Technical Disclosure Bulletin, Volume 15. No. 12 of May 197Γ Seiter, 3585/6). and since the extension of the capacitors Securing the minimum required capacity is greater than that of the transistors is in DE-OS 27 05 503 taught to provide two capacitors one above the other. However, it proves to be disadvantageous here that the transistors, which are to be kept small per se, by the formation and contacting of their gate electrodes still require a considerable amount of space, and that the advantage of the denser packing de? Capacitors, even if a central capacitor electrode is common to the capacitors arranged one above the other is, by an increased number of layers formed one above the other on the semiconductor substrate and thus an increased number of processing steps is bought, which in turn increases the risk of formation of Increase scrap.

The invention is therefore based on the object. a generic dynamic write-read speuher short access time without complicating the structure due to a small footprint with increased storage capacity at the same time, so that the integration and packing density are strong increase and its manufacturing process large production quantities guaranteed with low failure. It is also from the IEEE Journal of Solid-State Circuits, Vol. SC-8, No. 5, October 1973, left column of p. 312, known to reduce the space requirement of a memory cell to contact data lines with source zones for the FETs of two memory cells are effective. The desired extensive reduction in the area required by a storage cell however, this does not achieve this.

The task is solved by adding two of the Memory cells arranged symmetrically next to one another between two data lines, the Gate electrodes of the MOS-FETs of each pair are connected to one another by a second conductor which over the capacitor electrodes and a first conductor connecting them as well as through an insulating

Memory cell, a contact hole is required If now _{m sc} hj _c ht is arranged separately from this, and by the storage capacity per chip is increased, a single Kont.aklloch • grows _to j _edem memory cell pair uch the number of contact holes, and the _one Jj ₆ memory cells overlapping and address semiconductor chip is with correspondingly larger dimensions _e i _obligations bearing insulating heard that select the "Ungen. However, if the packing density _2uge hearing address line can be improved with the second conductor and, the contact holes must _FT5 connects _the gate electrodes By this arrangement, smaller dimensions are executed, thereby _{[es st mö} possible. a dynamic read-write memory, the production quantity -J decrease by increasing the _{Auscher with increased} capacity and a relatively simple shot,. . Structure rjlatzsDarend on a single semiconductor

Build up chip. It was proposed in DE-AS 26 19 849, comb-like between data lines to arrange mutually penetrating and alternately connected to the two data lines memory cells. Although this mutual crackdown gives the appearance of more favorable land use, is it is necessary to have relatively intricate contact holes in each case with two memory cells that are jointly assigned Shapes of the gate electrodes and the conductor connecting them to be provided so that the possible reduction the space requirements are unfavorable limits. The space required is further reduced, when the lateral distance between the gate electrodes and the capacitor electrodes in each memory cell has a dimension on the order of 1000 Å. A simple structure is achieved when the second conductors are made of polycrystalline silicon. It was recognized as being useful in each Storage cell pair the Kondeiisäioreiektroden ais To carry out parts of the only first conductor. The contact hole through which the second conductor is connected to the address line. in the axis of symmetry of the memory cells belonging to the memory cell pair. The production is facilitated by the second capacitor electrodes as well as the respective other electrode of the MOS-FETs are formed by an inversion layer in the semiconductor substrate. Defined areas can be created by adding the second capacitor electrodes and dip each other's electrode MOS-FETs are created by the diffusion of dopants into the semiconductor substrate.

The generic dynamic read-write memory can be easily produced by forming the memory cells in pairs with common first capacitor electrodes provided next to one another on the substrate between the gate electrodes of the MOS-FETs, and by having the gate electrodes of the MOS-FETs of each pair as one common Conductors are formed whose central region connecting the gate electrodes is guided like a bridge and insulated over the capacitor electrodes, and by covering the conductor having the gate electrodes with an insulating layer having a contact hole through which the conductor is contacted with the address line. An increase in the packing density is achieved by forming the capacitor electrodes ahead of the gate electrodes of the MOS-FETs, by converting the surfaces of the outer ends of the capacitor electrodes into an insulating layer, and by laterally connecting the conductor forming the gate electrodes to the converted end regions of the capacitor electrodes is formed. It has been recognized as expedient that the insulating layer resulting from the conversion of the end regions of the capacitor electrodes is formed with a thickness of approximately 100 Å. It has been shown to be advantageous to jointly form the capacitor electrodes of a memory cell pair as areas of a conductor. A simple method is achieved in that the gate electrodes in each memory cell pair are produced together with the second conductor and are located essentially in the plane of the capacitor electrodes above the semiconductor substrate. It was recognized as worthy of imitation to vaporize the gate electrodes and the second conductor made of polycrystalline silicon that connects them.
In detail are the features of the invention

on the basis of the following description of exemplary embodiments in conjunction with the illustrative embodiments Drawings explained. It shows here

Fig. 1 is a circuit diagram for a memory cell pair of One-transistor ^ memory cells,

F i g. 2 shows a plan view of the arrangement of the in FIG. 1 illustrated memory cell pair, F i g. 3 shows a section along the line ΙΙ-ίΙ of FIG. 2, 4a to 4f are sectional views showing the successive operations in the manufacture of the in the F i g. 2 and 3 illustrate the read-write memory shown,

Fi g. 5 shows a section through a modified embodiment a read-write memory, and

6 and 7 alternative arrangements of read-write memories.

1 shows two memory cells, each with a transistor Tr and a capacitor Cs . One of the lead electrodes of the capacitors Cj ί and Cs 2 are jointly connected to the terminal of the voltage source T. The other electrodes of the capacitors CsI and Cs 2 are each connected to one of the electrodes of the associated transistors Tr 1 and Tr 2. The gate electrodes of the transistors are connected together to an address line AL 1. The other electrode of the transistor TrI is connected to the data line DL 1 and that of the transistor Tr 2 is connected to the data line DL 2 . The address line AL2 also shown already belongs to the next JO memory cell pair

The transistors and capacitors shown symbolically in FIG. 1 are in a semiconductor substrate incorporated. A very large number of pairs of memory cells are arranged on the semiconductor chip. which are connected to the various address and data lines.

F i g. 2 and F i g. 3 now show, in plan view and in section, the structure and construction of the memory cell shown in FIG. In the semiconductor substrate AO 24, the two diffusion layers 20 and 21 form, which have a conductivity opposite to the conductivity of the substrate, which is shown in FIG. 1 shown data lines DL1 and DL 2. These diffused layers form the electrode areas for the two MOS-FETs. A first conductor 22 is arranged on the semiconductor substrate 24 separated by a silicon oxide layer or by another insulating layer 25. The ends 22A and 22ß are each designed as an electrode of the capacitors CSl and Cs 2. The ends 23Λ and 23ß of a second conductor 23 are m in the same plane as the ends 22Λ and 22ß of the first conductor 22; but are insulated from them by thin insulating layers The part of the second conductor 23 connecting the ends is arranged above the first conductor 22 and insulated from the latter. The end parts 23A and 23ß of the second conductor 23 form the gate electrodes of the MOS-FETs Tr 1 and Tr 2 The conductors 22 and 23 are preferably embodied as layers of polycrystalline silicon. At a contact hole 26, the second conductor 23 is connected to a metal layer 27 which the address line AL 1 of FIG. 1 forms

The regions of the polycrystalline silicon layers 22 and 23 shown in FIG. 2 with dashed lines show that the insulating layers arranged under these areas are made thinner than in the other areas, and they each form the capacitors Cs and the MOS-FETs Tr.

The inversion layers 28 and 29 are produced by applying a high voltage to the first conductor 22 in the surface of the auxiliary substrate 24. I) iesu inversion layers each form the second electrodes of the capacitor Cs i and the capacitor Ci 2 as well as the other electrodes of the transistors TrA and 7> 2. The capacitance of the capacitors is thus determined by the inversion layers, by the thin insulating layer and by the ends 22A and 22ß, while the transistors are determined by one of the data lines 20, 21, by one of the inversion layers 28 and 29, and by the end part of the conductor 23 formed gate electrodes are formed.

The lateral distance between the gate electrode of a memory cell and the corresponding capacitor electrode is very small. These two electrodes are only separated from one another by a thin insulating layer, which reduces the area per memory cell and increases the packing density on the semiconductor chip. The gate electrodes of the two memory cells are also connected to the address line Ali only through a single contact hole 26, as a result of which the number of contact holes in the chip is reduced to half the number of memory cells.

The production of the Semiconductor chips explained. As shown in FIG. 4a can be seen, the insulating layer 25, for example made of SiOj, made on the surface of the semiconductor substrate 24. The parts of this insulating layer 25, which are above the locations for the transistor, for the capacitor and for the doped diffusion layer 20 are arranged are made thinner than the remaining areas of the insulating layer 25. Then it happens Application of the first conductor 22, for example by vacuum vapor deposition of a polycrystalline silicon layer. which is then partially removed again by etching, so that only the necessary parts remain. In order to make this layer 22 conductive, dopants are diffused in after the vapor deposition, or else already doped polycrystalline silicon is used

In Figure 4b, the conductor 22 is using the C.V.D. process or a similar process with an insulating layer 30 covered, in this way, the stray capacitance of the arranged on this insulating layer Decrease wiring. A region 31 of the semiconductor substrate 24 in which the transistor is manufactured is to be, as well as one end of the conductor 22 remain uncovered.

The entire surface is now oxidized by heating, so that, as shown in FIG. 4c shows the exposed surface and the end of the conductor 22 and the surface 31 of the substrate 24 each with thin insulating layers 32 and 33 are coated, so that the entire surface of the semiconductor substrate is covered with insulating material

In Figure 4d, the production of the second conductor 23 is shown. Polycrystalline silicon is applied to the semiconductor chip using the vacuum vapor deposition process and removed again in certain areas by etching.The parts that remain after the etching form the gate electrode 23/4 and the connecting piece that is supposed to establish the connection to the address line AL . The conductor 23 does not protrude the part ass semiconductor substrate 24 in which the data line DL 1 is to be created.

In FIG.4E of the conductor 22 as a mask, by using the thin insulating layer away above the location of the substrate in which the Dalcnleitung Dl I are prepared should there be rungsstöffe from the free left the surface of the I-lulblciier Substruls 24 from Dcjtie diffused, the generate opposite conductivity compared to the conductivity of the semiconductor substrate 24. The doped diffusion layer 20 forms the data line DL 1 and an electrode of the MOS-FET Tr. The diffused into the substrate

To increase the conductivity of the second conductor 23, dopant is also diffused into the surface of the layer. According to FIG. 4f, the entire surface is then covered with an insulating layer 25 using the chemical vapor deposition process or a similar process. The contact hole 26 leading to the conductor 23 is worked into this layer. Electrically conductive material, for example aluminum, is then applied so that the address line AL 1 is produced, which is electrically connected to the conductor 23 through the contact hole 26. The memory cell is thus completely manufactured.

In the F i g. 4a to 4f is only one half of the Memory cell pairs shown. In the illustrated In this way, the other memory cell shown in FIG. 4 is also produced at the same time. Also will the Conductors 22 and 23 described as layers of polycrystalline silicon. The layer of the first conductor 22 but can be made of any material, for example aluminum, if

JO whose surface is converted into an insulating layer can be, the second conductor 23 can be made of any conductive material.

From the description given so far, it can be seen that the electrodes of the capacitor Cs and des

J5 transistor Tr in each memory cell are formed by the ends of conductors 22 and 23, respectively. Between these electrodes there is an insulating layer that only needs to be 1000 Å thick. This insulating layer is made from the layer of the first conductor 22

"to made of polycrystalline silicon by conversion. The distance of 5 μηπ necessary for the separation the capacitor and transistor electrodes were previously required, are no longer required, whereby a space allocation within each memory line

waste on the semiconductor substrate is eliminated, d. i.e., that occupied by each memory cell Surface area is reduced and the packing density is increased.

In the modified version according to FIG. 5 is a shallow impurity layer 34 with a comparison to the conductivity of the semiconductor substrate 24 oppositely directed conductivity at the particular for the capacitor Cs 1 point in the surface of the semiconductor support layer 24 diffused in the polycrystalline layer 23 forms a part of this capacitor Cs 1. Due to the diffused Doping layer 34 does not need the voltage applied to conductor 22 to have the maximum value.

A possible variant in the positional arrangement of the memory cells shown in FIG. 2 with regard to the data lines DL and the address lines AL is shown as a plan view in each case in FIG. 6 and FIG. 7. In the arrangement according to FIG. 6, the memory cells are on both sides of the data lines DL arranged in parallel to one another. Each memory cell of each memory cell pair arranged between the data lines DL 1 and DL 2 is on one of these data lines

guided. The address lines AL 1 and AL 2, which cross the data lines at right angles, are arranged above the memory cell pairs. In addition, because the gate electrodes of the transistors belonging to the memory cell pair are produced on a common polycrystalline silicon layer, the electrical connection of an address line to two memories can be produced via a single contact hole 26.

in FIG. 7 the pairs of memory cells are only arranged on one of the sides of the data lines DL 1 and DL 2, DL3 and DL 4. In this case too, the data lines are crossed at right angles by address lines AL , and the two memory cells of a memory cell pair are electrically connected to an address line via a single contact hole 26. Here, too, it can be seen that, compared to the number of memory cells, the number of contact holes is only half as large as is the case with the previously known read-write memories.

Since, as already described, the contact between an address line AL and the gate electrodes is established above the capacitor and its area is larger than that of the gate electrode, larger contact holes can be used compared to the contact holes of known memory cells without increasing the chip dimensions. This greatly improves production performance because, despite the high degree of integration, very small contact holes are not required.

So far, each data line has been designed as a doping layer diffused into the semiconductor substrate and each address line is described as a metallic conductor machined into the top surface of the chip. However, it is possible to use the data lines as conductors and to run the address line as a polycrystalline silicon layer. Based on general experience however, a better result is achieved if the data lines are used as diffusion layers, the address line but are designed as metallic conductors.

The conductors 22 of all memory cell pairs do not need to be individually connected to the voltage source Γ. All conductors 22 of the mutually adjacent pairs between the data lines DL can be produced in one piece and connected to the voltage source T via a common contact hole.

Because of the higher packing density, more information can be stored on the same chip area without reducing production output. But that> the performance of read-write memory at the same time reducing costs ^cl considerably been improved '.

55

For this purpose 3 sheets of drawings

Claims (1)

Patent claims: 1. Dynamic read / write memory on a semiconductor chip equipped with MOS-FETs of a first conductivity type with a plurality of data lines in the substrate as doped diffusion layers of one of the first opposite Conductivity are formed with a plurality of address lines and a plurality of one-transistor memory cells, each one Have a capacitor for storage and a MOS-FET for input and output of the information, wherein a first capacitor electrode is opposite to the semiconductor substrate through a thin insulating layer is separated, and one of the electrodes of the FET is connected to a data line while the other electrode is provided in the vicinity of a second capacitor electrode and the The gate electrode is connected to one of the address lines, characterized in that that