DE2656004A1 - Address expansion unit for microprocessor - uses character bit to control automatic switch=over between memories - Google Patents

Abstract

The address capability of a micro-processor is double by use of a switching logic block which responds to the state of a character bit. The microprocessor (mu P2) composed of arithmetic unit (RE) and programme store (mu PG) is in communication with memory (5) over a number of address lines (m). The memory is composed of two sections (D, P), each of 2m capacity. Switching between memory blocks is controlled by a logic unit (LO) with built in multiplexer (MU) that responds to a character bit (KL).

Description

Address range extension for a microprocessor

The invention relates to an arrangement for address area expanding direct addressing of a two-block memory with 2m information storage spaces each for a microprocessor with m direct address lines, which have a tag-controlled Logic depending on the license plate access to the 2m places of one or the other Have blocks.

Computers with directly addressable memories have a specific Number of address lines designed on which a memory address in a Binary code can be sent, a binary digit being provided for each address line is In this way, for example, a computer with 16 address lines can address a 64 K memory directly. If this storage capacity is insufficient, a larger memory must be used, but a correspondingly larger one Address area required. With commercially available computers (microprocessors), however, the number of address lines is fixed and cannot be changed.

In an application (own file number: A.W.Sweet-R.T # Swindle 8 # 2, P ) has already been proposed, the address lines connected to the microprocessor to lead via a switching device to two memory blocks of the same size. Addicted the address lines with one or the other become block select flags Memory block connected. These indicators are based on a read-only memory of the first part of an instruction, the second part of this instruction in The microprocessor outputs the address for the selected block. In general an instruction comprises a certain number of machine cycles. The for this at the The read-only memory provides addressing required identifiers in parallel Form in a shift register, from which it is then used to control the switching device can be read out individually one after the other clock-controlled. To execute commands, which require fewer cycles, e.g.

Jump instructions, care must be taken that after the last Cycle is skipped to a new program step. There are no more to this Means shown for external command decoding required.

In the context of the also to be solved with the named storage arrangement Problems, the object of the present invention is the address range expansion to simplify.

This object is achieved in that the microprocessor has a Microprogram memory has which generates the identifier and the output of the address controls via a micro-command. In addition to the omission of a read-only memory, a Shift register and additional decoding means there is the additional advantage that at the transition to the next instruction a cycle for loading the shift register not applicable.

Further advantageous embodiments of the arrangement according to the invention can be found in the subclaims.

The invention is described below with reference to the accompanying drawings The illustrated examples are explained in more detail. They show: FIG. 1 a first Arrangement for doubling the address area and the storage capacity by two separate memories and FIG. 2 a second arrangement for doubling the address area and the storage capacity with a double storage.

The arrangement shown in Fig.1, in which only the understanding The elements necessary for the invention are taken into account, contains a microprocessor / uPZ with a microprogram memory / uPG and a computing unit RE. The control in the microprocessor pPZ takes place via microinstructions that are stored in the microprogram memory / uPG are stored and by a sequence control, not shown, in each microprocessor is included, to be called. The arithmetic unit RE carries out the microinstructions accordingly arithmetic and logical operations. She has been controlled by one Access to microinstruction from the microprogram memory yuPG via an address multiple any places - according to the respective address - a memory S to there Information, i.e. to write in or read out data or programs. The number m of address lines AL in the address multiple is by the architector of the arithmetic unit RE, which limits the address range for direct addressing is - as already stated in the introduction.

If you take a binary code as a basis for addressing - commercially available Microprocessors work with this - then you get an address range of 2m where m is the number of bits of an address word, i.e. the number of address lines AL.

The m address lines AL are controlled by a logic LO either to the 2m available memory locations of one or the other memory block P or D switched, via m lines PAL or via m lines DAL. Consequently the address area is expanded to 2 x 2m.

The two memory blocks P and D are in their internal organization similar. Block P is used for storing and removing programs and Block D for Data used.

Switching the address lines AL from one memory block to the other, e.g. from P to D, is executed in the LO logic by a multiplex module MIJ, if this has a 1-bit identifier K from the microprogram memory on its control line KL / uPG refers to tK = "1"). If K = "O", the address lines remain in the example mentioned connected to the program memory block P. In the microprogram memory / iPG is each known whether parts of an instruction from the program memory block P or whether data - So the data memory block - are to be addressed, and the microprogram memory / uPG accordingly outputs an identifier K to the line KL. This will be Command analyzer circuits, e.g. for recognizing voltage commands, are superfluous. The license plate is output before the address submission, so that the multiplexer MU is set in time in the manner of a switch.

The same reference numerals are used in the arrangement shown in FIG as used in Fig. 1 if they are identical things. Which also includes the microprocessor yuPZ with its m direct address lines AL and the identification line KL. The lines AL and KL mentioned are also in this exemplary embodiment, FIG. connected to a logic bO ', which, however, differs from that in the previous exemplary embodiment (Fig.1) contains an expansion stage AD in which the 1-bit identifier K is the m-bit address word will be added. This allows the address range from 2m to 2m 1, i.e. also can be expanded to double.

The memory S consists of a double block with 2m 1 memory spaces, where the lower half P is the memory locations for programs and the upper half D is used for data. The memory locations are accessed via the address multiple DPAL with (m + 1) -bit address words.

Claims (1)

Claims ¼ 1. Arrangement for direct address area expanding Addressing of a two-block memory with 2m information storage spaces each for a microprocessor with in direct address lines, which have a tag-controlled Logic depending on the license plate access to the 2m places of one or the other Blockes, characterized in that the microprocessor (/ uPR) has a Microprogram memory (/ uPG) that generates the identifier (on line KL) and the output of the address (on lines AL) via a microinstruction (on lines BL) controls. 2. Arrangement according to claim 1, characterized in that the license plate controlled Logic (LO) contains a multiplexer (MU) that depends on the m address lines (AL) from the identification (on line KL) with one (P) or with the other block (D) connects via m block-specific address lines (PAL or DAL), with the two blocks can be separated from each other. 7. Arrangement according to claim 1, characterized in that the license plate controlled Logic (LO ') contains an expansion stage (AD) which leads to the address (on lines AL) can add the identifier (on line KL) and that the memory (S) consists of a Double block (P, D) is formed, which with the tag-controlled logic via mci Address lines (DPAL) is connected.