DE2653543A1 - MICROPROCESSOR COMPUTER SYSTEM FOR DATA PROCESSING - Google Patents

Description

Patent attorney
Dipl.-Phys. Leo Thul

Stuttgart * 3

A.W.Sweet-R.I.Swindle 8-2

INTERNATIONAL STANDARD ELECTRIC CORPORATION, NEW YORK

Microprocessor computer system for data processing

The invention relates to a microprocessor computer system, in particular with a 1-bit microprocessor that has a memory with random access for data required during processing and any intermediate results has j whose inputs and outputs are provided with buffer memories and which is controlled by an external Clock signal, receives instruction words from an external program memory in a specified cycle.

It has already been proposed (P 25 21 900) to use a 1-bit microprocessor for simple data processing tasks to use. This microprocessor contains a computer unit on a chip, all of which occur performs arithmetic and logical operations, a Random access memory that holds data and intermediate results required during processing, and Buffer memories that temporarily store input and output data.

November 8, 1976
Sat / Mr

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Program words are step-by-step controlled by an external clock generator from an external program memory given into the microprocessor, which control the data processing in a fixed cycle.

The invention is based on the object of the field of application of a simple microprocessor. The object is achieved in that a shift register with parallel inputs for receiving data to be processed and with parallel outputs for outputting processed data Data is provided that an input of the microprocessor is connected to an output of the shift register, the outputs the input data of the shift register in serial form and that an output of the microprocessor with a serial input of the shift register is connected, and that the shift register and the microprocessor with the same Clock signal work.

The inventive combination of shift register and microprocessor data with any number of bits can be processed.

A further development of the invention provides that for provision Additional memory locations with random access an AND element is provided, the inputs of which are clock pulses and receiving instructions derived from the program memory, the derived instructions being derived from the clock pulses whose output, which is connected to the serial input of the shift register, is switched through so that a program cycle is extended by as many program segments as the shift register has storage locations.

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This increases the memory capacity given by the architecture of the microprocessor.

Another development of the invention provides that several microprocessors are used to enlarge the computer system are provided with their own addresses, which individually depend on their data-carrying output via a multiplexer from an address via an address multiple from the higher-level processor to the serial input of the Shift registers are connectable, the address multiple is also connected to a demultiplexer that the Microprocessor, which has the pending address, activated via an input and that the shift register via a variety of lines for data exchange with the higher-level Processor is connected. This creates a very flexible calculator system, for example in telephone PBXs, where changing customer-specific requirements have to be taken into account, can be used quickly and with a minimum of effort.

Other advantageous developments can affect the rest Subclaims are taken.

The invention is explained below with reference to in drawings illustrated embodiments explained in more detail. Show it:

Pig.l an arrangement with a shift register, the one Has multiplex input,

2 shows an arrangement with a shift register f'fulfciplex — has output,

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.G.

Pig. 3 a circuit with a shift register in which both a multiplex input and a multiplex input are provided ₃

4 shows a circuit with a shift register for enlargement of the memory RAM for the micro processor and

Pig.5 is an interface circuit between an iron Malfci miferoprocessor and another processor laifc shift register.

In the example, a microprocessor is used that works as a 1-bit computer _s whose data inputs store silver interference filters with input buffers and whose data outputs are connected to output buffers that accept results from arithmetic operations -

There is also a memory ( not shown) with free access RAM for data, which is required for processing and for possible intermediate results. Delay elements and low-frequency clock generators are provided; the latter are formed from Iispulfolgeteilern. Command words from external program memories zügefffibrt _s each of which contains six address bits and two control bits. The address bits go to address decoding and selection circuitry, while the command bits control the operation of a logic unit which performs the processing. These instruction words are obtained in a fixed cycle in parallel form from the program memory, which is provided externally for the processor used here.

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The combinations shift register microprocessor described herein are so that they zusairanengeschaltet _s or more, and possibly also use the input and out-crossing auxiliary pins one of the aforementioned inputs and outputs. The pins used in this way are named RH, WPj LO and GL. Such an arrangement can operate with a delay of exactly two instruction cycles before the data are output on the named connection pins and also other direct output signals such as those from the output buffer memories. This delay arises because the microprocessor used here works with two-phase logic and is an LSI module. The above mentioned auxiliary termination pins have the following punctures:

(a) RH is a direct input for the microprocessor:

the data occurring on this connection are read into the logic unit with the READ command. In this case, the port RH is assigned the address 0.

(b) LO is the data output of the computing and logic unit,

which is only activated for write commands WRITE.

In the case of READ commands, the LO connection remains logical

(c) WP is an output of the logic unit, which with each

Command WRITE (WRX, WRX, WRO) is at logic 1 and for all other commands at logic 0.

(d) GL is an output from a blocking circuit - called

Control lock - of the microprocessor, which goes to logical 1, when address 14 (octal) appears and on logic 0 is reset when address 15 (octal) appears. Commands with addresses 14 and 15 are used labeled FLIP.

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• f.

The named outputs LO and WP are blocked when the control block is set to logic 0. The FLIP command (lh or 15) generates a logical 1 on the WP connection if the functional part of the program word indicates a WRITE command. When the address decode part indicates that the command word is a FLIP command, the logic unit is disabled from operation.

The four types of commands defined by the four possible values of the two function bits are as follows:

(i) RD - READ. With a normal address χ means

this: read from this address to the logic unit. With address 0 there is direct reading into the logic unit possible via connection RH. Address 77 is a fixed value logical 1.

(ii) RD means: read and complement. With any address this means: read along Completion of this address to the logic unit. The logic unit LU performs a NAND link of the fed-in data and RD commands.

(iii) WR - WRITE. The result of the calculation is thus based on the previous WR or WR command Transfer address in the command. A reset in the logic unit is provided for address.

(iv) WR means: write the complement of the calculation result to the address of the command. With the An OR function is provided for address 0.

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• 3.

In the circuit shown in Pig.l, the shift register SR can have any number of bits with parallel inputs IP. to have. The serial input of the shift register SR is connected to the output terminal OP1 (buffer memory output) of the microprocessor BP. Output connection WP of the microprocessor BP supplies clock pulses for the shift register SR, specifically with each command WRITE, so that the shift register SR is controlled by appropriately placed commands WRITE with the desired repetition frequency and timing. Output GL supplies a serial control signal from the microprocessor BP in response to a command FLIP of the type WRITE. This makes the shift register SR step by step
forwarded. In this way, data that have entered the shift register SR via the inputs IP can be
get into the memory RAM of the microprocessor BP.

It is assumed that four bits M1-M4 of the memory RAM for receiving data from a 4-bit shift register, for example be used. The program for this includes the generation of pulses via connection OP1 in order to enable parallel storage of the shift register SR on the inputs IP, after which a command FLIP of the type WRITE a produces the first output pulse on connection WP, as before described. Each step of the following sequence comprises two commands: RD-RH followed by WR-Mx.

The last position in the shift register SR is read into the logic unit via connection RH; registered mail follows from the logic unit in Mx. Each of these commands WR also generates a shift pulse on terminal WP for the shift register SR.

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The effect of these commands from the combinations RD-RH, WR-Mx is that the data contained in the 4-bit shift register SR is transferred to bits M1-M4 of the memory RAM, so that the data from the shift register SR replace that of the memory RAM. After the last of these command word combinations Another command FLIP of type READ terminates the sequence, whereby the output signal on terminal GL is reset to remove the serial control signal from the shift register SR, so that a further shift in the shift register SR to subordinate commands WR in the program is prevented.

The commands mentioned are preceded by the RD77 command (77 octal), which is logical 1 and which the WR-OPl command (write to Terminal OPl) and then the command WR-OPl (write inverse to terminal OPl) follows. This combination generates on connection OPl a pulse which causes the shift register SR to determine the start of an input multiplex operation.

Pig. 2 shows a circuit with a shift register SR, which enables an output multiplex puncture. In this case, data is entered from the WP connection via a pulse 0 controlled gate T and with serial control pulses from terminal GL. The output from the shift register SR takes place via a set of four output circuits OPS controlled by clock signals from the connection OP1 at the outputs Z1-Z4.

The sequence begins with a FLIP command of the WRITE type and is followed by a sequence of commands for each of the Z Bits. Each of these sequences can contain an invoice,

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the result of which is fed to the shift register SR via terminal 'LO. This way the results are in the shift register SR accumulated and step-by-step by means of the pulses appearing at connection WP for each write command the program sequence is pushed on and clock-controlled from the connection OP1 to the controlled output circuits OPS to hand over.

Such a sequence with the commands RDA, RDB and WRZ can deliver the result Α · Β at output Zl. This means that the content of position A and then the the place B is written and then the AND operation of A with B in the logic unit with command WR is over Data output LO written to output Z. As before, the sequence is ended by the FLIP command of the READ type. The sequence ends with the command sequence RD77-WR-OP, WR-OP, whereby, as in Pig.l, a pulse is generated at the connection OPl, which in this case contains the data from the shift register SR in the controlled output circuits OPS to the outputs Zl-Z4.

In Figure 3 are input multiplex and output multiplex functions combined. In a program for this purpose, the FLIP-WRITE command is followed by an input and then an output multiplex sequence, followed by the FLIP-READ command.

The command sequence of this program is executed by the commands • RD77, WR-OPl ROPl and then RD77-WR OP2, whereby the former the parallel input of the data on the lines IP into the shift register SR and the latter the transfer of the

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Output data from the shift register SR to the controlled output circuits causes. With regard to the description of the exemplary embodiment shown in FIG. 3, reference is made to the Description of the previous embodiments (Fig.l and 2) referenced, to which nothing more needs to be added. ■ ·

Fig.4 shows an embodiment in which a shift register SR is used to enlarge the memory RAM of the microprocessor BP. This shift register SR with an indefinite size of η bits is said to be with an m-bit RAM memory block work together in the microprocessor BP. All of these (n + m) bits are used as "variables for defining the status" designated. Since the variables must be kept saved from one program cycle to the next, the memory RAM of the microprocessor BP requires a storage capacity increased by η bits.

From what has been said, it follows that these m bits of the RAM memory are regarded as part of an (n + m) -bit shift register can. Because of this, the shift register so defined is set up in such a way that it (m + n) clock pulses during a Can record program cycle.

This program cycle is divided in time into a number of segments and is grounded at the beginning of each segment up to m data bits unsaved with the shift register, the number of bits relocated in this way depending on the requirements depends on the program. Between these data transfers, the application equations for the Variables that continuously occupy the m memory bits are evaluated, i.e. the program works depending on these bits

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41.

Thus, assuming m = 4 and n = 8, the following results Tabel:

begin

Microprocessor BP memory RAM

Shift register SR

1. Re-feeding ABCD

Evaluate equations for
ABC. Evaluate other equations.

2.Uf unsaved EFGH

Evaluate equations for EFGH; evaluate other equations chungen.

3. Transfer JKLM

Evaluate equations for JKLM. Evaluate other equations.

EFGHIJKLM JKLMABCD ABCDEFGH

Return to the start

The command sequence begins with each data transfer with command RD14, the command FLIP follows the sequence read, write, read inverse and write inverse (RD, WR, RD, WR) as follows:

RDl 4

RD Ml (A) WRO

RD RH (E), WR

RD M2 (B) etc. for every bit of

change.

This means that the content of Ml, i.e. A, is read out after the command RD14 by command RDMl and by command WRO is sent via output LO, after which the command RD-RH the transfer of the last bit from the shift register SR

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controls in the microprocessor BP and then command WR Ml controls this bit in Ml, in which it A replaces. Command RD M2 initiates the same sequence with regard to the M2 bit from the RAM memory.

The sequence is ended by command RD15 » the other command FLIP. Output GL of the microprocessor BP remains at logic 1 from command WRO to the end of command RDl5 and shift pulses, that is clock pulses for the shift register SR, occur with command WR Ml and equivalent commands for each transmission. These commands are generated by an external gate circuit T. In this way, the complete sequence for this transmission results as follows:

FLIP

(A) GL LO SR cycle RDl 4 0 - 0 RD M ₁ (E) 0 - 0 WR 0 1 0 0 RD RH (B) 1 0 0 WR M ₁ 1 (A) 1 RD M ₂ (F) 1 0 0 WR 0 1 (E) 0 RD RH (C) 1 0 0 WR M ₂ 1 (B) 1 RD M, (G) 1 0 0 WR 0 1 (P) 0 RD RH (D) 1 0 0 WR M ₃ 1 (C) 1 RD M ₁₁ (H) 1 0 0 WR 0 1 (G) 0 RD RH 1 0 0 WH M ₄ 1 (D) 1 RDl 5 1 0 0 0 (H) 0

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It should be noted in the programmer techniques used for the microprocessor BP that the bits in the memory RAM which the store information obtained during processing, generally only for limited periods in the program cycle are used, usually these periods lie close together. This makes the use of a shift register which can cycle several times particularly easy. Cycle formation usually takes place once per program cycle, but it is possible more than once.

The shift register can be a CMOS component whose Register length is designed for a 5-bit code on 5 register input connections. Here is a length-determining Code given for each microprocessor program that is permanently bound, so that for the microprocessor BP provided shift register SR has a fixed length.

There are certain limits to the use of such a memory:

(a) The bits stored in the RAM / SR relocation cannot be comprehensive in expressions throughout the program be used and

(b) the bits in the shift register SR involved in any RAM / SR relocation cannot be in segments of the program for which they are intended will be used during the segment.

The choice of the bit that can be stored in the shift register SR is therefore program-dependent.

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If the microprocessor BP has suitable inputs and outputs available, two or more shift registers SR can be connected to one and the same microprocessor BP can be connected. In this case a shift register SR uses the connections RH and LO as in Fig.4 and this or any other shift register SR uses one of the inputs and one of the outputs.

Fig.5 shows an interface circuit between a Multi-microprocessor system and another microprocessor, not shown, which is another identical or another can be bigger. The multi-microprocessor system is in the dash-dotted box; one the microprocessors are provided with the reference symbol BPN. The interface circuit contains a shift register SR with parallel and serial inputs and outputs. The data transfer between shift register SR and memory RAM one of the microprocessors e.g. BPN, but also the larger one Processor, happens according to the requirements.

The microprocessor involved in the data transfer is created by inserting the address of the desired microprocessor selected into the address buffer AP of the larger processor. The buffer AP is in connection with a demultiplexer DEMUX from a logic 1 to the input EW of the selected microprocessor, with it is believed to be just BP. A multiplexer MUX responds to the same address and connects output LO of the same microprocessor with the serial input of the shift register SR.

The read-only memory ROM contains the program sequence which is used by all microprocessors in the dot-dashed box.

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This program is divided into two areas. The first area concerns the application program for logical punctures, which the microprocessor executes on the basis of its controlled circuits. This program ends with the reset command RESET-PROGRAM COUNTER to a program counter that defines the sequence of commands from the read-only memory ROM. Of the The second area of the read-only memory ROM contains a data transfer program which begins with a FLIP command and ends with a reset command RESET (WRO).

The shift register SR can have any number of bits within of the capacity of the microprocessor, e.g. BPN, but usually each data wrap is 8 bits or fewer. After the restoration has taken place, the data originally placed in parallel occupy the shift register SR at large processor an area A in the selected memory RAM of the microprocessor and the data from area B from The memory of the microprocessor is in the SR slider. The areas A and B of the memory from the microprocessor can be of the same kind; they can overlap or be completely separated from each other. This is where the data transfer controlled by the clock signal CK, which is the result of the direct decoding of the word output from the read-only memory ROM is derived for any WRITE instruction that occurs in the reload segment of the program. Note that the storage between shift register SR and microprocessor BPN (in both directions) takes place serially; the ■ Restoring between the shift register SR and the large processor (in both directions) generally takes place parallel, possibly also serial.

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The detailed coding for the data transfers is as follows:

Command memonic execution

Sets the control lock of the addressed microprocessor • BP

FLIP RD IU WRZ B2 WRZ AD 0 RD WRO WR Al f RD 0 WR A2 I. I. WR At RD Bl

Shift register contents to RAM bits Al-An

RAM bits Bl-Bn to the shift register

Sets all control locks in the BPS microprocessor

The microprocessor program normally runs in read-only memory ROM in the area that contains the application program, because of the program counter reset command RESET PROGRAM COUNTER between the application and data transfer programs skipped, i.e. left out of the normal command sequence. If the other processor has a If data transfer with one of the microprocessors such as BPN is required, then the intermediate memory AP with the Address of the desired microprocessor BPN and the sliding

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register SR loaded with the data intended for this microprocessor.

An identifier derived from the buffer AP causes the program counter reset function of the Pest value memory is locked so that at the end of the The next cycle of the application program the pest value memory ROM passes to the data exchange program. This causes the data transfer already described to take place, at the end of which there is a further identifier the disabling of the program counter reset command RESET PROGEAM COUNTER and the application program continues to run normally. When the other processor reads data that the selected microprocessor in the shift register SR has filed, the indicators for a subsequent Operation postponed.

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Claims (1)

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Claims / Ι.) Microprocessor computer system, in particular with a 1-bit microprocessor, which has a memory with random access for data required during processing and any intermediate results, whose inputs and outputs are provided with buffer memories and which is controlled by a external clock signal, receives instruction words in a fixed cycle from an external program memory, characterized in that a shift register (SR) is provided with parallel inputs (IP) for receiving data to be processed and with parallel outputs for outputting processed data, that an input (RH ) of the microprocessor (BP) is connected to an output of the shift register, which outputs the input data of the shift register in serial form and that an output (LO) of the microprocessor is connected to a serial input of the shift register, and that the shift register and the microprocessor with the same Clock signal (on connection WP) work. 2. Microprocessor computer system according to claim 1, characterized in that an AND element (T) is provided to provide additional memory locations with random access, the inputs of which receive clock pulses (0) and commands derived from the program memory, the derived commands from the Clock pulses are switched through to its output, which is connected to the serial input of the shift register (SR), so that a program cycle is extended by as many program segments as the shift register (SR) has storage locations. - I - 709825/0870 ORIGINAL INSPECTED A.W.Sweet 8 - 2 - ■ 3 · Microprocessor computer system according to claim 1, with a superordinate processor, characterized in that several microprocessors (BP) with their own addresses are provided to enlarge the computer system, which individually with their data-carrying output (LO) via a multiplexer (MUX) are dependent can be connected from an address via an address multiple (ADDRESS) from the higher-level processor to the serial input of the shift register (SR), the address multiple also being connected to a demultiplexer (DEMUX) that controls the microprocessor (BPN) that has the pending address , activated via an input (EW) and that the shift register via a line manifold (DV) for data exchange with the. higher-level processor is connected. 4. Microprocessor computer system according to claim 3, characterized in that a read-only memory (ROM) is provided for Umspeieherurig the shift register contents, the inputs of which are controlled by the external program memory and the output of which is connected to a control input (CK) of the shift register (SR) and that the line manifold (DV) for data exchange is formed from bidirectionally stressed parallel lines. 5. microprocessor computer system according to claim 4 ,. characterized in that the address multiple (ADRESS) is connected to an intermediate memory (AP) which, in addition to the addresses generated by the higher-level processor, also accepts a program-modifying identifier » ORIGINAL INSPECTED 709825/0870