DE2637961A1 - CONVERTER CIRCUIT FOR CONVERTING A BINARY SIGNAL INTO AN AQUIVALENT ANALOG SIGNAL - Google Patents

Description

Patent attorney Franz Werdermann, 2 Hamburg 36, Neuer Wall 10

N. 76,065 DH

National Semiconductor Corp. 2900, Semiconductor Drive Santa Clara, Calif. , V.St.A.

Converter circuit for converting a binary signal into an equivalent analog signal

Pur, the present application claims priority from the corresponding ¹ US Application Serial-No. 608 873 dated August 29, 1975.

The present invention relates to a converter circuit for conversion a binary signal in bit-parallel format into an equivalent analog signal.

The invention relates generally to a digital / analog signal converter, and in particular to an integrated circuit for performing digital / analog signal conversion and a Analog-to-digital signal conversion through successive approximation

The majority of known digital / analog signal converters and the analog / digital signal converters working with successive approximation, who use the first-mentioned signal converters have problems due to the non-monotonous signal conversion

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Conversion to "Bin digital / analog signal converter with non-monotonic behavior" is a converter where the analog output signal does not grow in the same direction as the successive supply of binary words increases with the value at an input of this converter. Among the known digital / analog signal converters all require components that are relatively precisely matched to one another in order to achieve monotonous behavior. More precisely, the components of the known digital-to-analog signal converter must be matched to one another within half a bit with the lowest value so that the signal converter exhibits a monotonous behavior. A bit with the least significant bit (LSB - least significant bit) corresponds to the reciprocal value of 2 ¹¹ , where η is equal to the number of bits in the binary word

A previously known and widely used digital ZAnalog signal converter is generally referred to as R / aR-Ladder DigitaWAnalog signal converter. This signal converter uses a ladder-like resistor network that has twice as many resistors and as many switches as there are bits in the Binary word that is to be converted into an analog signal. This signal converter can also be used in an analog-to-digital signal converter with successive approximation. The resistances this network must be matched exactly to one another so that the signal converter shows monotonous behavior. In particular, the Resisted in the branch for the least significant bit within half a bit of the least significant bit to the The value of the terminating resistor can be adjusted so that the circuit shows monotonous behavior. In the same way, each branch must

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lie within the value of half a bit of the least significant value of all the branches which are connected in parallel with one another and are of a lower order than this branch, so that the circuit exhibits nonotonic behavior. In the case of an 8-bit digital / analog signal converter, for example, the resistances must be adapted within a tolerance of $ 0.2.

Other digital-to-analog signal conversion techniques and the analog / digital signal conversion with successive approximation use either capacitor or transformer networks · The components of these networks must also be accurate be coordinated so that the signal converter shows a monotonous behavior. The majority of the previously known digital / analog signal converters, which show a monotonous behavior, require complex and expensive processing methods. Those digital / Analog signal converters built with discrete components require the selection of components with relatively high Accuracy so that these components match each other within half a bit of the least significant. Hence are these discrete circuits are also relatively expensive if they are to behave monotonously

The incentive of the R / 2R digital / analog signal converter is that it can be interpreted in such a way that the actuation of any individual or all of the seers contained in it does not changes the current flowing through the branches of the resistor network. This means that when each switch is actuated, the current in each corresponding branch of the network increases a summing amplifier and equal to the value of the Current remains in this branch before actuation. It follows,

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that if there is a change in current in the actuation of any switch, it would result in an error which the Current change is proportional. This error could be large enough to cause the circuit not to become monotonous behaves. Some of the other digital to analog signal converters have does not have this circuit-related advantage, and compensation must be carried out for the current change that occurs from the actuation of the switch in the converter results "

The problem of matching the values of the components to one another is further complicated by another factor: In the past, these circuits have been produced by creating circuit connections between the individual components in a known manner, the type of connection depending on the type of circuit, for example an integrated circuit or a circuit with a discrete construction. The contact points of these connections are ohmic insofar as they offer a certain resistance in the circuit. The resistance value of ohmic contacts contributes to mismatch between the components and the Z _we strength of the digital / analog converter in signal. Since the magnitude of the resistance values given by these contacts fluctuates strongly and cannot be predetermined, the resulting mismatch cannot be easily determined before the circuit is completed. Signal converters are less than the value of half a bit of the least significant value in order to allow a certain tolerance for the resistance, which is given by the ohmic contacts in the circuit. The resistance value given by these ohmic contacts can also

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if contribute to inaccuracy in those circles where, how explained above, a change in the current can occur. The inaccuracy of such circuits can be the result of non-linear behavior of the circuit and / or undesirable Lowering the gain in the circuit. Both of these causes can be the result of unpredictable resistance values of ohmic contacts in the circuit. It follows that it is desirable to increase the number of these to restrict ohmic contacts to a minimum "

In these implemented as integrated circuits digital / analog signal converters, which are dependent on the current flow through their various components and branches, the geometry of the circuit components must be appropriate to the value of the current flowing through them be. As a result, these components can in some cases become quite large, thereby increasing the area of the integrated Circuit board of which they are part · The geometry these components must also be adapted within the tolerances explained above. It follows that it is desirable to minimize the area of an integrated circuit die; and the need to adjust the To bypass the geometry of its components to the flowing current

It is therefore the object of the invention to provide a digital-to-analog signal converter and to create an analog / digital signal converter with successive approximation which, due to the circuit concept, show monotonous behavior, and where the tapping of a reference voltage does not cause the signal converter not to be monotonous behaves, the converter circuit is extremely simple

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and makes relatively little complex and inexpensive Procedures required in their processing, furthermore, the converter circuit has a minimum number of Ohmic contacts, with at least some of the associated components having minimal geometric dimensions and this geometry need not be adapted.

The proposed according to the invention for solving the problem posed Converter circuit is characterized in that a voltage divider circuit is parallel to a reference voltage source is connected and has N-1 outputs that each of these Outputs is assigned to the corresponding binary word from a large number of binary words which are equivalent to the numbers from 1 to N-1 are, where the mentioned binary words have η bit, and where is applicable:

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that a plurality of switches in a Sehalter arrangement between the corresponding outputs of said voltage divider circuit and an output of said switch arrangement is connected, that said Sehalter arrangement N-1 Stropfade ait n switches in, each current path has that the idle state of each of the said Switch in each «current path defines a corresponding binary word from a plurality of binary words, which are equivalent to the numbers from 1 to N-1, each of the mentioned switches in each current path corresponds to the state of a corresponding bit of a binary word with η bits and according to this state can be operated

The features and delays of the invention are represented by a digital / Analog signal converter circuit achieved using a voltage divider

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which is connected in parallel to a reference voltage and a plurality of circuits which are connected to one another in a holder arrangement and respond to the individual bits of a binary word in order to generate an analog signal at an output of the holder arrangement which is equivalent to the binary word. If, more precisely, the binary word to be converted has a number of η bits and N «^ ¹ , then under these conditions the switch arrangement closes N current paths between the corresponding outputs of the voltage divider and an output of the switch arrangement with the number of η switches in each rung. Each switch in each rung corresponds to an assigned bit of the binary word that is currently being converted and responds to this bit. In the idle state of the Sehalter, each current path defines a corresponding binary word from a large number of binary words based on the switching state of the switch located therein, which are equivalent to the numbers from Θ to N-1 in a corresponding manner.

A feature of the invention is that an elongated strip of semiconductor material of a first conductivity type is provided diffused in a substrate layer of a semiconductor material of the opposite conductivity type to to form the voltage divider, as well as a connection of those switches that are connected to the voltage divider

Another feature of the invention is to provide a layer of semiconductor material of a conductivity type which into a substrate layer of semiconductor material from the opposite Line type is diffused to the adjacent ports of

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to form two adjacent switches.

Further advantages and features result from the following Detailed description of the invention based on exemplary embodiments and based on the accompanying drawings. Show it:

Fig. 1: a circuit diagram of a digital-to-analog signal converter which has been carried out according to the principle of the invention,

Figo 2: a block diagram of a circuit arrangement for execution a digital-to-analog signal conversion Use of the converter circuit shown in Fig. 1,

Fig. J: a circuit diagram, partly shown as a block circuit, an analog / digital signal converter arrangement with successive approximation, which according to the principle of the invention has been carried out

Fig. 4-: an illustration of the logical links that are used in Fig. 2 shown control logic circuit,

Fig, 5: a plan view of the arrangement on the monolithic integrated circuit die of the circuit shown in FIG. 1, and

6s is a vertical sectional view of the circuit board in the direction of arrows 6-6 in FIG. 5.

Corresponding reference numbers in the various representations

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of the accompanying drawings are intended to be congruent To identify components.

With reference to the detailed illustration according to Pig. 1 becomes a circuit for converting a 3-bit binary word into a Analog signal shown. The circuit includes a voltage divider circuit, indicated generally by the reference numeral 10 and connected between a reference voltage Vg and ground potential is. The voltage divider circuit 10 is formed from a plurality of resistors 12-19, and the connection points between these resistors form the outputs with the corresponding reference numbers 20-27 · These outputs are with corresponding inputs connected to a switch arrangement, indicated generally by the reference number 50 and having an output 32

The switch assembly 30 includes a plurality of switches 34-47. The binary word to be converted to an analog signal is represented by the letters ABC, where A is the most significant bit, B is the second most significant bit, and C is the Represents the least significant bit. X, B 'and u are, of course, the complementary values to A, or · B and C. The Sehalter 34-37 are virtually coupled to one another and are normally located in the locked or open switching state when the bit C having the lowest priority to a binary ^N 0 ^H. The switches 38-41 are also practically coupled to one another and are normally in the switched or closed switching state when the bit C with the lowest place value has the binary value ^N 0 ^N , or its complementary vert TT has the binary value ⁿ 1 ^M. The switches 42 and 43 are also practically coupled to one another and are in the locked position

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or open switching state when bit 6 with the second highest value has the binary value "0". The switches 44 and 4-5 are also practically coupled to one another and are in the closed or switched-through state when the bit B with the second most significant value has the binary value ^H 0 ⁿ , or its complementary value B "has the binary value" 1. The switch 46 is normally in a locked or open switching state when the bit A with the highest priority has the binary value "0", and the switch 47 is normally in a switched or closed switching state when the bit A with the highest priority has the binary value ^H 0 ", or its complementary value A" has the binary value "1 ⁿ .

The switches 34-47 are thus controlled by control lines that are shown schematically by dashed lines, which are designated by the reference numerals 48-53.

It should be noted that there are eight outputs from the voltage divider circuit 10 and eight current paths from these outputs to an output 32 through the switch arrangement 30, with three switches in each stroke path "O * represents, and that. ^ The locked or open switches each represent the binary value ^N 1 ^H , each of the eight strobe paths in the switch arrangement 30 representing a binary word from a plurality of binary words which go ^{from H} 000 ^M to ^{11 IIi *} , namely Ib idle state of each switch if ABC is * 000 ^H.

If a specific binary word to control switches 34-4-7

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is used via the control lines 48-53, the equivalent analog voltage for this binary word is generated at output 32 as an analog amplitude. Assuming that the resistors 12-19 have the same values, each ^{binary word used successively from M} 000 ^M to ^M 111 ^M to control the switches 34-4-7 generates an increasing analog signal in which the values of the increment are equal to one another ·

Assuming, for example, that the binary word "000" is fed to the switch arrangement 30 via the control lines 48-53, the switches 34-4-7 remain in their illustrated position and the output signal of the switch arrangement 30 is zero. If, however, the "binary word ^M 001 ^{H is} fed to the switch arrangement 30 via the control lines 48-53, the switch 34-37 are closed, the switches 38-41 are opened, and the remaining switches 42-46 remain in the position shown, in such a way that that only the connection point 21 of the voltage divider 10 is connected to the output 32 of the switch arrangement 30 »In the same way, the binary word" 010 "causes the connection of the connection point 22 with the output 32, the binary word ^H 011 ⁿ causes the connection of the connection point 23 with the Output 32, the binary word ⁿ 100 ^M causes the connection of the connection point 24 to the output 32 »the binary word ^M 1O1 ^M the connection of the connection point 25 to the output 32, the binary word ^M 11O" the connection of the connection point 26 to the output 32, and the binary word ^M ni "causes the connection point 27 to be connected to the output 32 ·

The digital-to-analog signal converter illustrated in FIG. 1 is so above in connection with the conversion of a 3-bit binary word been described «It goes without saying, however, that the

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Subject of the invention can be used for converting binary words of any size into an analog signal. If the binary word to be converted has the number of η bits, then N-2 becomes ¹¹ . Then the voltage divider circuit 10 must have the number of N components, such as the resistors 12-19, and N outputs or connection points. The holder arrangement contains a total of 2N-2 switches, N holders being connected to the N outputs of the voltage divider circuit 10. In addition, the switch arrangement 30 includes N current paths from N outputs of the voltage divider circuit 10 to its own output 32, as well as switches in each current path 0 to N-1 correspond to each current path of the switch arrangement 30 is connected to the corresponding connection point of the voltage divider circuit 10, which corresponds to the equivalent analog voltage for the binary number represented by this current path

If, accordingly, an 8-bit binary word is to be converted into an analog signal, the voltage divider circuit 10 contains 256 resistors with 256 outputs going therefrom. Switch assembly 30 also includes 510 switches, with eight switches in each of 256 current paths. Starting with the current path connected to the lowest voltage divider output of the voltage divider circuit 10, each of the 2 ^ 6 current paths represents the binary numbers ^M 00000000 ^H to ^M 11111111 ^M due to the idle state of the switch located in it. It follows that such a digital-to-analog signal converter would not be feasible in the case of a construction with discrete components. Furthermore, if any current were to flow through any of the current paths of the switch arrangement 30, an error would be made in the

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/ ³ 26379B1

Analog output signal available sexn.

FIG. 2 illustrates a circuit arrangement for converting a binary word into an analog signal using the one shown in FIG. 1 Scheraatically represented digital-to-analog signal converter. Like there As shown, the binary word to be converted is contained in a memory 100, and each bit of the binary word and its core supplementary value are output to the digital / analog signal converter via a large number of control lines 102. Thus, these control lines correspond 102 the control lines 48-53 according to Figo 1. The output 32 of the digital / analog signal converter becomes a buffer amplifier 104 with a high input impedance, which emits the analog signal equivalent to the converted binary word at its output.

When the bit having the highest significance has the binary value "0" in the conversion of the binary word, the switches 46 remain and 4-7 in the position illustrated, "However, if the bit having the highest priority at the converted binary word to a binary ^H 1 ^M , the switch 46 turns on and the switch 47 remains open. Similarly, switches 42-45 are controlled according to the logic voltage value for the second most significant bit, and switches 34-4-1 are controlled according to the binary value of the least significant bit in the binary word to be converted _e 1 it follows that for all possible bit combinations of a supplied binary word which is supplied on the control lines 48-53, an analog signal amplitude is supplied to the output 32 which is equivalent to a specific supplied binary word. Due to the high input impedance of buffer amplifier 104-, relatively little or no current flows through any of the

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Current paths in the switch arrangement 30, so that the error is relatively small. However, this error does not result in the digital-to-analog signal converter shown in FIG the voltage divider circuit 10 is closer, is always more positive than any connection point which is closer to the negative end of the voltage divider circuit 10. If the buffer amplifier 104 is a buffer amplifier designed using what is known as "I FKD ¹¹ or ^M MOS ^W circuit technology, then no current flows, apart from brief current peaks.

The digital-to-analog signal converter shown in FIG. 1 can, as shown in Fig * 3, as an analog-to-digital signal converter with successive Approach can be used. Because of the operation of such a circuit, as will be described below, the switch 41 is not required and is therefore not shown in the circuit «

If each of the resistors 13-18 has the value of 1 ohm, the resistor 19 1.5 ohms, and the resistor 12 0.5 ohms, then a voltage of 8 V applied to the voltage divider circuit 10 provides voltages of 0.5; 1.5i 2> 5 \ 3.5} 4.5} ^^ and 6.5 V at the corresponding connection points 21-27. These voltage values correspond to the binary numbers from "001" to ^H 111 ^H ·

The output 32 of the digital-to-analog signal converter is connected to an input of a comparator circuit 56, and the analog signal V _x to be converted into a binary signal is fed to the other input of this comparator circuit. The output of the comparator circuit 56 is connected to a control logic circuit 58,

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which clock pulses C are supplied via a terminal 60, and a trigger signal S via a terminal 62. The control logic circuit 58 generates each bit of a binary word in turn on a corresponding one of a plurality of output lines of output lines 64 · as output signal · you output lines 64 are also used with the digital-to-analog signal converter Control of the switches contained in the switch assembly 30 connected The output lines connected to the digital / analog signal converter 64 also provide the complementary value to each bit of a generated binary word, in such a way that these lines denote the Control lines 48-53 according to Pig 1 correspond to

Initially, the control logic circuit 58 brings its output for the bit with the most significant value to the binary value ^M 1 ^M , so that only that current path in the switch arrangement 30 that connects the central connection point 24 of the voltage divider circuit 10 to the output 32 is switched through. As a result of this process, the voltage at the connection point 24 of the voltage divider circuit 10 is compared with the analog signal V to be converted by the comparator circuit 56. Is the analog signal to be converted V__ larger

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as the voltage at this junction point, the Aussangsspannung goes to the comparator 56 to the logic voltage value "1 ^H above · Venn jedoeh the analog signal V is lower than the voltage Getting Connected point ^v to this, there is the logical voltage value ¹¹ O ¹¹ at the output of the comparator circuit 56 · If the output signal of the comparator circuit 56 is at the logical voltage west ^N 1 ^N , the output of the control logic circuit 58 for the bit with the most significant value remains at the binary value "1"

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has a low logic voltage value "0", then the output for the bit with the highest significance in the control logic circuit 58 changes from the binary value "1" to the binary value "0". With each clock pulse C "successively supplied to control logic circuit 58, the output for each bit follows the same pattern as described above for the most significant bit Binary value "1" is brought, then a comparison is carried out, and then this bit output either ^{remains at the binary value M} 1 ^{M or changes over to the binary value M} 0 ^M depending on the comparison carried out in the comparator circuit 56. At the end of these successive approximation processes After the comparison operation has been carried out with the bit of the least significant value, a binary word is generated on the output lines 64 · which is equivalent to _{the analog signal V x} ANALOG / DIGITAL CONVERSIONS ¹ * by Hermann Schmid, Verlag Van Nostrand Reinhold Co., V.St A., 1970, and in particular, refer to pages 240-24-7 of this book. Although this work also illustrates and describes a control logic circuit such as control logic circuit 58, another embodiment of this control logic circuit is described in Pig. 4 · illustrated and described below »

The one in Pig. 4- control logic circuit 58 shown is intended to used together with a 3-bit digital / analog signal converter to be, however, it goes without saying that the circuit can be used in a digital / analog signal converter of any desired Size for executing the analog / digital signal conversion can be expanded with successive approximation. As shown in Figo 4-

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the output of the comparator circuit 56 is at a Line 66 an input of an AND gate 68, and the clock pulses C * from terminal 60 through an inverter 70 to the other Input of AND gate 68 passed. Terminal 60 is also connected to one input of an AND gate 72. The trigger signal S at connection 62 is fed to the reset input R of a bistable multivibrator 74. The output "Q" of the bistable multivibrator 74 is connected to the other input of AND gate 72 · If accordingly a trigger signal S is fed to the terminal 62, then clock pulses C at an output of the AND gate 72 output, which is connected to the input of a counter 76 «. The connection 62 is also connected to a reset input of the Counter 76 connected via a line 75 in such a way that the counter is initially reset when a trigger pulse S occurs will. Each positive voltage excursion of the clock signal C ″ causes the counter 76 to continue counting and, one after the other, an output signal each generated on a corresponding output line among output lines 78-81 · The output lines 78-80 are connected to an input of a corresponding QDER gate among three OR gates 82-84 «The outputs of the OR gates 82-34- correspond to the control lines 48, or · 50 and 52. These Outputs are passed through reverse stages 86-88, and the outputs these reversing stages correspond to the control lines 49 or 51 and 55

The output of the AND gate 68 is connected to an input of each of three AND gates 90-92, and the output lines 78-80 are similar to the other inputs the AND gates 90-92 connected · The outputs of the AND gates 90-92 are each with the control input S of a corresponding

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Das connected to the under three bistable flip-flops 94-96 The trigger signal S supplied to terminal 62 is applied to the reset inputs R of the bistable flip-flops 94-96 switched, that these are reset when a trigger pulse S is applied. The control outputs S of the bistable trigger circuits 94-96 are connected to the second input of a corresponding OR gate 82-84 connected «

Initially, when the trigger pulse S is applied to the terminal 62, the first clock pulse C ^f supplied to the terminal 60 advances the counter 76 to generate a high output level on the line 78, this generates a high output level or via the OR gate 82 the binary value ^H 1 ^H on the line 52 · The high output level on the line 52 closes the switch 46 in the switch arrangement 30 in order to switch the connection point 24 to the output 32. If the voltage at the output 32 is higher than the analog voltage V is, the output level of the comparator circuit 56 is at the higher logic level value.Only in the event that the output signal of the comparator circuit 56 has a high level value and during the negative voltage excursions of the clock signal 0 * at the terminal 60, a high output level is at the output of the AND gate 68 is generated. If such a high output level is generated at the output of the AND gate 68 when the line 78 is at a high level value, the bistable multivibrator 94 is set via the AND gate. When the bistable multivibrator 94 has been set, the control line 52 remains at its high level value. If the bistable flip-flop 94 has not been set when the counter 76 is incremented, this is to cause its output signal on line 79 to have a high value and its output signal.

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signal on the line 78 goes to a low level, the signal on the control line 52 goes from a high to a low level, or from the binary value ^H 1 ^M to the binary value ^M 0 ^{M in} such a way that the switch 46 is opened. Under these conditions, the signal on the control line 53 changes from a low to a high level and causes the switch 47 to close.

After the bit with the most significant value has been determined, the output of the control logic circuit 58 for the bit with the second most significant value is brought to the binary value "1". This is achieved by the local circuit of the counter 76 in such a way that the output signal on the line 79 is at a high level in order to generate a signal with a high level on the control line 50. Accordingly, the output of the control logic circuit 58 for the second most significant bit is driven to the binary value ^M 1 ^M to close switches 4-2 and 4-3. If switch 46 is closed due to the fact that the bit with the If the highest priority has the binary value "1", the voltage at the connection point 26 is compared with the analog signal V _x , and if the bit with the highest priority has the binary value "0", the switch 47 is used to test the connection point 22 and to compare its voltage with the analog signal V _x closed «. If this comparison process produces an output signal with a low level on the line 66Ό, the bistable multivibrator 95 is not set. However, if the comparison produces a high level signal at the output of ^v ergleicherschaltung 56, the bistable multivibrator 95 is set so that the output signal remains on the control line 50 at a high level value when the counter 76 continues to count again. This process continues

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continues until each of the bits has been sequentially determined. At the end of this process of successive approximation, the Output voltages on control lines 48, 50 and 5> 2 a binary word that is equivalent to the analog signal V. The output of counter 76, on output line 81, after recording of the fourth clock pulse C · has a high level value after the trigger pulse S has been generated, the bistable is set Flip-flop 74 to prevent further clock pulses C * are transmitted through the AND gate 72

In the above explanation it was stated that the execution the switch 34-4-7 cannot be carried out as discrete components Therefore, the switches illustrated in Figo 1 are schematic representations of electronic switching devices, such as semiconductor transistors, and in particular field effect transistors (FSDs). Figures 5 and 6 illustrate an embodiment of the voltage divider circuit 10 and the Switch arrangement 30 in semiconductor technology «

5 msä, Fig «6 g © s © ig '& _s dm & ®s in! Ig * 1

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gp @ n in Metall / Ossiä / äal ^ leiter ^ construction or S "schsik atifgebaut * The Spaimungsteiiersehaltesg 10 is formed from siner Selsieiat 106 from semiconductor material of a Leitimgstjps in Eis® Behl & ht 108 from semiconductor material from the opposite Leitimgst ^ p _s beisDielsweiss © in substrate is diffused. in the sogenanntezrl ^ S circuitry 106, the layer consists HalbleitermateriEl p-Leitungstjp, and the layer 108 of Halbleiterssateri & l from ni © i "& ii5iigstyp _e addition sindj as shown in FIG · and Fig. 6, a Yielsahl of Layers 110 of the same

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Semiconductor material such as the layer 106 diffused into the layer or the substrate 108. As also in Figo 5 and Pig · 6 are the source and drain electrodes of switches 42-4? by corresponding parts from the corresponding layers 110 formed.

As shown in FIG. 6, the upper surface of the semiconductor layer or of the substrate 108, together with the layers 106 and 110, is covered by an oxide layer 112. The thickness of the oxide layer 112 is reduced in the subregions 114, and these relatively thin subregions 114 form the oxide layer for gate electrodes, these bridge the gaps between corresponding subregions of the layer 106 and the layers 110 ₉ as well as the gaps between corresponding subregions between adjacent layers 110. Its metallic layer 116 overlies the oxide layer 114 of each gate electrode. The oxide layers 114 of the gate electrodes and the corresponding metallic layers 116 are shown in FIG. 5 by dashed lines. Each metallic layer 116 thus forms the gate electrode of each of the field effect transistor switches 34-47 in MOS circuit technology.

From Fig. 5 and Fig. 6 it follows that the following advantages are provided by the Embodiment of a digital / analog signal shown in FIG. 1 converter can be realized:

the voltage divider circuit 10 consists of a continuous strip is formed from semiconductor material, there are no ohmic contacts to connect the adjacent resistors 12-19 with each other. Since corresponding sub-areas of the semiconductor

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Layer 106 act as the source electrodes of the MOS field effect transistor switches 54-41, so no additional ohmic contacts are required between the voltage divider circuit 10 and the switches 54-41. Because of the layers 110, there are also no additional ohmic contacts between the switches in the Switch assembly 50 required. Furthermore, since in the preferred embodiment of the invention the output of the switch arrangement 50 is connected to a buffer amplifier or comparator in what is known as the ⁿ I PED ¹¹ or ^M MOS "circuit technology, the MQS field effect transistor switches 54-47 carry no current If the MOS field effect transistor switches 54-47 carry no current, no error is generated by a current flow · Bs also follows that adjacent resistors among the resistors 12-19 have a mismatch of up to to ^ O # without causing insufficient accuracy as a result, however, larger portions of the voltage divider circuit 10 should be matched to a lower percentage of error to maintain acceptable accuracy for the higher order bits of the binary word being converted ·

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709810/0801

Claims (1)

PATENT CLAIMS 1. converter circuit for converting a binary signal in bitparalleiern format into an equivalent analog signal, characterized in that a voltage divider _{circuit (10) is connected in parallel to a reference voltage source (V R} ) and has N-1 outputs (21-27) that each of these outputs is assigned to the corresponding binary word (ABC) from a multiplicity of binary words which are equivalent to the numbers from 1 to N-1, the said binary words having η bits, and where the following applies that a plurality of switches (54-47) is connected in a switch arrangement (30) between the corresponding outputs (21-27) of said voltage divider circuit (10) and an output (32) of said switch arrangement (30), that said switch arrangement (30) N-1 current paths with η switches in each current path shows that the idle state of each of the mentioned switches (34-4-7) springs from the current path © in © ntspreefeendes BiBä3? W © ^ -fe (J®0) a multitude of binary word © nf © increases _s di © & © si numbers, from 1 to 1-1 are equivalent ₉ where J © d © E »dsr g @ siaiaa1j © a switch" in each current path the state of a corresponding bit of a binary word with η bits corresponds to rad according to this state, ο can be actuated 2 «Converter circuit according to claim 1 _5, characterized in that it comprises a control logic circuit (^ S) for generating a binary word with η bits and for supplying this binary word to the corresponding switches (34-47) which are each assigned to this bit. - 23 709810/0801 26379R1 3. converter circuit according to claim 2, characterized in that said control logic circuit (58) comprises a circuit (56, 68, 70, 72, 74, 76, 82-84, 86-88, 90-92, 94-96) to carry out an analog / digital signal conversion with successive approximation, which between the output (32) of said switch arrangement (30) and each of said switches (54-47) is switched 4o converter circuit according to claim 1, characterized in that said voltage divider circuit (10) is an integrated Circuitry executed circuit module (12-19) comprises, which consists of an elongated strip (106) of a semiconductor material is formed by a first conductivity type which diffuses into a semiconductor material (108) of the opposite conductivity type is that each of said switches (34-47) is implemented in integrated circuit technology, and that a sub-area of said elongated strip has a connection of at least one of said switches (34-47). 5 converter circuit according to claims 1 and 4, characterized in that that each of said switches (34-47) is a field effect transistor and that each of a plurality of portions of said elongate strip (106) is the source K electrode of corresponding among at least some of the field effect transistors mentioned (34-40) forms. 6. converter circuit near claim 1, 4 and 5 »characterized in that that each of the ax of said voltage divider circuit (10) connected switch (34-40) is an integrated circuit executed field effect transistor, in which a corresponding 24 - 709810/0801 The corresponding portion of said elongated strip (106) forms the associated source electrode, so that each of these switches (54-40) comprises a layer (110) of semiconductor material of one conductivity type diffused into said semiconductor material (108) of the opposite conductivity type and having a certain distance from said elongated strip (106) to form the drain electrode of this ^ö chalters that an oxide layer (112, 114) drain mentioned above and the source electrode, and in that a metallic layer ( 116) lies over said oxide layer (114) and forms the gate electrode of this switch. 7 · converter circuit according to claim 6, characterized in that each of the switches (41-4?) not connected to said voltage divider circuit (10) has an integrated field effect siransistor Circuit technology whose source electrode (110) at the same time forms the drain electrode of at least one other switch, and that this drain electrode is a layer (110) of semiconductor material of the first conductivity type, which is diffused into said semiconductor material (108) of the opposite conductivity type 8ο converter circuit according to claim 1, characterized in that said voltage divider circuit (10) has N outputs (20-27), each of which is a binary word from a plurality of binary words that are equivalent to the numbers from 0 to N-1 are that said holder assembly (30) with N current paths η switches (34-47) in each of these current paths, and that the Idle state of each of said switches (34-47) in each current path a corresponding binary word from a plurality of - 25 - 709810/0801 2 B 3 7 9 Π 1 Defines binary words that are equivalent to the numbers from 0 to N-1 are· 26 - 709810/0801