DE2627628A1 - INTERNALLY PROGRAMMABLE DATA PROCESSING SYSTEM - Google Patents

Description

_.HeinpEvd (
Patent attorney
I Malchin 22. Herrnsir. 15, Tel. 29 255S Postal address Mischen 26, Posnaci 4 ä.DZ / D / 0

Munich, June 19, 1976

My reference: P 2360

Applicant »HONEYWELL INFORMATION SYSTEMS INC.

200 Smith Street
Waltham, Mass., USA

Internally programmable >> Data processing system

The invention relates to an internally programmable data processing system according to the preamble of claim 1. In particular, the invention relates to an improvement of digital computers in the area of database operations.

The hardware of electronic computers has changed from a first generation created by the use of electron tubes was characterized, through a second generation, which was characterized by transistors, to a third Generation developed in the main by

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is mainly determined by integrated circuits. In connection with these different generations of hardware was made use of different generations of software, the first generation software mainly through the machine language, assembler and subroutines were determined and the software of the second generation by high-level programming languages, characterized by monitoring programs and microassemblers was. The third generation software is characterized by operating systems, online real-time systems, Multi-program systems and database management systems.

The hardware of the first generation together with the software of the first generation and also the hardware of the second Generation together with the software of the second generation were primarily aimed at batch processing, the execution of the jobs was primarily carried out in a serial manner. Furthermore, there were the hardware / software systems of the third generation also aimed at a batch processing, but due to the emergence of multiple programming different jobs could be processed in parallel instead of serial way and with these Systems allowed the inclusion of input information for processing when it was generated.

The fourth generation systems will typically be classifiable as communication and control systems that are characterized by widespread processor applications and that are primarily stimulated by transmitted data rather than batch programs. The system is controlled primarily through input information instead of intervention by the operator, the information suppression generally taking place in real time.

In developing the above mentioned generations of computer systems, a key requirement was to develop effective methods for accessing the database of the computer system.

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In the beginning, one came to the development of the system databases a large number of different databases according to the application. As a result of this growing number of databases Problems arose with regard to the requirements for the memory and with regard to the redundancy of data storage, which was additionally made more difficult by the problem that the redundant data at different times in one place has been updated correctly and incorrectly elsewhere. There were steps Taken to address these problems by integrating the many databases of a system into a single database became. Honeywell's Integrated Data Storage (IDS) is an example of a system that has been designed to avoid these problems. The integrated data memory was composed of a central database, which for example could be used by the inventory management system, internal booking procedures and payroll procedures, by accessing the relevant data in the database. In this central integrated database there is a single data record that describes a piece of information, the various functional requirements are common. For example, inventory management and internal Make a booking based on the number of a given item in a department store.

Using continuously improved software techniques, effective techniques for using integrated databases have been developed. The group concept is a technique that allows access to data records in the integrated database on the basis of relationships between the data records. A typical relationship is, for example, all employees in a certain department, for example in the production department. The production department can be assisted by a. User record can be described and the employees within the department can be described by a member record. The group which describes a relationship, such as membership in a department,

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can then be accessed through the member's data record which allows the software to extract all member records and thus all employees within, for example of the department.

At this stage of development, the integrated data memory can solve some of the pure data problems mentioned above, ζ.Β »the problem of redundant data in different databases and the problem of adding multiple copies of records. The problem was caused by a single record solved, which thus allowed a reduction in the memory size for the data and a single copy of the data. Other Database problems persisted in the execution areas. The group concepts introduce new techniques represent regarding the use of the computer; however, from this point on there were no specialized hardware commands for the Central processing units of the computers to support these new technologies. As a result, a group operation, such as finding the first member of a group, in terms of software only through a series of Standard machine commands such as add, load, save, etc. can be implemented. The result is quite a long computing time for relatively simple group operations, such as finding the first member, putting a record in a group and other group operations.

There is thus, on the one hand, a need for a database system that solves the traditional data problems that have already arisen through integrated data techniques have been solved using group operations, as well as on the other hand at one effective database system in terms of execution time and other system performance parameters. To this to be achieved would be specialized, through hardware / firmware

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Supported commands required to provide assistance with group operations. For example _, a single command relating to a database address of a user record of a member record (member and user records are described below) in a register would require execution within a much shorter period of time than a series of five to ten extended machine commands to perform the same operation in a traditional machine.

The invention is accordingly based on the object of an improved To create general purpose digital computers. The new general-purpose digital computer to be created is also intended to be an improved one Have capability in database management operations.

The object indicated above is achieved by the invention characterized in claim 1.

According to the present invention, an internally programmed data processing system is created with a memory which consists of a plurality of addressable memory space segments, each segment having a segment number and being limited by upper and lower variable limits. Each segment _s is further subdivided into at least one page which is accommodated at a specific assignment address within the segment and which has an identification page number. Each of the database records or records for storing a large number of files is grouped into groups of database records or records. Each group has at least one user record or one user data record. Each of the pages also contains offset address information for the

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locate each of the database records a selected group of said groups from a specific position on a selected page of said groups Pages. This data processing system also has at least one index register for storing a selected one Database index address, comprising a database pointer address, which forms an address of a specific database data record of said database data records. Everyone of the database records having at least one of the database pointers includes one. Area, one side and one Line address. The area address is used to determine the location of a specific file of database data records; the Page address is used to determine the location of a specific group of the database data records within the named file. The line address is used to define the specific one data record of the database data records. The relevant data processing system further comprises command hardware responsive to a serial search command; this hardware includes:

a) a segment number generator device which, in response to an area and page address derived from the command, sends a Segment number generated;

b) an address ^ converter, which the segment number converts to an absolute address for the local designation of the relevant page with respect to a system base;

c) a display setting device generated by the address translation device controlled within the said page provides a display which is used to determine the Availability of a selected database data set with regard to the relevant advertisement is used;

d) Loading devices which, controlled by the display definition device, load the relevant area ^ the relevant 3 »ίΛψη * · and the relevant line number into the corresponding index register when the selected database data record is available.

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The invention is exemplified below with reference to drawings explained in more detail. Ss show:

1 is a block diagram of a multiple program system utilizing the invention;

Fig. 2 is a schematic representation of various, from the Invention of the hardware structures used, FIG. 3 shows a list of expressions which are used for reserved memory areas are used in registers of Fig. 2, Fig. 4 is a schematic diagram of a process control block of a machine used by the invention; Figure 5 is a schematic diagram of a system for addressing a process control block,

6 is a schematic diagram of the system base of a computer system using the invention; Figures 7A and 7B are schematic representations of a stacking segment and a stacking frame of one utilizing the invention Computer system,

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Figure 8 is a schematic diagram of a system for addressing of G segments and in particular the queue of processes in the G-O segment of a computer system according to the invention ,

Figure 9 is an expanded schematic diagram of a G-O segment, which is the queue of processes and the process connection of a computer system according to the invention represents

Figures 10A to 1OL are block diagrams of structures in the process control block _t

Figures HA to HR block diagrams of structures in the System base,

Figure 12 is a schematic diagram of user and system segment addressing schemes supported by the system base and making use of the process control block structures, Figures 13A through 13C are schematic diagrams of the control unit according to the invention,

FIGS. 14Λ to 141 are flow charts of the distribution unit in FIG Firmware of the computer system according to the invention, FIGS. 15A to 15H, diagrams of the data records and their information addresses as used in the group commands, FIGS. 16A to 16C are diagrams of the database page format and the descriptors that describe these pages, Figure 17 is a flow chart of the firmware as it is used, to store a database page in main memory, FIG. 18 is a block diagram of a hardware mechanism for for finding a database page in main memory, FIGS. 19A and 19B are diagrams of descriptors, the groups and describe records used by the database commands.

Figures 20A to 20F are diagrams of instruction formats used by the "Database" commands.

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Figs. 21A to 21B are flow charts of searching for one User-related database command in firmware / hardware,

22A through 22D are the logic block diagrams for an in Hardware executed database command regarding the search for a "user,

Figs. 23A to 235C are flow charts of a lookup related Serial Database Instruction in Firmware / Hardware, Figs. 24A, 24b and 25 Linking Block Diagrams of a Das Search of relevant serial database commands in hardware, FIG. 26 shows the flowchart of one executed in firmware / hardware Check Record Type Database Instructions, Fig. 27 is a logic block diagram of one in hardware executed database command of a test data record type, FIG. 28 shows the flowchart of an unloading database command in firmware / hardware and

29 is a logic block diagram of a hardware unload database instruction.

The tools used for a database command relating to finding a user, finding a Serial audit record type or a discharge in a large Computer systems are necessarily complex; Typically, such tools can be found in a Honeywell Series 60 calculator. In addition, a complete Understanding of the teachings of the present invention can only be achieved once the reader is familiar with the art Computer technology and is familiar with the tools used. Because of this, it is considered desirable considered to explain at least briefly the general structure of a typical large data processing system in which the principles of the present invention can be applied to advantage. It should also be considered desirable

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should be considered first to explain the basic concepts on which the present invention is based.

The database group concept combines various techniques (tables, lists, chains, rings, files and field arrangements), used in most known computers, particularly in their programming. The present Concept is a specialization of the more general mathematical group concept from which the data structure group receives its name and many of its properties. In this context, the word "group" is always used in the sense of a data structure and not used in a mathematical sense.

Many systems support the group concept, but this support is only provided by software. In the area of database management, the integrated data storage system (IDS) from Honeywell first made extensive use of the group concept in order to deal with complex manufacturer and bank problems. The integrated data storage system makes use of the chain form (ring form) of group realization. These basic concepts are implemented in terms of hardware or firmware; they aind present in existing computer so that new and improved digital computer to be created.

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The group represents one of three complementary concepts (record, field and group) that are used to create and store of data structures are required, these data structures having an equivalent in the natural environment Find. If the natural environment is viewed in terms of existing system elements, then those describing them lead Properties and the relationships between them to the following corresponding information system concepts: record, field and group. In a simple example taken from the school sector, the system elements can, for example, be the teachers and describe the children. Some of the assignments for the teacher are determined, for example, by the name, the level of training and the classroom. Likewise, some can Assignments for the child are given by first name, age and family name. Between teachers and children there is a certain relationship. In an information system model for this natural environment, two classes of Datasets are created, one assigned to the teachers and one assigned to the children. In every teacher record There is a field that stores the name of the teacher, another for the level of training and another for the number of the classroom. Each child record contains corresponding fields for first name, age and family name .

The information system can match the child record with the teacher record link in different ways, with the appropriate linkage to realize the group concept must be selected. This can be done, for example, by all of the children’s records after their teacher’s record be arranged in the file. Such an arrangement is then referred to as a table or data record arrangement. the The present embodiment makes use of the technique of chain or ring implementation of the group concept. In this Form, the user data record contains a reference address to the first member data record. Each member record contains in turn, a reference address to the following member

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Record. The last member record of the group contains a hint address that refers back to the user record. Variations are allowed, which the user record or the user and all member records with additional Note address fields are provided with the address of the previous record and possibly a note address to save the user record for member records.

The data structure group concept described above is a refinement of the mathematical group concept, i. H. in the case of the user role, the group definition is contained in the data structure group. The group membership is included in the case of the membership role. The records can have many roles as users and members of various on an ongoing basis Groups included. This property allows the creation and handling of complex structures, thereby reducing the Complexity of the actual environment can be reproduced. In this refinement of the mathematical group concept one reversible either from a user to the members or from any member to the user to go to in this way to restore the group definition.

With regard to the data structure groups, the group definition is normally based on the value of any field or fields within the user record, while membership in the group in the computer is based on the adjusted value of an equivalent field or fields within a potential member record such as produced. Often times, this phenomenon can be taken advantage of by removing the field from the member records that have the customized data and depending on the user record for re-establishment.

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In the school example mentioned above, it was said that a teacher played the role of a "user" of a teacher / children group [ owns. To extend this example, let us note that in most schools the relationship between teacher and child is not a simple relationship (l: n), but rather a rather complex relationship (now), since the Children have different teachers for different subjects. This complex relationship of teacher: child can be in a new relationship system element can be converted: "pupil", so that two simple relationships result; Teacher pupil and child: pupil. The teacher has many children as students in his class, and as a student, the child has multiple teachers. The new system element "Student" has the assignment "Subject" and "Lesson", which are used to describe and differentiate serving one relationship system element from another. A child can use the same teacher for different ones Have class subjects.

The data structure group concept has four basic properties:

1. A group has one and only one data record in the user role.

2. A group has zero, one or more records in

the membership role and the number changes over time.

3. Any record can be the user of zero, one or more groups at the same time.

4. Any record can be a member in null, one or several groups at the same time and thus simultaneously through different user data sets to be used. Each record can only appear once as a member of a particular group. the Member roles do not overlap with user roles.

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The determination of "next" and "previous" is important for the procedural algorithms that are used to solve the problem reside in a computer with stored myzu. In addition to the procedural limitation of treatment to one data set at the same time there are more important simplifying consequences for an algorithm if the Member records within the group the algorithm in a predetermined ordered order of the data values or can be offered in an orderly sequence of temporal insertion (FIFO, LIFO). The statements of "first" and "last" are essential for starting and stopping the iterative execution of the data algorithm. The order of the Members in a group is therefore a prerequisite for efficient handling of the group.

The main motivation for arranging records in groups within a file is to simulate realities the natural environment and in facilitating access to selected records within the File / that represent some special relationship. The methods for accessing groups vary to some extent the known access methods and, on the other hand, complement these known methods. These access methods are in the below Table listed.

Table I.
Access methods

Direct access method Finding a data record

Data key access method Finding a data record Group user access method retrieval of a data set group member access method Iterative use; Prospecting of every member of a group

Sequential File Access Iterative Use; Aufsumethode ^x monitoring of each record

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The first four access methods are primarily used for Settlement and search procedures use, where required, the recorded status of a particular system element or a related group of system elements or, if there is a need, the recorded Bring the status of the system elements up to date. The sequential file access method is primarily used when adding periodic batch files. It is possible to access the same data set through all five methods To gain access if the opportunity so requires. It is accordingly possible to combine these access methods to use to achieve a special effect.

If the previous example is taken up, it is possible that the data record assigned to a teacher can be accessed using the data identification key access method is found again and that then all records relating to the students by the Group member access method. For each The student record can be the child record with the group user access method be found. Alternatively, the data can be retrieved with the data identification key access Start with the child record and then access all records relating to students and teachers. The basic recovery options that can be derived from the group are shown in the table below specified.

Table II
Recovery options

Given

user

user

Group member access method

Group member

Finding

First member or finding an empty group First member or finding, that lying outside the group

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User Group member Last member or

Detection of an empty group

Any group member or next member

Member noting that last

Member of the group

Any group member Previous member

Member or finding that

first member of the group

Any group user User of the Member group

There are a number of basic procedure operations which regarding of the groups apply. These are complementary to the basic procedure operations for the records and fields, which are better known. The collection of basic procedures (hardware / firmware commands) can be used in terms of operations Fields, records, groups and procedural logic control can be divided.

The following group of hardware / firmware commands is used to manipulate data within fields. Suppose that the information descriptive of the field, e.g. the size, the storage space and the recording mode, required for execution needed for an operation is given as part of data descriptors associated with the operation. The ones in this group The operations included are, for example: move, compare, check, add, subtract, multiply and to divide.

The following group of hardware / firmware commands performs both direct as well as serial access when processing data. These commands are for the Creation of a data set, its subsequent retrieval,

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its modification, its review and its division provided. The firmware / hardware commands with regard to the data record are as follows: creation of the data record, destruction of the Data record, direct location of the data record, serial retrieval of the data record and test of the data record type.

The following group of hardware / firmware instructions lead to the foundation of conventional data processing and formation of blocks for advanced database and message management systems. They are used for education, access, handling and reviewing groups. The hardware / firmware commands are as follows: insert a data record, Removal of a data set, finding a relative data set (first, last, next, previous, etc.), finding of a user data record, testing: whether group is empty, testing: whether member inserted, triggering user data record and Trigger member record.

The following group of base register hardware / firmware instructions enables the determination and modification of the one currently in progress Process status related to the database access. The hardware commands are as follows: unload the base register, Zeroing the base register and the aforementioned "find" · Instructions that load a ~ base register.

Just as well as the groups can be used to create records They can also be organized in an application database and given access to them in a A wide variety of system software areas can be used. Below is a list of areas of the system software listed in a table, with some application cases listed for each area of the group concept. This list ηυς provides an example of some obvious use cases and does not claim to be complete.

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1. Database systems

a. Index construction (sequential index and optional index)

b. Data description structures

c. Shared tax lists

d. Process-dependent structures

2. Date! Systems

a. Catalog construction

b. Access right control

3. Message systems

a. Formation of mailbox indices

b. Queue messages ·.

c. Access to multi-element messages

4. Programming systems

a. Control of program libraries

b. Text output

c. Program control structure

d. Symbol reference and symbol definition structures for grouping

e. Intermediate program form for compilation

5. Operating Systems

a. Queues of jobs

b. System resource allocation tables

c. Determination of a final standstill

d. Queues of processes waiting for events

(Input / output completion, timer)

e. Distribution queues

t.

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I. General explanation

The invention works with a hardware system which is coordinated by a hardware / firmware / software operating system. In FIG. 1, the processor subsystem 101, the memory subsystem 102 and one or more up to 32 peripheral subsystems 103 are shown. The processor subsystem includes a central processing unit (CPU) 104 and up to four input / output control units (IOC) 105. Each peripheral subsystem consists of a peripheral control unit (PCU) 106, a number of device adapters (DA) 107, and up to 256 peripheral input / output devices 108. The memory subsystem 102 consists of one to four semiconductor memory modules, each with a memory capacity of 32 to 512 kilobytes. In the processor subsystem 101, the central processing unit 104 performs the basic processing operations for the system and works in conjunction with the memory 102. The I / O controller 105 controls the entire exchange of information between the storage subsystem 102 and the peripheral devices 106.

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A. Central unit

The central unit comprises a main memory synchronizer 109, a buffer memory 110 and several elements forming the arithmetic unit 111 and optionally emulators 112. The main memory synchronizer 109 prevents difficulties in the use of the main memory by the arithmetic units 111, the buffer memory 110 and the input / output controller 109 Synchronization takes place on the basis of priorities: The input / output control has the highest priority, followed by write operations in the memory (triggered by the processing unit) and then followed by
Read operations in the memory (transfer to the buffer memory). The central unit also contains the address control unit (ACU) 131,
which controls the addressing of the main memory, as well as the associative memory (AS) 132, which is used to store the addresses last used in the main memory. The buffer memory 110 is a pure high-speed buffer memory which reproduces a selected area of the main memory and is in exchange with the arithmetic unit in order to reduce the average memory access time. Each time the memory is read, the buffer memory and the main memory are accessed. If the
If the information to be retrieved is already in the buffer memory, the reading process in the main memory is terminated and the information is retrieved from the buffer memory. Otherwise the main memory 102 is read out. Each time this occurs, the central processing unit 104 retrieves 32 bytes containing the desired information. This remains in the buffer memory for future memory reference. Since this is permeable to software, this can
the program controlling the computer does not determine at a given time whether the information processed by it was taken from the buffer memory or from the main memory.

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The computing unit 111 handles all data processing and address generation within the central unit. A typical control memory 130 within the arithmetic unit 111 (cf. Book "Microprogramming: Principles and Practices by Samir S. Husson, Prenticse Hall, Inc.) contains firmware that the system starts the central processing unit 104 and the input / output control 105 controls and an unillustrated command group decoded. Optionally, the control store can be scientific Deliver commands, test routines, emulation packages or special purpose features that expand the capabilities of the processor subsystem. As a further option, the central unit enables the emulation of other systems. The emulators 112 are part of FIG Firmware or software and in some cases hardware.

B. I / O control unit

The input / output control unit 105 of the processor subsystem forms the data path between any peripheral subsystem 103 and the Storage subsystem 102. This path enables peripheral commands to be initiated and controls the resulting data transfer. An input / output control unit can usually operate up to 32 channel control units, not shown in detail.

C. Peripheral Subsystems

The peripheral control unit is in a peripheral subsystem 103 according to FIG (PCU) 106 an independent microprogram processor, which reduces the load on the central processing unit 104, that it controls the input / output devices 108 during the input / output operations. The peripheral control unit 106 accomplishes this by executing commands in a channel program. This program results in arithmetic, logical, transmission, Shift ^, and branch operations which are carried out in the peripheral control unit be performed. There are various types of peripheral control units according to the types of devices that are dio can be controlled: For example, data record unit, mass storage (disk), magnetic tape, information transfer, etc.

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The device adapter 107 lies between each peripheral control unit and the devices it controls. Each adapter contains predefined Firmware and logic circuitry required to establish communications with a particular device are. Depending on the type, a device adapter 107 controls one or more devices.

The main functions of the peripheral subsystem 103 are as follows:

1. Conversion of CPU instructions into a sequence of for the ent- j speaking peripherals acceptable commands. !

2. Compression and expansion of data in those from the central; unit or suitable peripheral devices ₍ form.!

3. Informing the central unit of the status of the subsystem and the business under its control; rate. ■!

4. Independent initiation and execution of errors and; Recovery procedures.

5. Enabling on-line diagnostics without interference

the possibility of sharing devices through! the assigned peripheral processor. ι

A peripheral control unit eliminates the main memory: Difficulties between the devices assigned to him, however solves < the input / output control difficulties between the peripheral control units.

D. Storage Subsystem

Each memory module 1-4 is 4 or 8 bytes in size. The number of modules, their scope and the data flow can vary accordingly change the size of the calculator. The memory modules are pierced fourfold in such a way that four modules follow one another are accessible (module 1 contains the first 8 bytes, module 2 contains the second 0 bytes, etc.). The shooting through reduces the Number of access conflicts to the main memory and thus reduced also the mean memory access time. The memory can be in In the event of errors, the memory blocks within a module can be rearranged without destroying the neighboring

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removed. The main memory 102 consists of a capacitive one Storage medium in the form of metal oxide semiconductor chips (MOS), this medium works according to the refresh principle Maintaining information. Each space is typically refreshed at least once every 2 ms. The construction ensures that there is little conflict between the recovery for the timeline and memory access. In the event of In the event of a conflict, refreshment has priority.

An area at the beginning of the main memory is reserved for hardware and firmware. The upper limit of this range is through determines the content of a boundary address register (BAR) which is visible to the system software. The content of the border address register is determined when the system is started. The memory area below that in the limit address register specified address can contain input / output control tables that configure the peripheral subsystem, firmware to control the central processing unit or define microprograms and tables for emulation. The scope of the area below that mentioned Address depends on the system configuration. Whether microprograms are in the main memory or in the control memory depends also depends on the system structure and the application of the system.

2. Basic machine structure on

There are typically three basic data structures in this hardware used: data formats, registers and command formats that can be recognized by software.

A. Data formats

The information is between the memory and the central processing unit transmitted in multiples of 8 parallel bits. Every 8 bit information unit is called a byte. Parity or error correction data are also exceeded with the data, but cannot be influenced by the software. In the following Description closes the expression data which are

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associated parity and error correction data.

B. Byte s

The bits within a byte are numbered from 0 to 7 from left to right. The bytes are separated or in groups processed. Two bytes form a half word, four bytes form a word, eight bytes form a double word and 16 bytes form a quadruple word. These form the basic formats for all data including commands.

C. Data presentation

All data are in binary form, but can be binary or decimal or can be explained alphanumerically. Data bits are interpreted as binary coded decimal data in groups of four; in Groups of eight as alphanumeric or 16 to 64 as binary digits. The latter are viewed as having signs, fixed or floating numbers in binary representation. Any number of consecutive Bits up to a double word can also be processed as a bit sequence (string). The group of alphanumeric characters is represented in EBCDIC. ASCII is used as an alternative selection code.

D. Byte addresses

The byte storage locations in the main memory are numbered consecutively starting with zero. Each number represents the address of the relevant byte. A group of consecutive bytes is assigned halfword, word, doubleword or quadruple word if the address of the left byte in a group is a multiple of 2, 4, 8 or 16. As soon as a half word, word, double word or quadruple word is arranged in this way, the unit can be called up from this address. The storage space of data in the main memory is determined by a data descriptor, which is created directly during address development.

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E. Recognizable registers

There are 33 registers recognizable to the user in the central unit 104 according to FIG. 2a, the contents of which together indicate the status defined by the central unit. There are four types:

1. General register

2. Base register

3rd scientific register (as an option)

4. various registers

F. General register

The general registers (GR) 201 in Figure 2b are used for processing used by fixed binary numbers and bit strings. There are typically sixteen 32 bit general registers in the central unit 104, which are designated by GRO to GR15. The general registers GR8 to GR15 can also be used as index registers. In this case, they will later be referred to as XO to X7. Indexing is done using what is contained in a register 32-bit integer. Two's complements.

G. Base register

The base registers (BR) have the same format as instruction counters (IC) and as stack memory registers 202 to 203. The base registers are used during the address calculation to determine part of the memory. There are usually eight 32-bit base registers named BRO to BR7.

H. Scientific Registers (Floating Point Registers) Scientific Registers (SR) are optional equipment for calculating with floating binary numbers. Usually there are four scientific registers of 8 byte type, designated SRO to SR3. The scientific registers have the format 204 to 205 in Figure 2b.

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I. Various registers

There are five other registers, namely:

Command counter with the format 202 to 203; Status register with the format 207;

Stack registers called T registers; Boundary address registers with the format 202 to 203 and hardware control mask registers with the format 208.

The command counter (IC) is a 32-bit register which contains the addresses of the commands to be executed. The status register (STR) 207 is an 8-bit register which stores the facts about the currently running procedure, for example whether the most recent operation has undercut the range. The stack register, known as the T register, is a 32-bit register that contains the pointer to the top of a memory stack to be torn down that is assigned to the currently active procedure. The stack memory provides the work space as well as a mechanism for ensuring local variables and for providing procedure entry points and return information. The Boundary Address Register (BAR) 206 is a 28 bit register that indicates the lowest absolute main memory address accessible to the software. This register is loaded when the system is started up and can only be read once by the software. The hardware control mask register 208 is an 8 bit register that holds machine status information.

J. Command formats

There are about 200 commands, although more or less can be used as well. Each command has one of four different lengths but always has an even number of bytes. Commands are stored in consecutive memory locations. The address of the leftmost byte is a multiple of 2 and forms the address of the command. The first eight bits (and in

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in some cases bits 8 to 11 or 12 to 15) of a command represent the opcode, while the remaining bits correspond to one or more operands. An operand can be a register identifier, a displacement identifier, an address syllable (logical address), a literal value or an immediate Represent literal value. The type and number of operands are determined by the command format.

3. System organization

A. Job step and task

The work to be carried out by the computer system is determined externally with the aid of the job control language through a series of job steps. A job step is a unit of work that comprises the hardware system elements be assigned. A job step typically consists of different tasks. A task is the smallest unit of the User-defined work and consists of a flow of information that is processed without parallel operation.

B. The process The concepts of tasks and job steps that are recognizable to the user are represented in the hardware by a process or process groups. A process is defined as an ordered sequence of commands which can be executed asynchronously by the central processing unit, ie several processes can be active and use synthetic elements at the same time. However, only one process is running at a time. A process group is a related group of processes required to execute a job step.

C. Process control block and system base

Since process &. ^L can relinquish control by the central unit during its execution at various points, a memory area is made accessible in the main memory for the process for saving the state of the central unit. These conditions-

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information is used to preset the central unit before a process takes over control of the central unit again. This storage unit is called a process control block (PCB) 400 (see Figure 4). Contains the data in the process control block the addresses of the memory area assigned to the process <address space) , the content of all associated registers and the status of the process. Thus, the process control block serves as a temporary one Storage area for the information required to start or restart a process without loss of information. Each process control block can be recognized by the hardware and can be defined by the operating system via a group of hardware tables, which are developed during system preparation and modified during operation are addressed (Figure 5).

There is an absolute main memory area that serves as the system base is designated (Figures 5 and 6). This area is developed by firmware and is accessible via the base address register (BAR) accessible from which read but cannot be written into. The system base 502 contains a number of system attributes, which is a job step number and a process group number Include (J, P) for the current process. Another attribute in the system base is a pointer to a through Hardware defined data structure known as J-table 503 is. This table contains an entry point for each job step currently in the system. Every entry point in The J table 503 points to an associated P table 504, which likewise represents a data structure defined by hardware. This table defines a process group and contains an entry point for each process in the process group. Every P-table entry point points to a process control block 400.

In Figure 5 ... 1, the J number over the arithmetic Part 506 of the computer unit 111 (see Figure 1) indexed reference address Access to a J table entry point 503. This in turn contains a P-table pointer, which if they

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is indexed by the P number via the arithmetic unit 506, access to a P-table entry point 504. Latter contains a pointer address 507 to the process control block of the current process. The operating system thus has access to the active process control block and uses the contents of the limit address register 501 for this purpose and can use any other process control block which is given by its assigned logical name (JP).

D. Memory segmentation

In a multiprocess plant there are at a given time many processes in memory. These processes have different scope and different memory requirements, which means a memory allocation problem arises. The hardware in cooperation the operating system, not shown, solves this problem by dynamically allocating memory space. As a result of The memory space is allocated in the form of segments of different sizes, and the random nature of memory requirements Memory allocation can be reorganized during process runtime will. Thus, a number of non-contiguous memory segments can be allocated to a process. This kind of Memory allocation is called segmentation. She represents an additional The problem is that the memory addresses have to be modified when part or all of the process is relocated will. To alleviate this problem, the present system provides a technique in which those used by a process Addresses are logical addresses instead of absolute main memory addresses. These logical addresses become absolute for development Addresses used. Segmentation also enables each process to access its own or allocated memory segments through a system of segment descriptors. By accessing a segment doscriptor, a process can determine the address of a segment obtain. Segment descriptors are located in main memory and are maintained by the operating system.

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Each process can have access to up to 2068 memory segments. Usually this would be an equal number of segment descriptors require per process. However, because the segments can be shared, the operating system shares the segment descriptors in segment tables. This grouping is based on the possibility of access by a process (task), a process group (Job step) or in general, i.e. for the entire system. Up to 15 segment tables can be assigned to each process. This technique only requires one segment descriptor for each segment accessible to the process via a segment table. Thus, the memory space required to accommodate the segment descriptors is reduced. The memory update during the rearrangement it is reduced and one gets some program protection. The main mechanism for 'program protection forms the ring system, which is the subject of older applications.

A process must be able to determine which segments it has access to. Thus the system provides the process with two segment table word arrangements (STWA). These arrangements include the. Addresses of all segment tables that are accessible to the process. It there are two segment table word arrangements per process because segment sizes are given, namely large and small. Size

22nd

Segments have a maximum size of 2 bytes, while small segments have a maximum size of 2 bytes. The difference in segment size is made in steps of 16 bytes up to the maximum size. A system can typically be up to 28 large Segments and 2040 have small segments. The segment table word arrangements can be redeployed by the operating system. Therefore a process must have the absolute address of the Know segment table word arrangements. The process control block for a process contains two words that contain this information and are known as address space words ASWO-1 (FIG. 4). Each word points to a segment table word arrangement STWA. The operating system updates the content of the address space words, as soon as the associated segment table word arrangements have been

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be switched. Working down a chain of pointing addresses and the decoding of the segment descriptor is a firmware function and, once initiated, is not even visible to the operating system.

The segmentation defines over 200 million bytes and address space than accessible to the process. This amount exceeds the capacity of the main memory. Therefore, in connection with the Main memory a secondary memory (magnetic disks or drum) is used. The operating system makes it appear that the System has a much larger main memory than is actually available. This concept is called virtual memory.

At any given time, a defined segment may or may not be physically in main memory. The content of a segment descriptor indicates whether the associated segment is in main memory or not. The hardware detects every attempt by a process to gain access to a segment that is not in main memory and informs the operating system. The operating system leaves the desired segment The operating system then inserts the memory address of the segment into the segment descriptor, which is the only place where the absolute address of a segment can be found aware that the segment was not in main memory or had to be reloaded into main memory.

The computer system described so far provides data and procedure protection in that processes are prevented from interfering with one another or in an unauthorized manner with the respectively assigned To use address space jointly. This protection is mentioned by restricting the addressability with the help of the Memory segmentation and achieved through a ring system. The segment tables isolate the address space of the various processes in the system. The processes always use one while exercising

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segmounted address. This consists of a segment number and a relative address within the segment. The hardware checks that the address used by the process is part of the address space assigned to the process. If the address is outside of the specified Address space, an exception signal Ein Picaeß appears cannot rely on data within the address space of another process because the hardware uses the segment tables of the referring Process used. This means that there is no possibility for a process or a process group to assign a system element which belongs to a different process group.

In general, there is an overlap of address space in the system for those segments which are shared by all processes. These more or less public segments are generated by system programs that check and represent a safeguard against address conflicts. The segmentation thus protects the user programs against each other and protects the operating system against the user programs. Segments that are shared by several processes are not protected against misuse by one of these processes. To solve this problem, ^{a ring system * 1 is} used, with procedure and data segments grouped into four classes or zones. The four ring zones are labeled 0 to 3. Each ring represents a certain level of system privilege, with zone 0, ie the innermost ring, having the highest privilege and zone 3, the outermost ring, having the lowest privilege. Each procedure in the system is assigned a minimum and a maximum ring number for exercise, which defines who is allowed to call the procedure. A procedure is a subroutine that is able to call other procedures and pass parameters to them. The general rules of the ring protection system are as follows:

1. A 'procedure in an inner ring has free access to Data in an outer ring. Conversely, a procedure in an outer ring cannot reach data in an inner ring

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2. A procedure in an outer ring can be turned into a procedure branch in an inner ring; however, the reverse is not allowed.

3. Two ring values are assigned to each segment with data, one for reading (RD) and one for writing (ViR). These · ring values determine the maximum ring value in which the Procedure can be executed when it reaches data in either read or write mode.

Every time a procedural command is executed, the ring number becomes of the procedure (effective address ring number EAR) with the »ring numbers assigned to the segment with the selected data. The effective address ring number represents the maximum number of process ring numbers in the command counter and all ring numbers in the Basic registers and data descriptors in the addressing path. Dependent ·

the result of the comparison of the ring numbers is either allowed or denied access to the data. For example, if a system table exists in a segment with a maximum write ring number 3 and a maximum read ring number 1, the user procedure in ring 3 can read the table, but cannot update it. By agreement, the rings are 0 and 1 reserved for the operating system, while rings 2 and 3 are reserved for the user. The ring 0 contains those segments which are critical to the overall system operation. Ring 1 contains the set of system segments whose errors do not become irrevocable Cause disruption, but could be rectified. The user can use the ring 2 for tested programs and the Use ring 3 for programs under test.

F. Procedure calls

The procedure call is an important function in the system. It is used to direct calls from one procedure to another, User procedures to use operating system services and a modular structure within the operating system too possible. A procedure call is caused by commands, as well by a system element regarded as hardware Stack memory (Figure 7Λ). A stack memory is a mechanism

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which records, stores and returns data according to the principle that the information entered last is output first will. Stacks are made up of special segments called stack memory segments. There is such a thing of a number of consecutive parts, called stack frames 701 (Figures 7A and 7B), which make up each procedure can be assigned dynamically. The first stack frame is loaded into the top of a segment, and subsequent ones Stack frames are then loaded. The last stack frame loaded is called the top of the stack viewed. The T register 702 detects the top of the stack for the currently active process. A virtual T-register consists in the process control block of all processes in the system. A stack frame 701 in Figure 7B consists of three areas: A work area 702, in which the variables are stored, a security area 703, which contains the contents of the registers and a communication area 704 into which Parameters can be entered between the procedures. Before calling a »procedure, the user must specify the registers which he wants to make sure, and he has to go to the communication area enter the parameters that are to be added to the called procedure. When the call is made, the Hardware the contents of the instruction counter IC and certain base registers in order to facilitate a return from the called procedure. Each procedure call creates a stack memory frame within a stack memory segment 701, and subsequently incoming calls create additional stack frames. Everyone Leaving one of these called procedures leads to the deletion of a stack memory frame from the stack memory. Consequently a timing of the calls is maintained, the proper * Jumps made easier. To ensure protection between procedures running in different rings, different stack storage segments are used. There is in each process has a stack segment for each guard ring . A process control block contains three stack memory base words,

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which on the beginning of the stack storage segment for the rings O, 1 and 2 that are associated with the process. The stack segment for ring 3 cannot be reached by an inbound call. Its stack memory start address becomes possible not required in the process control block.

4. Process management and synchronization

The system enables multi-process operations controlled by an operating system using a combination of software, hardware and firmware. The software creates and deletes processes within the system, while the hardware and firmware perform the multiplex processing in the central unit. In addition, a combination of software, hardware and firmware ensures synchronization between the processes. However, processes are usually not always at the beginning and end of I / O; Operations started and stopped, also during the processing of an associated job and at other times for purposes which the operating system deems necessary. A communication system is required to effectively start and stop related processes and to convey information between you. The hardware system. delivers internal messages, called semaphores, to establish a communication link between the processes.

A. Process States

A process can be in one of four possible states at a given time, namely running, prepared, waiting or suspended. The hardware takes note of these four possible process states and executes various firmware procedures .. in order to allocate the process, change the state and maintain the data structures based on the process state. The process control block contains a status field which defines the current status of the associated process. A

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Process is in the running state if it has control authority via the central unit. This condition closes the supply the central unit with address space (segment tables) and a start address. The central unit then carries out the commands in the procedural segments of the process. The J table word of the process name (logical address) of the process control block for the current process is kept in the current process word (BAR + 60) within the system base (FIG. 6). The one shown in FIG The system basis is almost the same as in Figure 6, only some details are omitted. The preparation status corresponds to the essential to the state of the process, with the exception that the process has no control handle to the central unit because it has not yet noticed the process. A "standby" one The process, like other prepared processes and the process currently running, is in competition with control access to the central unit.

A waiting process cannot continue until a specific one Event occurs, for example a message is received through a semaphore. A waiting process is not being accessed s competition with the central unit, however, with regard to the expected event, it can compete with other waiting processes stand.

A suspended process is interrupted for a period determined by the software and is later resumed. the Decision to stop the process and restart it later letting go is out of the process. A suspended process is therefore not active and has no information about the occurrence of events and cannot use the central unit. A ..> process is suspended under the following conditions:

1. In executing a termination command because all its functions have been fulfilled;

2. As a result of an interruption in the operating system and

3. When an exception condition occurs, the controller is transferred to the operating system.

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B. Process Allocation

A process goes voluntarily in the course of its actions because of its actions from one state to another or involuntarily due to the actions of other processes. The one known as the dispenser Central unit firmware controls the transition of the process between its states. The arbiter uses a group of queues to list the processes that are preparing or waiting are to be distributed. Suspended processes are controlled by the software.

Referring to Figures 6, 8 and 9, it should be noted that a prepared or waiting process is represented by a process control block and a special queue entry point called a process connection. FIG. 9 shows an exploded view of the contents of GO segment 802 and contains the process connections 803a-803b and 803c-803g of the active process as well as the free process connections 805a-805c of suspended processes. Each process connection indicates the process (J, P), the process priority and a pointer to the next process connection in the queue. There are different types of queues, such as waiting queue 803-b and prepared queue 803c-g. A hardware unit similar to the J table and known under the designation G table ( FIGS. 6 and 8) contains the reference addresses for all general, ie system-wide segments 802-8O2n. The first element GO of the G table 801 points to the segment 802 containing the dispatcher queue. A G table reference address for the G table 801 can be found in the system base 502 in FIG. 8O3g identified in GO-Segmont 802. Thus, the arbiter can check all prepared processes by polling the prepared queue 803c-803g. If the current process is its

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Status changes, the arbiter removes the process connection at the head of the prepared queue and uses the J, P name for access to the process control block. The process defined by this then becomes the next process to run.

Since more than one process can wait for the same event, there is a queue of waiting processes 803a-803b for each event. The waiting processes are also over in the GO segment lying process connections 805 are chained to one another. A pointer to the head of a waiting queue is in one Semaphore 903 available. There are a number of events a process can wait for. Because of this, a number of are in the waiting state queues located, each of which is assigned a semaphore 903, 904.

The number of prepared or waiting processes changes dynamically. This also changes the number of prepared ones and waiting queues required process connections. This fact poses a memory management problem for the arbiter This problem is solved by another queue, which is called queue 8O5a-c for a free one Process connection is referred to. This queue concatenates all process connections in the GO segment that are not through the prepared ones or waiting queues and can be prepared or waiting as an extension of a particular queue Processes are used. A pointer 901 is to the head 902 of the queue 805 for free process attachments next to the beginning of the GO segment 802.

C. Process synchronization

Process synchronization is necessary in order to coordinate the activities of two processes working on the same task. It is achieved through the use of semaphores 903-904, which data structures represent dio in the address space

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of the communication process. A semaphore is used to signal the occurrence of an event and to process message queues. An event in this sense is any phenomenon observed by one process that may be of interest to another process. The event can be, for example, in the completion of an asynchronous operation or in the accessibility of a system resource. A process uses two semaphore operations to signal an event occurrence. One operation sends a signal to a semaphore, the other receives the signal from a semaphore. The send operation is often called the V operation and the receive operation is called the P operation. The send operation allows a process to send out data or a signal that data is prepared. The semaphore stores the signal _f until another process is prepared to receive the data. The releasing process is thus free to continue working because it has released the data. The receive operation checks a certain semaphore and picks up the signal. If a signal is present, the receiving process continues. If, however, there is no signal at the semaphore, the receiving process goes into the waiting state. The semaphore then serves as a pointer to the head of a queue. The process remains in the waiting state determined by the queue at the semaphore until another process sends a signal to the semaphore in question. Thus, a semaphore can hold a signal until a process picks up that signal, or a semaphore can hold a process until a signal is sent to it.

Messages can also be forwarded from process to process. A message has the same presence or absence characteristic like a signal and, in addition, information. Part of the information is provided by the hardware and a Part through the procedure of the process that sends out the message. A message contains the process name dos send out ! Process. Thus, many processes can transfer information through one

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Send a single semaphore with the name of the sender. A message semaphore can have a queue of messages waiting to be picked up by a process will. As with signal semaphores, requirements change of storage space, which can create a storage management problem. Again, the problem is caused by a queue free communication links resolved. These connections are in a known place in a segment, which is easy to find when communication links are to be established or delivered. Because semaphores and the on The entire semaphore structure is protected. This is achieved through hardware and software conventions that allow access to each one containing a semaphore Segment ^ constrain. Thus, semaphores must be in semaphore descriptor segments some of which can be G-segments if system communication is necessary. However, all are G-segments with the exception of the segment GO semaphore descriptor segments. Each semaphore descriptor contains a pointer to a semaphore. Semaphore addresses are set with the help of a semaphore descriptor developed, whereby an additional protection for the semaphore is given. A semaphore segment can be logically used a segment number and a relative position within the segment or addressed directly by using the G, D number will.

E. Process Control Block Structures

Figure 4 shows the format of the process control block (PCB) 400. This is a storage area in main memory dedicated to a process is made accessible in order to secure the state of the central unit. The addressing of the process control block has already been explained above in connection with FIG. The process control block hint addresses 507 points to the process control block PCB in

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Storage space O in Figure 4 out. As you progress in the downward direction, the memory locations increase by 4 bytes each, while from memory location 0 upwards they increase by 8 bytes. The storage locations below storage location O are viewed as positive and those above as negative. The upward memory locations are optional and may or may not be included in the process control block. Memory locations 148 to 176 are also an option. The numbers under the memory locations indicate the shift in bytes compared to the reference memory location O of the process control block and should not be confused with the otherwise usual reference symbols. Starting with byte 0 up to but not including byte 16, four process main words PMW 0 to PMW 3 are stored, each process main word being 4 bytes long. The process noun 0 occupies bytes 0 to 3 and consists of four parts: a capability byte, a priority byte, a status byte and a decor extension byte DEXT. In FIGS. 10a to 10d details of the process main word PMW 0 are shown, further details of the capability byte 1001 resulting from FIG. 10b. There the first bit 1005 represents the calculation mode bit which indicates whether or not time calculation functions are being performed for the process. If this bit is set to ¹¹ O ", then there is no time calculation function for the process, while one takes place when the time calculation bit 1005 is set to" 1. "Bit 1006 for the scientific mode is set to 0 if the scientific register of the system is not provided and a safety area for the scientific register does not exist in the process control block PCB at bytes 148 to 176 in Figure 7. If bit 1006 for the scientific mode is at "1", the scientific option is present and is used in the process. The security area of the scientific register is used, if necessary, to save the contents of the scientific register. Bit 1007 for the code mode indicates whether a standard code group or a compatibilityUtscodc group is used by the process where ¹¹ O "

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means that a standard code group is used, while "1" in the third bit position 1007 indicates that a KombatLbilltätcode group Is used. The usual bits of the capability byte are set to zero.

Details of the priority byte 1002 are shown in FIG. 10c. The first four bits 1008 are used to set the level of priority of the process given to the given process control block PCB is assigned. Each process has one of 16 priority levels and is used to order competing processes, i.e. (a) to select one the prepared processes to be carried out, (b) for placing the processes in queues. The priorities decrease from 0 to 15 and for a given priority level the FIFO rule is applied, i.e. the first to arrive Process is issued first. The next four bits 1009 of priority byte 1002 are zeros.

Details of the status byte 1003 are reproduced in FIG. 10d. It provides information related to the process associated with the process control block PCB 400. If the process is activated, the active field bit A 1010 is set to "1". The suspension field S 1011 becomes "1" when the process is suspended. The sub-state field SS 1012 is a 2-bit field and determines the following Sub-states of the process: (a) in the case of binary 00, the process is inactive; (b) in the case of binary 01, the process is waiting in the queue the prepared processes (Q / PR / RDY); (c) in case 10, the process is waiting for a semaphore in a semaphore queue (Q / PR / S); (d) in the case of binary 11, the process is executed by the processor. The center operation field (MOI) 1013 becomes "1" when

an interrupt occurs in the middle of the operation and is taken into account during the execution of an instruction, ie before the process is completed. The decor extension mode bit EXTD 1014 is at "1" when the process is operating in an extended decor mode, ie in an emulation mode of the system. Bits 1015

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and 1016 are at ¹¹ O ". The fourth byte of the process main word PMWjO contains the decor extension number and is used when the system is operating in the simulation mode.

The process main word PMW 1 is in bytes 4-7 of the process control block PCB saved. Details emerge from FIG. 10e. Status byte 1016 is the first byte in PMW 1 and stores the contents of the status register. The multiprocessor byte MP 1018 is important for a multiprocessor construction, otherwise this field is "0". The second and fourth bytes in the process main word PMW 1 are the MBZ fields 1017 and 1019, which are at Normal operation must be zero.

The main process word PMW 2 occupies bytes 8 to 11 of the process control block and can be seen in detail from FIG. 10f. The field from bit 4 to bit 31 contains the internal name SEG, SRA 1021 of the semaphore to which the process control block is connected when the process is either waiting or suspended. The field 1023 for exception class and type contains the class and type of the same interruption exception which, after an exception signal, causes the process to go into the suspended state. Field 1022 from bit 4 to bit 15 is meaningless if the process is in a state other than those mentioned above.

The process main word PMW 3 occupies bytes 12 to 15 in the process control block 400 and points to a decor extension table. FIG. 10g shows details, where ^ the field 1024, called DETSZ, defines the number of entry positions in the table and, in the event that this field is equal to zero, the process does not have a decor extension. is permitted. The DETA field 1025 specifies the absolute address of the decor extension table in units of 16 bytes and is only important if the DETSZ field is not equal to 0. The decor extension table consists of DETSZ input. ask, each one byte long. The DEXT input

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the table determines the ability of the process in decor extension mode DEXT to work. If this byte is equal to 0, the decor extension mode is not permitted. Is however the DEXT dyte is "1", which is the decor extension number DEXT allowed. Values other than 0 and 1 are for the decor extension table number 1004 not allowed.

Bytes 16 to 23 of the process control block 400 contain two address space words ASW 0 and ASW 1, each of which is a reference address to an arrangement of segment table words. Both ASW 0 and ASW 1 have the same format according to FIG. 10h. The scope of the arrangement of segment table words is determined by the number of segment table words in an arrangement and usually includes six ASW 0 and eight for ASW 1. Das STWSZ field 1026 indicates the scope of the arrangement of segment table words at. The field STWA 1027 for the segment table word arrangement contains the absolute address STWA of the arrangement in units of 16 bytes, i.e. the absolute address of the arrangement is 16 times STWA in bytes.

Bytes 24 to 27 in the process control block contain an exception word EXW, which can be seen in detail from FIG. 10i. It contains a reference address (SEG, SRA) 1029 to an exception class table, which defines the action which a process takes after an exception signal according to its in the process noun PMW 2 must perform stored class (see Figure 10f). The MBZ field 1028 of the exception word EXW must be "0".

The stack memory word SKW in bytes 28 to 31 of the process control block contains the value of the top of the T-register on the stack of the process when it is not running is, and results in detail from Figure 10j. Bits 0 and 1 determine * elas information field (TAG) 1030. This TAG field transmits its contents of the descriptor and must for a stack memory word SKW be equal to "0". Contain bits 2 and 3 of the SKW word the RING field 1031, which contains the segment address of the Contains ring number assigned to the stack memory for protection purposes,

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and must be equal to "O" in this case. Bits 4 to 31 contain the segment number SEG, the relative segment address SKA 1032 and form a field which describes the segment in a segment table and the relative segment address within the segment. The stack memory word SKW is foitwritten each time the process leaves the flow state. Des is used to restore the T register contents as soon as the process starts. In this case, the TAG field 1030 and the RING field 1031 are checked to see whether they are equal to ¹¹ O ". Otherwise, an exception signal indicating an indispensable process control block occurs.

. is

In bytes 32 to 3ΰ of the process control block 400 the content of the instruction memory contain word ICW, which is sometimes also referred to as ICC. Figure 10k shows this Command counter content word ICW, for which the TAG field 1033 must have the binary value 00, i.e. values other than zero are not permitted. The current RING field 1034 occupies bits 2 and 3 and determines the current ring number of the process which is used for the Determination of the access rights to the main memory is used. Bits 4 through 31 determine the segment number SEG and the relative segment address SRA 1035, which is the address of the next command to be executed is given. The MBZ field in bytes 36 to 39 must be "0". It is tested every time the process control block of the names J, P receives access. If it is not "0", a PCB exception signal occurs on.

The stack memory base words SBW 0-2 occupy bytes 40-51 in the process control block 400. These words have the same format and are shown in detail in FIG. 101. You will while the stack operation cn used and every time it is used your TAG field 1036 and your RING field 1037 must be zero. Otherwise an exception signal is generated. Djue bits 4 to 31 included the segmented address 1038 of the first bytes of the stack

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memory segment for rings 0, 1 or 2. Bytes 52 to 83 of the Process control blocks 400 form a memory space, which serves as a save area for the base registers, and eight Includes words. Bytes 84 to 147 form a security area that is used to secure the values of all general registers (16 words) is used. Finally, bytes 148 to 179 are also a security area, which is used to ensure scientific ^ Register (8 words) is used.

Five double words are in the process ¹ control block. 400 is arranged above address zero for the purpose of time calculation when the bit for the time calculation mode in the process main word O is set. These words lie between the process control block address minus 8 and the address minus 40. Each word contains a time interval, expressed in ms units, in its first 32 bits, with bits 52 to 63 being filled with zeros. The remaining time double word RTO, consisting of the first eight bytes above 0 in the process control block, contains the amount of time that was actually expended by the pre-processor for the process before an end-of-time exception occurs. The RTO word is updated in the following way: Every time the process leaves the sequence state, the status of the process timer is stored in the RTO word. As soon as the process returns to the running state, the process timer status is loaded from the RTO word.

The processing time calculation double word RUA in bytes 7 to 15 is a time counter which indicates the total amount of processor time during which a process was in the running state. The calculated time is that which the processor used exclusively for the relevant process. The RUA word> t is updated as follows: Every time the process leaves the sequence state, the process time counter PT is read. The difference in the contents of the RTO word and the time counter PT is added to the RUA word. The process timer word PT is then stored in the RTO word. The time that a process is suspended is not calculated. The RTO and

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ORIGINAL INSPECTED

RUA words were also written when the calculation mode bit is set to "0". However, the words CET, RTO and WTA to be described later are only used in the process control block encountered when the calculation mode bit in the process main word PMW 0 is at "1". You will only in this case updated.

The waiting time calculation word WTA in bytes 12 to 23 is a Real-time counter, which determines the total length of time in which the process has been in the waiting state. The WTA word will updated as follows: Every time the process leaves the waiting state, the TOD reading is read from a clock of the day and the difference between TOD and the value of a word CET is added to the waiting time calculation word WTA.

The double word RTA in bytes 24 to 31 for calculating the preparation time, which is also a real-time counter represents the total time over which the process was in the prepared state. The RTA word is updated as follows: Every time the process leaves the preparation state, the value TOD of the day read the time clock and add its content minus the content of the CET word to the RTA word. The CET double word in bytes 32 to 39 indicates the time of day at which the process entered one of the following states: Prepared, waiting, running and exposed. It describes the time of entry into the current current state.

System base structures

FIG. 6 shows the format of the system base 600. It is in the absolute Main memory and is developed by firmware which over the limit address register BAR is accessible, which, as mentioned, can only be read from £ r into which cannot be written. The Grcnzadrcssonrogister BAR is located below an area in main memory that is reserved for hardware and separates this area from the system base 600. The latter contains a number of

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System attributes, which include a job step number and a process group number (JP) for the current process. The logical name J, P of the process becomes the absolute address of the corresponding process control block PCB derived. The scope and address of the J table are determined by the contents of the J table word (JTW). This word is located at the by the BAR register specific address. The format of the J table word results from FIG. 11a. The scope (JTSZ) 1101 or the J table 1204 in FIG. 12 determine the number of entry positions in the J table 1204 which have up to 255 entries can. The JTSZ 1101 perimeter field is an 8-bit positive integer. An exception signal occurs if J is greater than JTSZ. The absolute address of the J table 1204 is obtained by multiplying the J table pointer address 1102 by 16. The J table 1204 contains the J table entries, the format of which can be seen from FIG. 11b. Each J-table entry point is determined the absolute address of a P table 1205, which is obtained by multiplication the P table pointer address 1104 is 16. The scope (PTSZ) 1103 of a P table defines the number of entry points in the P table. This extent is a positive one 8-bit integer, which is typically between 0 and 255 and indicates the number of entry points in the P table. An exception signal, which indicates that the address is outside the P table, appears if P is greater than PTSZ. Each entry point of the P table 1205 determines the absolute address of a process control block 1206 by using the reference address 1107 of the process control block multiplied by 16. A presence indicator P 1105 is when it is "0" that Absence of process control block 1206. If the process control block is present, this presence indicator is at "1". is if this indicator equals "0", an exception signal occurs which indicates a vacant P-table entry. The bits 1 to 7 of the P table indicator (Figure 11c) must equal 0 (MBZ field 1106), otherwise an impermissible occurs Input to the P-Tabello indicating exception signal.

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The format byte of the G table word (GTW), which can be seen in detail from FIG. 11d, is located at the address BAR plus 4 of the system base 600. The scope and address of a G segment table 1212 are defined by the content of the G table word. The scope (GTSZ) 1108 of the G table 1212 determines the "number of entry positions in the G table, which usually has up to 255 entries. The scope field GTSZ is an integer positive 8-bit field. An exception signal indicates that you are outside the G table if the G number is greater than GTSZ. The absolute address of the G table is obtained by multiplying the G table reference address 1109 by 16. The format of the G segment table entry position is two words (8 bytes) ⁴ and is called the G-segment descriptor. The format of such a G-segment descriptor is shown in Figures 11e and 11f. All G-segment descriptors are directed and consequently the indirect bit (I) 1111 must be "0" , otherwise an exception signal arises which indicates an illegal segment dencriptor. The presence indicator P 1110 is a 1-bit field which, when it is at "1", indicates that a segment in the main memory belongs to the segment number which corresponds to the descriptor. If the presence indicator has the value ¹¹ ", then no segment is defined and a reference to this segment descriptor causes an exception signal to the effect that this segment is missing. The availability bit A1112 is also a 1-bit field which indicates whether the segment is available or not. It is only checked if this segment is defined, ie if P is equal to "1". Otherwise it is neglected. The usage display field (Uli 113! shows whether the segment has been selected or not. If the bit If U is "0", this segment has not been accessed. Otherwise, it is "1." The description display field (W) 1114 shows whether or not a segment has been written. If it is "0", nothing has happened otherwise it is set to "1." The access indicator (GS) 1115 of a G-segment descriptor must be set to "01", otherwise a appears

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an output signal which has an illegal segment descriptor indicates. The reason for this is that a G segment always contains semaphores and commands for a semaphore require that the GS code is "01". Conversely, it does not apply that all semaphores must be in a G segment. The absolute address of the base of a segment 1214 is defined in the G-segment descriptor according to FIG. He by a 24-bit basic field 1116. The content of this field is multiplied by 16 to get the absolute address. The second word of the G segment descriptor in Figure Hf comprises the bit positions 32 to 63 in the G table 1212. The RSU field 1117, bits 32 through 39, is reserved for software use and is generally ignored when it is as it is here Case is used as a G-segment descriptor. The MBZ field 1118 must again be equal to "0", since on the other hand an exception signal occurs, which indicates an illegal segment. Since the MBZ field 118 occupies bits 40 to 51, it sets the peripheral field 1119, which is the field for a small segment. Thus, all G segments must belong to the small segment type. The segment scope

1119 is a 12-bit integer positive field that defines the number of bytes in the segment. The segment scope is divided into multiples of 16. As a result, the segment size for a G segment 1214 cannot exceed 2 ^ bytes (small segments). When reference is made to a displacement D within a G segment, where D is greater than or equal to the segment circumference 1119, an exit from the segment exception occurs. The method of accessing main memory using a G segment and a shift D within the segment is referred to as G, D access. The various exceptions that can occur during G, D store operations are called G, D access exceptions.

In the following, reference is made again to the system base 600 according to FIG. There are nine system exception cell words there, which are housed in the spaces between BAR plus 8 and BAR plus 44 are. The format of these EXC words results from FIG. 11g. Because when a system exception occurs, for the transmission semaphores are used by messages for certain processes ^, the reference addresses for these semaphores are in Find new locations in memory, each of which is called a system exception cell. It is each one per class of system exceptions. The MBZ field

1120 must again be on "0", otherwise a system over-

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examination takes place. Each exception cell EXC contains the system name (G, D) 1121 or 1122. The channel exception cell is located in BAR plus 44 of the system base and has a format which corresponds to the one is similar to the system exception cell. It contains the system name G, D of a semaphore which is used for the transmission used by messages related to certain processes when the channel exception signal occurs.

Figure 11h shows the format of an internal processor queue word IPQW, which starts at BAR plus 48. The IPQW word points to the head of a queue from in the prepared state processes located (Q / PR / RDY), as indicated in FIG. 9 by the reference numerals 905 and 805. The queue connects processes in the preparation state all processes that remain in the preparation state. It is represented by the head of the Q / PR / RDY field 1124 (Figure 11h) of the IPQW word selected by pointing to the top of the queue of prepared processes. The head of the Q / PR / RDY field 1124 contains a 16-bit positive integer which is the offset from the base of G-segment number 0, called the GO segment, opposite the first byte of the Q / PR / RDY field. If this bit field is "0", the queue is classified as viewed empty. The MBZ field 1123 must again be "0", otherwise a system check signal appears.

At the point BAR plus 52 of the system base 600 is the place for the initial and current retry numbers, their Format results from Figure 111. The NFS field 1125 is a non functional memory field and is not used by the system base. The initial trial number field 1126 and the current one Trial number fields 1127 are used to control how often an automatic retry instruction is executed before a machine fault exception signal is generated. Dioou Values are loaded with the same number by a retry reset counter, not shown.

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The sequence process word RPW shown in FIG. 11j is located in memory location BAR plus 56 of the system base and is used to store the name of the current process and in the case of a Monoprocessor structure used with its priority. The NFS fields 1128 and 1131 are again non-functional storage fields and can be used for any purpose, but generally have no application in the system base. Of the The priority level of an ongoing process is set in PRI field 1129 saved. An asynchronous interception bit is in the AB field 1130, while an asynchronous interception ring is in the ARN field 1132 the logical name J, P of the current process is im In the case of a monoprocessor structure, stored in the J, P field 1133.

An absolute table reference word according to FIG. 11k is present the digit BAR plus 60 in the system base 600 and is used during the initial system load to store the absolute addresses to prepare ISL in the initial system loader by the content of the boundary address register BAR is added to all absolute addresses in the ISL program. The absolute table reference address 1135 determines the storage location of the absolutization table (not shown). Your scope will be through the ATSZ field 1134 is determined.

The serial number word of the central unit is shown in FIG. 111 and consists of a 4-byte word which is in the storage location BAR plus 64 . In addition to the serial number of the central unit, it contains the serial number field 1136 of the central unit. FIG. 11 m shows the word designating the upper limit of the main memory, which is stored in the memory location BAR plus 68. This word 1139 gives the absolute address of the last accessible word in main memory. The word shown in FIG. 11n is located in the memory location BAR plus 72, which specifies the device terminal number (CN) 1140 for the initial loading of the ISL system and the hardware device channel number (CN) 1141.

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Type and sub-type of a device used in the computer system is indicated by a hardware device type word (Figure Ho) in the fields 1143 and 1144, while the RSU field 1142 for Software is reserved. This word can be found in the system base at BAR plus 76. A similar word from Figure 11p shows a similar format and contains the type and sub-type of device used when the system is initially loaded will. This word is at the position DAR plus 80.

the
If the restart button is pressed on a computer, a simulated V operation for a Seraaphor runs and comes to the preparation state. A reference address to this semaphore can be found at the position BAR plus 84 in the system base and is called the restart cell word. It has the format shown in FIG. 11q. It is similar to that of the system exception cell and contains the name G, D of a semaphore in the G field 1149 or B field 1150. The MBZ field 1148 must be "0". If there is more than one processor in the computer system, a word for multi-process expansion is provided in the system base 600 at the position BAR plus 88. This is shown in Figure 11r.

Example ^ for the use of the system base and the process control block

Figure 12 shows an embodiment of how the system base in conjunction with the process control block for addressing and access. to a user segment, a system segment or a segment with a queue of prepared processes is used. The main memory 1200 has one for hardware use reserved part 1203. A limit address register BAR 1202 separates the system base 1215 from that reserved for hardware Part 1.B03 of the main memory. The limit address register BAR 1202 is used to address variables in the system base 1215 uses the contents of the limit address register of the advance in four byte units of the desired size

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added in the system base. This address then points to the first byte of the size in the desired system base. In FIG. 12 points the limit address register 1202 to the J table word JTW. This word contains a pointer that points to the J table 1204. By indexing to the J number according to the figure you get a J table input 1216. This input is located a P-table reference address, which refers to the absolute Address in the P table 1205 indicates. Obtained by indexing to the P number (see Figure 5) within the P table 1205 one is the absolute address of process control block 1206. As already described, there are 1206 in process control block two address space words ASW 0 and ASW 1. The more significant bits of the segment table number field STN in the base register 1201 are used for exploited access to one of these two address words, in this case to the word ASW 1, which is a reference address to a Has segment table word arrangement STWA, the segment table word arrangement STWA 1208 leads. Together with the segment table number STN of the base register 1201, eight segment table words in the segment table word arrangement are accessed 1208. These segment table words point to one of the eight segment tables 1210. The segment table entry point STE from the Base 1201 is then used to execute one of the 256 entry points in the segment table 1210, where a segment descriptor is located. The latter is then used to access the user segment 1211.

To gain access to a system segment 1214 that is used for storage is used by semaphores, a G table word GTW is used in the system base 1215. Receives the address of the G table word by adding the shift of the G table word in the system base to the limit address register BAR 1202 (see FIG. 6). The G table keyword GTW contains a G table reference address a G table 1212. Using one available in the system G number and indexing in the G table gives you access to a G segment descriptor, which is used to address a system segment 1214 serves. Similarly, the system basis for

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access to a queue of preparation state Processes (Q / PR / RDY) 1213 used by one internal processor queue word ..IPQW, which refers to the Q / PR / RDY segment 1213.

G. control unit

Figures 13a to 13c show details of the control unit. Although it is shown separately from the central unit CPU, it is actually part of the central unit and consists of a memory control unit (CSU) 1301, a control memory interface adapter (CIA) 1302 with associated sub-units, a control memory loader (CSLJ 1303 and a control and loader unit (CLU) 1304. The memory controller 1301 receives microinstructions via the control and loader unit 1304 and the control memory interface adapter 1302 from the control memory loader 1304. Under normal operating conditions, the microprograms are loaded from an external source during the initiation process of the system and are v / grounded for permanent purposes However, the memory controller 1301 also has the ability to be reloaded and started in a manner which provides a variety of CPU operations Controller 1301 available: (a) Eigenrange mode; (b) emulation mode; (c) Self-domain and emulation mode at the same time; (d) Review mode. This capability arises because the microinstructions in the memory control unit are the source of micro-operations which are used to control the operation of all other functional units of the central processing unit, for example the emulator 1316, the arithmetic unit 1317, the instruction fetch unit IFU 1318, the address stick unit ACU 1319 and the data management unit DMU 1321 Furthermore, the previously described goneral register 1307, base register 1308, scientific register 1309, T register 1310, status register 1311, instruction counter IC 1312 and hardware control mask register 1313 are shown within the central unit 1306. ^v

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In the typical case, the memory control unit CSU 1301 is a 9K bipolar programmable κ * read-only memory PROM in an integrated Circuit technology with a read / write random access memory RAM. They usually have a read cycle time of 150 ns and a write cycle time of 450 ns. Any storage space of the control memory stores an 84 bit microinstruction word and each microinstruction word controls one central processing unit cycle. Each time a memory location is read in the memory controller 1301 its content is decoded by microinstruction decoders which generate a micro-operation control signal, each of which is a triggers a certain operation within the central unit. By grouping together positions within each microinstruction word one obtains control memory sequences which execute a certain central processing unit operation or an instruction. Since every command is triggered by the central unit, used certain bits within the opcode are used to determine the start sequence of the control store. By checking certain flip-flops, which are set or reset by command decoding sequences, it is the memory control unit possible to branch off into a special sequence if necessary.

The control store interface adapter 1302 is in information exchange with the memory controller 1301, the data management unit 1321, the address controller ACU 1319 and the Arithmetic unit 1317 in order to operate the storage control unit in this way 1333 in Figure 13d to be determined. The control store interface adapter 1302 also contains logic circuits for the modification, checking, error detection in control store addresses and for generating hardware addresses. The latter is generally used for developing a starting address of a Error sequence or used for the introductory sequence.

The data management unit 1321 forms the interface between Central processing unit 1306 and the main memory and / or the buffer memory according to Figure 1. The Datcnverwaltungseinheit has the task determine which unit is that of other unit

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Has required information and this information to ι at the correct time in the registers of the central unit. The data management unit also takes care of the masking for | certain write operations. The instruction fetch unit IFU 1318 forms interfaces with the data management unit 1321, the Address control unit 1319, the arithmetic unit 1317 and the memory control unit 1301 and is responsible for ensuring that the central processing unit is supplied with commands. The instruction fetch unit has each have the next instruction in their registers before the current instruction expires. To make this possible, the IFU 1318 is a 12-byte command register, which is usually more than contains a command. In addition, the IFU, controlled by the memory control unit CSU, requests information from the main memory before this information is actually needed. In this way, it continually updates its 12-byte command register. Commands are prefetched using normally unused j

i memory cycles. The IFU also decodes every Befel and infor- j mates other units over the length and format of the command. j

• The address control unit ACU 1319 is connected to the IFU, the ALU, the DMU and the CSU via the CIA. The ACU 1319 is responsible for j the entire address development in the central unit. All operations of the address controller including! the transmission to, from and within the control unit are - · by microinstructions of the memory control unit and by logical; Circuits causes. The normal cycle of the address controller depends on the type of addresses in the instruction, not the type of instructions. Depending on the address type, the address controller can perform different operations for each address within a command. The address control unit also contains an associative memory 1319a which is the base address

the latter use eight memory segments together with their segment numbers saves. Every time a memory is to be accessed, the segment number with the content of the Associative memory compared to see if the base address of the segment is already developed and stored.

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-58- f

If the base address is in the associative memory 1319a, so it is used for the absolute address development, which saves a considerable amount of time. Is the The base address is not in the associative memory 1319a, so it is developed by accessing the main memory tables. However after developing the base address of the segment, this is stored in the associative memory together with its segment number for Filed later reference. The arithmetic unit ALU 1317 works with the address control unit ACU, the command retrieval unit IFU, the data management unit DMU and the memory control unit CSU together. Its main task is to perform arithmetic Operations and data processing required by the central unit. The operations of the arithmetic unit are entirely dependent on microinstruction control signals from memory controller 1301. The arithmetic unit 1317 and the memory control unit 1301 is assigned a buffer LSU 1315, which is sometimes referred to as an internal storage unit. This buffer typically consists of one Read-only memory with 256 memory locations and 32 bits per memory location as well as selection and read / write logic for this Storage. The buffer memory 1315 is used to store control and maintenance information from the central unit used. In addition, it contains workplaces, which are mainly used to temporarily store operands and partial results serve during data processing. Furthermore, the arithmetic unit 1317 is assigned an auxiliary memory 1317a, which in the usual case 64 flip-flops for storing different states of the computer system.

The central unit also has a clock unit 1320, which practically consists of two clock systems in one unit. The "" first clock system generates the clock signals for controlling the interface adapter 1302, while the second clock system generates the clock pulses for the operations of the functional

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units within the central unit.

The format of the control memory word 1325 is reproduced in FIG. 13c. This is an 84-bit word and is divided into the following six main fields:

la '. Subsequent type field 1326 (3 bits)

b. Branch and / or microinstruction field 1327 (23 bits)

c. Constants Generation and Determination 1328 (14 bits)

d. Data for busbar 1329 (8 bits)

e. Microinstructions 33Ο (32 bits

f. test 1331 (4 bits)

The 3-bit E field of the control memory word 1325 is used as the subsequent control field. There are typically seven different control sequences and one is reserved for the current computing system. Referring to block 1335 in Figure 13b, if the E field is 0, 1, or 2, then branch field A. B, C, D ₇ and L of microinstructions 1325 is used to generate the next address. The first six bits of the KS register 1337 are used together with the B field, a C test results, from this a D test and the L field supplies the next address of the next microinstruction, which is then entered in the address register KS 1337 is entered. If the E field is set to binary 4 (see block 1335), the next selected address is taken from the interrupt return register KA 1339. The address in the ΚΑ register is the one generated by the logic circuit to generate the next address when a hardware interrupt occurs. If the E field is set to binary 5, a branch operation is used to cause an auxiliary return operation from a microprogram subroutine. When this occurs, the contents of return registers KR 134G are used as the next control memory address. Return register 1346 is loaded by issuing a control store instruction containing the current control store address.

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in the KS register 1337 plus 1 from the incremental switch 13 38 into the KR register 1346 transferred. One way for a one-bone insert routine is given via a KT return branch register 1347. Every time the KA register 1346 is loaded the old contents of this register are transferred to the KT register 1347 and every time a microprogram return command is called, the content of the KT register is entered into the KR register. One possibility for an insert subroutine in the third level is through the KU register 1340 and in the fourth level through the KV return branch register Shown in 1349. If the E field of the control store word is binary 6, the next addressed control store word is equal to the current address in KS register 1337 plus 1 in the incremental switch or incrementor 1338. If the E field is in binary, the memory control unit 1301 changes to the checking mode and the next address is equal to the current address plus

In addition to sequencing branches to the next control store address of block 1335, hardware-generated sequencing is shown in block 1336 of Figure 13b. Blocks 1335 and 1336 are actually hardware registers and are constructed to accommodate the various forms of microinstruction can have. The hardware-determined branches represent overriding states, such as errors , initiation, control memory scanning, etc., which suppress the E field and forcibly enter a fixed address in the control memory address register KS1337. The branching occurs in that a line interruption takes place for one clock period and the address which would have been er.zevsgt under the control of the E field is loaded into the KA interruption return register 1339. A hardware controlled address is entered into the control store address register. Certain interrupts generated by hardware or firmware have priority when the interrupt blocking flip-flop is set, which is the

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Prevents performing additional interruptions in their class until the interrupting state is resolved. A firmware micro-operation exists to control the resetting of the interrupt-blocking flip-flop for those sequences which are under the influence of firmware. These sequences automatically reset the blocking flip-flop at the end of the sequence. The states listed below according to their priority exist in this category .

(a) loading the control memory;

(b) Scan the control memory

(c) hardware failure?

(d) software failure

The remaining hardware states do not set the interrupt _{blocking flip-flop /} but cause immediate action when they are generated. The states listed below according to their priority exist in this category:

(a) introduction;

(b) soft release;

(c) Entry into the maintenance console j

(d) entry into the maintenance console;

(e) Hardware output.

An initiation signal causes the memory controller 1301 branches to address binary 0, errors that can be reset by hardware are cleared and a control store load operation followed by a control store scan sequence carried out under hardware supervision will. In addition, the system initiation is carried out. A soft enable signal causes the CSU 1301 to branch off to the binary 0 address, clears the errors that can be reset by hardware and resets the interrupt blocking flip-flop. A signal for entry into the maintenance group causes the storage control unit branches to the addresses given by the switches on the information board. A signal to enter the maintenance channel lets the memory control unit branch off to an address which is generated via the maintenance channel. The address will be from

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the maintenance busbar QMD 1344, which is part of the maintenance channel is. An Ilardware output signal leaves the memory control unit branch off to binary address 2. This sequence is used as a maintenance facility. At the end of the episode is through surrender of an E-field branch instruction initiated a return and the E field is set to binary 4.

A control store load signal causes the store control unit to branch off to the binary 0 address. It also switches the CSU read cycle Flip-flop and the system clock generator 1320 and transfers the memory control unit to the loading state. In this state it can Memory controller can be loaded from the control memory loader CSL 1303, the input / output controller IOC 1305, the main memory 102. Or the maintenance panel 1355. If a load is carried out from the CSL loader, this will cause automatic scanning at the end of loading. If, on the other hand, loading is carried out from a different medium, a scan can be performed either by generating a micro-op signal or by setting the sampling switch on the MP take place. A control store scan signal causes the store control unit to branch off to the binary 0 address. For the duration of the episode is subject to the scanning of the control by hardware. During the scan, the system clock 1320 is turned off and consequently no commands or checks are performed. At the end of the scan sequence, the hardware transfers the contents of the interrupt return register KA into the address register KS, the system clock is switched on again. And the control returns to Firmware back.

A hardware error signal causes a branch to address binary 4. In normal process mode, an activates in any Functional unit of the central unit detected hardware errors a hardware error line. The generated control storage sequence checks the system status with regard to the action to be taken. In the diagnostic mode, the hardware can detect Error states for micro-diagnosis recognizable. She controls

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the actions to be taken. A software error signal, on the other hand lets the control store branch off to address binary 1. This address is the beginning of a software bug reporting sequence which is under microprogram control.

In FIG. 13c, the E field 1326 is a 3-bit field for the branch code. The branch and / or microinstruction field 1327 consists of the A, B, C, D and L fields (see also block 1335 in FIG. 13b), the A field being the upper six bits of the next address and the B field being the middle four bits of the next address of the hash field at the 64-way branch, the C field a 6-bit test field for one of 64 tests, the D field a further 6-bit test field for one of 64 tests and the L -FeId is the least significant bit. The K field 1328 is a 14-bit field, of which six bits are used for a constant field, four bits for a constant or control field and four bits for a control field for a constant. The field 1329 for data transfer to S amme 1 r, chi one consists of the QA field with 4 bits to control the flow of information to the QA part of the QMB busbar 1344, while the QB field has four bits to control the information transfer to the QB- Contains part of the 1344 QMB busbar. The F-Field 1330 is a 32-bit field and is encoded to generate micro-operation sub-commands. The B field 1331 consists of four bits reserved for test purposes.

In operation, the microinstruction words are stored in a control storage arrangement 1333 saved. During a cycle of operation, this control store arrangement is identified by the contents of the KS address register 1337 addressed. This places the content of the addressed memory location in the group of locking registers 1357 entered. Portions of the contents of these registers are stored in the storage registers within each of the functional units of the central processing unit transfer. Each functional unit contains logic decoding circuitry for generating the required by the control store word defined subcommands under the control of the system clock. In general, decoding is used

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carried out within each functional unit and not centrally, so that the decoding time is reduced to a minimum and the number of lines for the transmission of command signals is reduced. In addition to semi avoids by decoding within \ each unit timing problems which may arise from different, borrowed cable delay times. Finally need ¹ those signals not to the control memory interface adapter 1302 returned, which are indicative of certain conditions within the functional unit and for the production of certain sub-instruction-signals are required. A typical decoder 1359 receives various fields of microinstruction words according to FIG. 13b and generates microinstruction signals a, b, c, d, ... g, r. A typical microinstruction decoder 1359 receives instructions from a microinstruction word. The field of the microinstruction word is decoded and sets a plurality of parts s, t, u, .... y, ζ to the potential "1". A matrix with predetermined control lines is coupled to the s to z lines at points ^oa _l ß _{i (} j ¹ '* ^ ·' - CJ . If the field

of a microinstruction is decoded, one of the lines s goes to ζ to high potential. Since the connection points marked in the drawing by dots and Greek letters are Crossing lines represent a line coupling, each will run along a horizontal line. spreading .. signal at those points where a coupling point is indicated, merge onto one of the vertical lines a to r. Any of the vertical Lines can be routed as inputs to one of the AND gates 1360 1365. Other input signals can also be sent the AND gates 1360 to 1365 are carried, including a clock signal t from the central clock '. Consequently, each when the clock signal assumes the value "1", those gates are switched through, all of whose inputs have a positive input signal to have. These gates supply micro-instruction signals to predetermined functional units within the central unit. For example when an instruction 1341 is decoded from read interlock register 1357 and a horizontal line is at "1", the vertical control lines a, b, c, and q are also positive and gates 1316, 1361, 1362 and 1364 are turned on when the

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Clock signal switched through one after the other. Consequently, the combinations in which the vertical control lines with the horizontal control line are coupled at different points / marked by Greek letters, a permanent one Switching matrix for the supply of micro-command signals to the central unit, namely for the control of the functional units within the central unit by micro-commands of the control memory arrangement 1333. Thus, permanent but changeable firmware can be built into the system by only the sequence of microinstructions is specified, which is required as a capability of the computer system.

Under normal conditions, data will be in the control memory array 1333 via a write data register of the central unit, which is also known as Internal Register YO 1343

entered,
is known _f A control flip-flop determines whether the upper or lower half of the memory array is to be written to. Data from the control and loading unit CLU 1304 arrive at the adapter CIA or the storage control unit CSU via the maintenance busbar QMB 1344 and are temporarily stored in the internal storage register YO 1343 before they are entered into the control storage arrangement 1333 ". The internal register 1343 is both The multiplexer KQM 1345 can be controlled either from the maintenance desk 1355 or by micro-diagnostic operations and provides a retrieval path from the registers connected to it. A comparison register KP 1350 is primarily used for maintenance purposes, together with a comparison logic 1352 and a decoding logic 1351.

H. Arbiter firmware for controlling processes The arbiter is a firmware / hardware unit, the main purpose of which is to manage the various process queues and to switch between the processes, and also includes the updating of the process queues, the process control blocks,

dom of the current process word in the system base and register of a

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new process. It also delivers messages to a process that is waiting on a semaphore (after a V operation, a simulated V operation for input / output control or for an exception handler). It also arranges messages in Queues at a semaphore after a P operation that has released a message link when a process is on a connection release semaphore waiting for its message to be passed on. The dispatcher unit also calls for the control input a process running in self-domain mode or after a dispute between two processes if the process continues and is in self-range mode, the firmware for self-range commands. He also calls firmware Decor extension to for

(a) a temporary call while control is being withdrawn a process that takes place in that decor extension;

(b) a temporary call while taking control of a process running in that decor extension;

(c) a specific call at the end of the transfer of control of a process which is running in the decor extension; and

(d) a certain call after a conflict when the current process is going on and in this decor extension mode expires.

The arbiter also idles the system when there is no running process. There are different ways to get to or leave the allocator:

(1) the initiation procedure SIP results in an entry point as the last step;

(2) the start and stop command leads to access to the dispatcher;

(3) P and V operations give access to the arbiter. The P operation picks up a message from a semaphore _/ and if there is no message the process goes to wait.

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In short, the arbiter is the main mechanism by which the Manages processes and thus also the process control blocks by having decides which process to run, and then the required one Initiates action, for example a removal of control for the currently running process. This means that it is in the process control block all information that is contained in hardware registers, buffers and the like for the current process, enrolls. It also leads to the transfer of control to the new process, i.e. it writes from the process control block to the different ones Hardware registers, buffers and the like. All information that is required for the implementation of the new process are.

A representation of the functions carried out by the allocator results from the flow charts according to FIGS. 14a to 14i. For example Block 1402 in Figure 14a is a representation of the function performed by an arbiter, with a microprogram word is supplied by the memory control unit and, after decoding in the decoder 1359, the corresponding parts of the central processing unit controls an appropriate sequence of microinstruction signals 1360, 1361, etc. to extract the internal process queue word IPQW from the Remove the system base in the storage subsystem 102 and transfer it to the buffer storage 1315. The dispatcher calls at the same time the GO segment descriptor (see FIG. 12) from that T table to which the G table word GTW in the system base indicates. Bits 16 through 31 of the IPQW contain a 16-bit positive integer indicating the displacement from the base of the GO segment to the head (first byte) of the queue Q / PR / RDY represents prepared processes. Are bits 16 through 31 of the IPQW word equals 0, the queue is considered empty. This means that there is currently no process in the queue stands. The next to be decided in decision block 1405. The question is whether a process is currently in progress. To this end, it is established whether the vacancy indicator is set or not. Is it set and, as has just been stated, is no further process

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in the queue, the system goes into the idle state 1406 about. However, if a process is in progress and is not a further process in the wait state, the current process takes its 1407 instruction on.

At decision block 1403 of the flow chart (Figure 14a), the Head of the queue indicated by the IPQW word in the GO segment transferred to the buffer if a positive whole-part value in the reference address area of the IPQW, i.e. in the Bits 16-31 is present. In order to avoid repetitions, the intermediate functions of the allocator in connection with the Control unit and the central unit are omitted. It should be noted, however, that such intermediate functions typically exist are. Up to this point it has been determined that some process is queued. Before taking further action a "determination is necessary as to whether a process is currently running in the central unit. This is done by means of the Determination blocks "1410 done. If no process is currently in progress, the head of the queue 1412 is taken into service. However, if a process is in progress, the arbiter must determine whether the current process or the head of the queue has priority. For this purpose, the priority byte of the current process CJP is used in. running process word of the system base process control block 400 Retrieved 1413. A decision is made at 1414 whether the the current process CJP is of lower priority than the new process NJP at the top of the queue. Has the current one If the process does not have a lower priority than the new one, the current process retains its control authority over the central unit and the elimination indicator is reset at 1415. This is always 0, unless one or more new processes since the beginning of the last command execution for the old process in the queues were queued and thus a conflict possibility has been created. Only in this case is the elimination indicator set to "1". Marriage the ongoing process can go on and carry out further commands, it is determined

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whether it runs in decor extension mode 1415. Is that the case, so the next command is in emulation mode, i.e. in the decor extension executed. If, on the other hand, it does not run in the decor extension mode, the next command is executed in Eigenrange mode. In decision block 1414, the new process did a higher priority than the old one at the head of the queue, bo the control authorization is removed from the current process and transferred to the new process. For this purpose, a firmware priority subroutine PRIQ 1418 effects the classification of the current process CJP into the queue by adding the LIFO priority number and the bv priority number first set off the old process under the control of the firmware subroutine RLLO 1419. The RLLO subroutine causes the -in the general registers, basic registers, scientific registers, T-registers, status registers and information contained in the command counter of the old process back to the appropriate memory area of the process control block in the main memory and causes the processing time calculation to be updated. In addition, the DEXT number of the process main word PMWO is written to the process control block 400 at 1420.

The new process NJP is now prepared for the takeover of control. The limit address register BAR is retrieved at 1422 and the current process word RPW is taken from the address BAR plus the system base is retrieved at 1423. The name of the new process NJP is first written into the current process word RPW and since this name is in the process connection PL of the queue Q / PR / RDY, the name in the process connection PL is in the block 14 24 entered in the current process word. This means that the new process from the queue becomes the current process and is able to * control the central unit. It no longer waits in the Q / PR / RDY queue and must therefore get out of it Queue can be removed by removing its name at position 14 from the process connection PL of this queue will. As soon as this is done, the queue is updated by a firmware subroutine UQLK 'at 1425a. The JP Nununor of the process that has just been removed from the system

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entered into a process connection in the Q / PR / RDY queue because it no longer controls the system but has to wait for it at 1426. At this point in time, the control of the central unit is transferred to the new process and the old process is placed in the queue, because there the new process is under control over the central unit, the vacancy indicator is at ¹¹ O "at 1427. If no running process were to control the central processing unit, vacancy 6.ger would be 1. The assignment of the processor has now been completed, the new process is now working with the central processing unit and the old process is in the queue, but the new one is still there Process not yet able to run because the hardware of the central processing unit 1306 in FIG Process must first be supplied with control information.

For this purpose, the firmware subroutine 1430 controls the central processing unit and The PMW 3 first calls the process control block (FIG. 4) into the buffer memory 1315 and then the process main word 0. The MBZ field of PMW 0 is checked at 1433 and if it is not equal to binary 0, a PCB exception signal appears, but it is the PMW 0's MBZ field equals zero, so PMW 1 becomes 1 at 1434 retrieved. The MBZ field of PMW 1 is checked again to determine whether it is equal to 0 or not. If it is not equal to 0, an output signal indicating an illegal control block appears. Otherwise the allocator goes to C. The address space word ASW 0 is taken from the corresponding memory in the PCB retrieved and the segment table word size STWSZ checked at 1437, to see if it is less than 7 or not. If it is greater than 7, a PCB exception signal is generated. Is it smaller or equal to 7, the ASW 1 is removed from the PCB at 1438 and its STWSZ-Fe ^ d is checked at 1439 to determine whether

- Π - ^f

it is less than or equal to 8 or not. If this field is greater than 8, a PCB exception signal appears. If STWSZ is equal to or less than 8, the exception word EXW is retrieved at 1440 and checks its MBZ field to see if it equals 0

en or not. If it is equal to 0, an impermissible PCB is created indicating exception signal. If it is equal to 0, the stack word becomes SKW retrieved at 1442 and checked its MBZ field at 1443. If the MBZ field is not 0, a PCB exception design appears; otherwise the command counter word ICW is fetched from the PCB and entered in the command counter IC and its I-linweisfeld TAG at 1445 checks whether it is equal to 0 or not. If it is not equal to 0, a signal appears for an impermissible one PCB .. "Otherwise the MBZ field (bits 0-31) is called up at 1446 and checked at 1447 whether it is equal to 0 or not. If it is not equal to 0, a PCB exception signal appears; however, if it is 0, the stack base words become SBW 0, 1 and 2 retrieved at 1448. The contents of the eight base registers in the base register security area of the PCB are retrieved at 1449 and stored in the base registers 1308 of the system. Then the contents of the 16 general registers are taken from the Unloaded general register safe area of the PCB at 1450 and entered into the general registers of the central unit at 13Q7. Before the scientific register is called up, the PMW 0 capability byte is checked to determine whether the scientific Mode is used or not (1451). Will the scientific Mode used then the contents of the scientific Register retrieved from the appropriate safe zone of the PCB and stored at 1452. The firmware then checks the capability byte of PMW 0 to determine if the calculation mode is being applied (1453). If this is the case, i.e. if the capability byte is binary 1, there is a calculation word in the PCB and the calculation word RTA for the preparation time is updated .. The firmware then checks whether the DEXT number is 0 (1454). This is not the case, so she states that. the machine * is working in emulation mode can, i.e. the decor extension option is used. Demented

70 * 9810/0933 "

Speaking, the DEXT number of PMW 1 is checked at 1455, to determine / whether it is larger or smaller than the DETSZ field of the process noun 3. If it is larger, it appears in 1456 a PCB exception. If the DEXT number is smaller than the DETSZ field but not equal to 0, then the machine runs in one permissible emulation mode and goes to F. In decision block 1455, if the DEXT field is 0, then the Self-range mode executed and the machine retrieves the segment table words STW at 1457. The remaining time word RTO of the process control block is retrieved at 1458 and the process timer is loaded for the amount of time the current process is in Working condition.

Up to this point, either (a) a new process NJP has the Control of the central processing unit taken over if an old process CJP 'was in the machine and the new process had a higher priority than the old one has, or (b) there was no old process in the central processing unit and the head process of the queue was processed. Under condition (a), the old; Process removed from the current process word and in a process connection PL in the queue entered while the new process was inserted into the current process word RPW in the process connection Q / PR / RDY and thus the states of the two processes have been switched. The new process became an ongoing process and was given tax authority via the central unit, while the old process has given up this control authorization. Then access to the PCB takes place of the new process and the information on how to carry out the new process was stored in the buffer or in the register arrangement of the address control unit.

According to state (b), if no old process was controlling the central processing unit, the head process of the queue became the prepared one Processes are taken over for processing and the new process becomes the current process, because the dispatcher has this from the process connection PL at the head of the queue and transferred it to the RPW word. This resulted in an empty process

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connection PL in the queue that had to be removed.

At decision block 1461, the firmware determines whether a running Process had control authority over the central unit and if there was a free process connection FPLS, an access was made to do this and it was queued and the current process was enrolled. However, if not a running process controlled the central unit, the PMW 0 of the new process is updated at 1460 and again checked at 1463 whether a running process in the machine. If this is not the case, the process connection of the new process, which is in the queue was and now the machine controls, at 1466 taken out of the Q / PR / RDY queue and becomes one

FLSP
ConnectionCrcLgabesemaphor / and now queued in the free process connection queue (805 in FIG. 9). It becomes part of the free process connection queue 1466a. The contents of the limit address register BAR are retrieved at 1464 ^ and the current process word RPW of the new process, which is now the current process, is stored at BAR plus 56 of the system base and updated by the fact that the identification of the new process is updated at 1465 in the current process word RPW is enrolled. The vacancy indicator is set to 0 if there was no running process. The elimination indicator is then set to 0 at 1467 and the segment associator AS 132 in FIG. 1, which is a typical content-addressable memory, is deleted at 1471. The process then enters process mode at 1470. This indicates that exception signals are being processed by the process running in the processor and not by the operating system. The firmware then advances to CAB 1480 and an asynchronous catch bit AB is checked at 1481 to see if it is a binary 1 or not. If the AB bit is 1, a check is made at 1482 as to whether the process ring number PRN is greater than or equal to the asynchronous ring number ARN. The interception bit AB and the interception ring number ARN are in the priority byte of the PCB of each process and have meaning if

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the process is in the processing state. They are derived from the RPW at BRA plus 56 of the system base and deferred because the next step 1484 leads to an asynchronous trap routine that takes into account those conditions which cause the asynchronous trap bit or asynchronous ring number to be entered in the first digit will. If these bits were not reset, the next firmware run would indicate that something went wrong when in fact nothing is wrong. As a result, the asynchronous trap 1584 would always occur and never be carried out. In the ent. Divorce blocks 1481 and 1482 would if the AB bit was not is set, or the AB bit is set and the process ring numbers is not greater than the asynchronous ring number, the firmware will pass over to determine which mode the processor will run in would, namely in normal mode or in emulation mode. As a result, the DEXT number is checked to see whether it is set to 0 and if not, normal mode of the machine starts at 1487. However, if the DEXT number is not equal to 0, then emulation mode is initiated at 1486.

Detailed description of the invention

The hardware / firmware system knows two basic types of data records, which are processed in group operations will. These two types of data records are the virtual memory data records according to FIG. 15A and the database data records according to Figure 15B. The virtual memory records are generally internal to operating system procedures used, whereby data records can be addressed by segmented addresses. Database records are saved in generally used by user agents, which identify their records by the number of the area, the page and the Address line. The area relates to a user file, the page to a subdivision within this file

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and the line number on a specific record within that page of the file.

According to FIG. 15A, the virtual memory data record consists of the following fields: The type field 1501 provides a description the type of data set and is derived from the data set descriptor of this data set. This will be later described in more detail. The D toggle field 1502 of the virtual memory data set describes the state of the data set. The data record can be in the following states: Active, this means that the data record is currently valid Contains data; and logically deleted, this means that the data record no longer contains any valid data, but still contains it Keeps storage space occupied. The length field 1503 describes the actual number of bytes in the record. The record body 1504 contains the actual data of the data set. The pointer follow-up field 1505 forms part of the record body and can point to the next, previous, first and last record or on the user record, these records being part of a group in which they are used as user or member records are present.

The second major type of record that is generated by the hardware / Firmware system is identifiable through database records formed according to Figure 15B. The type field 1510 again describes the type of data record and will be used in the following , descriptively derived from the dataset descriptor of the dataset. The length field 1511 describes the length of the data record in bytes. Record body 1512 contains the actual data of the record. The reference address sequence 1513 contains the reference addresses to the next, previous « etc. Record of the group. There is also a D toggle button 1604 for each record that is recorded separately and is described below.

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FIGS. 15C and 15D also describe the format of the pointer sequence of a data record corresponding to the fields 1505 and 1513 in Figures 15A and 15B. The hardware / firmware system recognizes two different formats of reference address sequences, one of which is shown in Figure 15C and represents the recognized sequence for member records and from the other of which is shown for the case of a user data record in FIG. 15D. Regarding the member records (Figure 15C), the Next Pointer field 1520 contains the address of the next member within the group. That Preceding pointer field 1521 contains the address of the preceding member within the present group. That User Notice Address field 1524 contains the address of the user in the group. In terms of user records it is the format of the reference address sequence recognized by the hardware / firmware shown in Figure 15D. The first reference address field 1532 contains the address of the first member record of the group. The last pointer field 1533 contains the address of the last member record within the group.

Each of these described reference addresses (next, previous, etc.) is optional. However, only the following combinations are legal for a given group:

Case 1. No first, last, next or preceding reference addresses for user or member records. (The member records have ¹ , user reference addresses)

Case 2. The user record has a first reference address and the member records have a next reference address. (The member records. * - ^c may or may not have user reference addresses)

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Case 3. The user record has first and last hint addresses and the member records have next reference addresses. (The member records may or may not have user hint addresses)

Case 4. The user data record has first and last reference addresses and the member records have next and previous pointing addresses. (The member records can be used as user reference addresses show or not)

Another characteristic of the hardware / firmware system is its ability to have four different classes or Recognize formats of reference addresses. These classes are designated as follows within a data record: Class 0, these are only used for virtual memory records; Class 1, these are also only used for virtual memory records used; Class 2, these are only used for data records and Class 3, these are only used for database records used.

All four pointer classes have a common meaning with regard to their first two bits. The first bit, the EOS bit, is an indicator bit for the end of a group. If this bit has the value ¹¹ I ", the reference address refers to a user data record by definition. The second bit, the NINS bit, is an indicator bit that the data record has not been inserted.

The format of the pointer from class 0 is shown in Figure 15E. The EOS bit 1540 and the NINS bit 1541 occupy the first and second bit position. The SRA field 1542 represents a 14-bit offset, which results in a shift within a specified segment is displayed, which is in this

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The data record stored in the segment. The SRA field, that is obtained from the reference addresses of class O is always associated with a segment number, which is generally from the Base register is obtained, which is used for addressing data records via reference addresses of class 0.

The Class 1 pointer is shown in Figure 15F. The EOS bit 1550 and the NINS bit 1551 correspond to the standard definition. The SEG, SRA 1552 field is made up of the segmented Standard address together with SEG and SRA in the manner previously defined. These reference addresses are used for direct addressing of a data record is used, the segment number being obtained directly from the reference address.

With regard to the reference addresses of classes 2 and 3, which are used in connection with database data records, makes the firmware / hardware system uses a convention that for each base register of the system described above (see Figure 2, 202) is assigned an index register. The general registers 8 to 15, 201 correspond to the index registers 0 to 7. The index register number IXR. is to the basic register number BR. customized. For example, contains for the base register BR3 the index register IXR3 (GRIl) a reference address to an area-page-line number (see Figure 15H), whose current SEG, SRA address is contained in the base register BR3. The user is thus able to either view his or her data set via a base register with the SEG, SRA address or via a database reference address, as it is in the index register of the area-page-line format is to be addressed.

The hardware / firmware commands that act on the database data records have the ability to assign areas, pages, and line references automatically convert to SEG, SRA addresses. Therefore, all of the actual memory references by the Database commands use the standard hardware mechanism that supports the

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Memory with segment and SRA number addressed, with the conversion the area-page-line contained in an index register is done automatically by the hardware if necessary.

There is a temporary 1: 1 correspondence between a page in a user file (area) and a segment like it identified by the hardware / firmware. The hardware / firmware therefore converts via a method to be described below Page descriptor mechanism converts any given page number into a segment number.

The format of the class 2 pointer is shown in Figure 15G. Fields 1560 and 1561 indicate the EOS bit and the NINS bit on. The page number is contained in field 1562. The line number is stored in field 1563 and represents the Number of a data record within a page in an area. A reference address to the complete area-page line number is obtained by using data records of class 2, with the area number from the index register which is referred to by the database command.

The formats of the class 3 pointing addresses are shown in Figure 15H. Fields 1570 and 1571 indicate the EOS bit and the NINS bit on. The area number is stored in field 1572. This refers to the user file number. The page number 1573 and the line number 1574 address a specific data record within the user file.

According to FIG. 16A, the page of a database is shown which forms part of a user file (area), such as it is identified by the hardware / firmware system. the Database pages contain the database data records as previously described with reference to FIG. 15B. As mentioned earlier, there are

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a 1: 1 correspondence between a database page and a segment at the point in time when the database page is stored in main memory.

The page header 1601 contains certain information about the page in which it is contained. For example, it can describe the length of the page in bytes and also give an indication of the number of data records (lines) within the page. It can also contain information in the form of a write bit which was set when the page was written when it was still contained in the main memory. Following the header, the row offset field 1602 forms the next body of the database page. This is an array of 16-bit elements which match on a 1: 1 basis valid line numbers for the page. For each element of the line offset field there is a D toggle field 1604 of 2 bits and an offset field 1603 of 14 bits. The D toggle field describes the status of the data record, for example, as inactive, logically deleted, physically deleted or active. The offset field represents a 14-bit pointer to the data record, which corresponds to a relative shift with respect to the beginning of the page. It can be seen that the hardware is able to address a database record in this page by using the offset, the offset being concatenated with the segment number belonging to this page. The procedure for obtaining the appropriate segment number is described below. The remaining part of the database page is made up of the actual database data records, e.g. data records 1610 and 1612. These data sets of the page (segment) can be arranged in any part and are not necessarily in the same order as in the corresponding position line offset field. "If the D toggle field describes the data record status as inactive or physically deleted , the offset field is set to 0 and the data record does not exist.

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The actual database page is addressed by a page descriptor according to FIG. 16B. The segment number 1625 of the page descriptor contains the segment number corresponding to the page number after it is loaded into main memory. Area number 1622 contains the area number (file) of this page. The page number 1624 represents the actual page number. The indicator 1626 for the last page has the value "1" with regard to the highest page number for a given area. The shift count 1623 contains the number of bits of the page number. The hardware / firmware system identifies a varying length of the page number by using the formats of the Area Pages * Line Pointer. The next descriptor 1620 is used to indicate the next page descriptor within a chain of page descriptors. The previous descriptor 1621 refers to the previous descriptor within a chain of page descriptors. The use of these page descriptor chains is described below.

The page descriptor chain is formed by a hardware / firmware mechanism that is used to indicate which pages within files are currently stored in the main memory of the computer system. For each page present in the memory, a page descriptor is stored in a chain that can be identified by a single system and is pointed to by the integrated access control reference address according to FIG. 16C. The integrated access control pointer represents a one-word extension with respect to the system basis described above. The integrated access control pointer is stored under the address BAR plus 92, which address is one word after the end of the system basis. The format of the integrated access control reference address IAC contains an MBZ field 1630, a G number 1631 and a shift field 1632. The G number is a number of a G segment as described above. The shift field indicates a shift within this G-segment , whereby

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the beginning of the page descriptor ring is displayed. The page descriptors of all contained in a main memory Pages are then linked together in the traditional chain format. The Next Descriptor and Previous Descriptor fields form the connection.

FIG. 17 shows the hardware / firmware flow diagram for storing a database page in main memory. the Firmware is used to take a pointer for the area-page-line number and first determine whether the page is in main memory and, secondly, to form the page descriptor for this page, if the page than is found in main memory. The firmware starts with step 1701.

The first firmware action occurs in step 1702 where an IAC pointer is from main memory in the location BAR plus 92 is called. The IAC reference address is contained in the system base according to FIG. As a result of this Memory access exception 1703 may occur when fetching memory. Examples of a memory access exception are given, when the size to get is out of physical memory or when a memory read error occurs. The next step 1704 carried out by the firmware checks the MBZ field for the value zero. If the field has the value Does not have zero, a system check 1705 occurs. When a system check occurs, the system goes into a Diagnostic status over.

If the MBZ field has the value zero, the step 1706 executed next. The G number of the IAC field becomes transferred to the temporary register G. - The shift field is transferred to the temporary register D. The postponement is also transferred in a buffer to a storage location called the first pointer. Of the Step 1707 is performed next. The retrieval of the

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Main memory takes place at address G, D for the purpose of retrieval a page descriptor (see Figure 16B). This retrieval takes place in accordance with the G, D addressing described above. A G, D access exception 1708 can result this memory fetch may occur. Next up is the firmware perform step 1709. The area number and page number of the area-page-line number are determined by the firmware subroutine checked and compared with the area number field 1622 and the page number field 1624 of the page descriptor for Match compared. If the area and page numbers match, then step 1720 is performed, in which the firmware routine ends and the page descriptor just fetched from main memory is stored in the buffer is loaded.

If the area or page number of the current page descriptor does not match the area and page number of the area-page-line reference address currently being checked, so step 1711 is carried out. The next descriptor field 1620 of the page descriptor for the current page is used against the contents of the temporary buffer space, the contains the first reference address. If these two values are not equal to each other, then step 1713 executed, in which the temporary register D is loaded with the next descriptor field of the current page descriptor. The firmware branches to step 1713 after step 1707, in which the new descriptor is replaced by the next descriptor addressed page descriptor is retrieved and is subsequently checked.

If one goes back to step 1711, then in the event that the next descriptor corresponds to the content of the first reference address in the temporary buffer location, it is indicated that the entire ring of page descriptors, which describes all the pages in the memory, is now fetched has been,

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without the area page searched for by the firmware being found. In this case, a page exception occurs in step 1712 indicating that the page sought does not exist in main memory. In response to this exception, a suitable software action can occur, which may bring the searched page into main memory.

According to FIG. 18, a block diagram of the hardware is shown which is required to store a database page in main memory to find. The mechanism shown is activated by setting the page finder flip-flop 1851, which is arranged in the auxiliary memory 1317A of the arithmetic unit 1317 of the central unit 104. Before putting the page on Finding flip-flops 1851 becomes the area page number whose Page descriptor is to be loaded into the area-page-register Loaded in 1852. The contents of the area-page register are then used to determine whether the appropriate area-page

descriptor has been found.

Setting the page finder flip-flop 1851 to the "1" state prepares the AND gate 1854, which then allows the contents of the limit address register 1853 to be transferred to the adder 1856. The other input of the adder is formed by a constant with the value 92, which constant is stored in the hardware register 1885. The adder 1856 is arranged in the arithmetic unit 1317 of the central unit 104. The output of adder 1856 is connected to an AND gate 1857. The AND gate 1857 is prepared by the page finder flip-flop 1851. When the AND gate 1857 is prepared, the contents of the adder 1856 can be transferred to the memory address register 1858 of the memory system 1859. In this way, an address formed from the limit address register content plus 92 - is transferred to the memory address register 1858. As described above, this address forms the address of the integrated

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Access control pointer which can be found in the system base is. The integrated access control reference address IAC can be read from the storage system 1859. The output signal of the page finder flip-flop. 1851 is through the inverting amplifier 1886 inverted to the value "0", which in turn is used to set the read / write flip-flop 1887 of the memory system is used and "sets this flip-flop to the value" 0 " (Memory read operation). Thus, after the memory system detects that the memory address register 1858 has been loaded, a memory read operation can be initiated. Memory access exceptions may occur as a result of the memory read operation. As previously described, the memory access exceptions occur the activation of the exception handling mechanism. The exception handling mechanism is set by setting the memory access exception flip-flops 1860 activated, if any Exceptions are detected by the storage system. When the memory operation proceeds normally, the memory operation completion flip-flop becomes 1861 set to the value "1" and the content of the reference address IAC read out from the memory and transferred to memory data register 1862. The store operation completion flip-flop 1861 here indicates the Transmission of the contents of the memory data register via the AND gate 1863 free. This content, which is the reference address IAC represents, has the format according to Figure 16c.

The MBZ field 1630 of the reference address IAC is sent to a comparator 1865, which is contained in the arithmetic unit 1317. The comparator 1865 compares the MBZ field with the contents of a register 1864 which ^{stores the value 11} O ". If there is no comparison, the system test flip-flop 1866 is set to the value" 1 " State of equality, the equality signal enables the transmission of the G number ... ^l -1631 and the shift field 1632 of the reference address IAC via the AND gate 1867 to the G register 1873 and the D register 1874. The logic circuits for the transfer to the D register 1874 is described below.

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The setting of the page finder flip-flop 1851 in turn causes a first time flip-flop 1869 to be set. This flip-flop is set to the value "1" to indicate that the D register 1874 has been loaded for the first time. The output of the time flip-flop 1869 is connected to the AND gate 1871 together with the output of the AND gate 1867, the AND gate 1867 containing the D shift field of the reference address IAC, via the AND gate 1871 the Shift field of the reference address IAC passed on to an OR gate 1872, which in turn transfers the shift field to the D register 1874. The output of the time flip-flop 1869 is given together with the output of the AND gate 1867 to the AND gate 1868, the first pointer address register 1870 is thus loaded with the initial shift value obtained from the pointer address via the AND gate 1868 will. The use of the first pointer register 1870 is described below. It should also be noted that the output of the timing flip-flop 1869 is fed back to its reset input. The time flip-flop, which was set to the value "1" and thus allowed the loading of the first reference address register 1870 and the D register 1878, is thus subsequently reset to the value "0".

Once the G register 1873 and the D register 1874 are loaded, the G, D access mechanism 1875 is activated. This mechanism causes the main memory to be called up at the address specified by registers G. and D, with a page descriptor being called (see Figure 16b). This mechanism performs the main memory fetch according to the G, D addressing described above. G, D access exceptions can occur as a result of this memory call (e.g. outside the segment, illegal GD segment descriptor). If such exceptions are found, the G, D access exception flip-flop 1876 is set to the value "1", which in turn activates the exception handling mechanism. Otherwise

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- S7-

When the G, D access is terminated, the mechanism transmits 1875 the retrieved data in the page descriptor register 1877. The The data transferred into the page descriptor register 1877 have the format according to FIG. 16b.

After the page descriptor register 1877 is loaded, the area number 1622 and the page number 1624 are put into a comparator 1878 entered, which is arranged in the arithmetic unit 1317. At this point, the area page number that is in the Area page register 1852 is stored and that was loaded when the page retrieval mechanism was triggered entered into the comparator in 1878. If the comparator determines equality, then the searched page descriptor has been found and the mechanism has finished its function. The "comparison fulfilled" line of the comparator 1878 is therefore sent to the Page Finder Completion Flip-Flop 1879 connected. That A signal output on this line sets this flip-flop to the "1" state, thereby terminating the page finder mechanism is shown.

If the comparator 1878 indicates an unsatisfied comparison, the signal delivered on the corresponding line prepares the AND gate 1880 and allows the transfer of the next descriptor 1620 from the page descriptor register 1877 to the comparator 1883 and to the AND gate 1885. The Comparator 1833 compares the next descriptor 1620 with the contents of the first pointer address register 1870. If the comparison is fulfilled, the entire pointer address chain of page descriptors has been searched and the searched page descriptor has not been found. Under these conditions, the searched area page is not in the main memory and the equality signal of the comparator 1883 is thus used to set the page exception flip-flop 1884. The exception handling mechanism is then triggered by setting flip-flop 1864. ''

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The output of the AND gate 1880, at which the next descriptor 1620 of the page descriptor register 1877 is pending, is also connected to the AND gate 1885. This AND gate will prepared by the "not equal" signal of the comparator 1883, the not equal condition occurs when the end of the page descriptor chain has not been reached by reference addresses. The next descriptor field from AND gate 1883 therefore becomes the AND gate 1882 when the not equal signal is "1". The other input signal to the AND gate 1882 is formed by the signal from an inverting amplifier 1881. This signal of the AND gate 1881 represents the inverted The output of the time flip-flop 1869. The signal output of the inverting AND gate 1881 thus assumes the value "1", when the time flip-flop 1869 outputs the value "0" and the AND gate 1882 is thereby used to transmit the next descriptor field 1620 is enabled to the OR gate 1872, this OR gate in turn being connected to the D register 1874. This series of logic gates moves the next descriptor field from the page descriptor register 1877 into the D register 1874 and the G, D access mechanism is then ready to be activated again. The cycle of G, D access is now started again and a new page descriptor is retrieved and stored in the page descriptor register 1877 loaded. This operation of fetching new page descriptors is repeated until either the comparator 1878 finds the one searched for Page descriptor detects or until the comparator 1883 detects the end of the page descriptor chain.

Two further essential elements of the hardware / firmware system are shown in FIGS. 19a and 19b and will be described in more detail below. The group descriptor according to FIG. 19a is used to describe _L the properties of a given group. According to FIG. 19a, the P field 1802 has two bits which describe the tip address class (mode) of the data record tip addresses in this group. All data sets as well as user data sets,

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as well as member records have reference addresses of the same Pointing address class related to a given group. The 1803 group descriptor user hint field is set to the value "1" if member records have a user reference address for the user record (see Figure 15c) included. The other field, denoting reference addresses, indicates whether user and member records are first, last, have next and previous reference addresses. The group realization mode field K-1805 describes the manner in which the group is established with regard to the current group is used. Only the mode of the ring groups is explained in more detail in this description. However, there is a possibility the expansion to other modes of group implementation, such as by table arrangement or list arrangement. That Shift field 1806 is used to display the offset of the beginning of the record in memory with respect to the beginning of the pointer sequence used in this data record (see FIGS. 15a and 15b), Auf, the group descriptor according to FIG. 19a is always accessed by the database command is taken when the hardware / firmware is supplied with a description of the group assigned to it.

The data record descriptor according to FIG. 19b is used for the description Properties of the data set used. THE F-FIELD 1820 is used to describe the data record format. The format of the data records corresponds to either a virtual memory data record or a database data record, as has been described with reference to FIGS. 15a and 15b. The record type field 1821 indicates the type of data set and may be loaded into the type field of the actual data set in memory, as shown in Figures 15a and 15b. The record length field 1822 shows the actual length of the record in the main memory and is loaded into the main memory data records as shown in FIGS. 15a and 15b.

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The actual database commands assign one of the six formats shown in FIGS. 20a to 20f.

The GROP format according to Figure 20a contains the operation code 1910, the zero field 1911, a base register number 1912 and a complementary code 1912. The base register contains the segmented address of a data record. The complementary code is for a further differentiation of the special command described by the operation code is used.

The XI format according to FIG. 20b contains an operation code 1920 a complementary code 19 21, which is used to further differentiate the operation code, an address syllable 1922 Null field 1923, a logical delay field 1924, a pointer mode field 1925 and a BR field 1926. The base register 1926 contains a segmented address of a data record. In some of its usages, the address syllable 1922 refers to a group descriptor of the Group. The address syllable is developed into a segmented address according to the rules of address development as described above.

The DXDX format according to FIG. 20c consists of an operation code 1930, a complementary code 1931, which is used for further differentiation of the command is used, an address syllable ASl-1932, a zero field MBZ1-1933, a base register BR-1934, a second zero field MBZ2-1935 and a second address syllable AS2-1936 together. The base register in turn contains the segmented one Address of a data record. The first address syllable ASl-1932 refers to a group descriptor. The second address syllable AS2-1936 is used to address a binary integer.

The BRX format according to FIG. 20d contains an operation code 1940, a type field 1941 which is used to further differentiate the command, a base register field 1942 and an address syllable 1943. The base register contains the segmented address

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of a data set. The address syllable is used to address a group descriptor.

The DXGR format according to FIG. 20e contains an operation code 1950, a type field 1951, which is used to further differentiate the command is used, a first base register field BR1-1952, an address syllable 1953, a first null field MBZ1-1954 second base register field BR2-1955, a before-after-first-last field 1956 and a second zero field MBZ2-1957. The two Base registers are used to address two different data records found in memory. The address syllable will used to address the group descriptor. That Before-after-first-last field describes the desired arrangement of a data record within the group.

The OPDD format according to FIG. 20f has an operation code i960, a base field I96I, which is used to describe a specific Database operation is used, a type field 1962, which is used to further differentiate the command P-Field 1963, which is used to describe the reference address field, a first-last-next-previous reference address field I965, which is the other pointing address of the users and Member data records describes the shift field I966, which describes the offset of the start of the reference address sequence, and a BR field 1977 which contains the number of a base register. The base register contains the segmented Address of a data record in the main memory.

The database command relating to the search for the user is a firmware / hardware command that contains a group descriptor which, together with a base register BB, gives access to the user pointer of the member data record supplies. The user pointer is in a segmented address implemented in accordance with its pointer class. The segmented address is then stored in the base register BBR

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loaded. If the pointer is part of the database record, the pointer is also loaded into an index register. The command relating to the searching of the user is in the XI format, as illustrated in FIG. 20b.

Referring now to Figures 21A through 21E, there is a firmware flow chart for the Finding the command in question is shown. Operation 2001 of the firmware flowchart is for checking of the command format. Operations 2003 to 2005 call for a group descriptor to which the Address syllable of the command is shown. There are also some preliminary checks on the group descriptor. According to operation 2007, a pointer is retrieved which is addressed by the base register BR 1926 of the instruction. Indexing takes place by means of the offset 1806, which is obtained from the group descriptor (which contains the pointer sequence of the data record * - see Fig. 15a, 15b and 19a). By operation 2009, the pointer operation is determined from the group descriptor (see Fig. 19a); he follows specialized Functions in accordance with the pointer operation.

In the following, particular attention will be given to FIG. 21A. In operation, operation 2001 is first used to check whether the MBZ field 1923 of the command (see Fig. 20b) is zero. This zero check is carried out by executing the command from of the instruction fetch unit (see Fig. 13a, IFU1318) into a Register in the arithmetic unit 1317 is transferred. If the hardware test carried out in this register leads to that MBZ is not zero, the firmware branches to the exception handling indicated in FIG. 21A with 2002. These The exception is called an illegal format field exception. If the MBZ field is zero, the firmware advances to the Operation 2003 continues, according to which 3 bytes of the main memory are retrieved or called; this call takes place at an address that is identified by the address syllable AS1922 of the

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Command is set. This address formation is carried out in the address control unit (see Fig. 13a, ACU1319). As a result of the call to the main memory, memory access exceptions can occur, as shown in FIG. 21A in block 2004 is illustrated. Some examples of memory access exceptions are j Out of segment, segment does not exist or outside of main memory. The three bytes called represent a group descriptor as it is in context has been described with Fig. 19a.

The next step shown in Figure 21A is that the K-bit 1805 of the group descriptor (see Fig. 19a) is checked is used to determine whether the K bit is equal to zero lsi The check 2005 is carried out in that the group descriptor, which was originally retrieved from main memory and transferred to the data business unit (see Figures 13a, 1321) is transmitted to the arithmetic unit 1317. If it is found that the K-bit part of the group descriptor is not zero, an operation occurs in accordance with operation 2006 relating to the unavailability of a group characteristic Treatment a.

If the K-bit is zero, the firmware proceeds to operation 2007 as shown in Fig. 21A. Accordingly a call is made in the main memory at an address given by the command format (see FIG. 20b) Contents of the base register BR1926 with respect to the shift 1806 of the group descriptor (see Fig. 19a) is given. These The address at which the retrieval takes place is the address of the user pointer in the pointer sequence of the data set referred to by the command (see Fig. 15-). As a result of this main memory call, memory access exceptions 2008 may occur. The

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called user pointer is stored in the auxiliary memory location "X" saved. The addition of the shift field (1806, FIG. 19a) to the content of the base register is carried out in the address control unit (see 1319, Fig. 13a).

The firmware proceeds to operation 2009, as shown in FIG. 21A, according to which the pointer operation of the referenced record is determined. This determination is made by checking the P field 1802 of the group end scriptor called in operation 2003 (see 1802 in FIG. 19a). This test is performed in the arithmetic unit 1317 shown in FIG _o 13a. For pointers of class 0, a branch is made to 2013 according to FIG. 21B. For pointers of class 1, a branch is to be made to 2010, and for pointers of class 2, a branch is to be made to 2011 according to FIG. 21D. For pointers of class 3, a branch is to be made to 2012 according to FIG. 21S.

The handling of class 0 pointers is illustrated in FIG. 21B. Operation 2014 returns the effective address of the data set pointed to by the pointer which is stored in auxiliary memory location "X" and which was called in operation 2007 of FIG. 21A is. Operations 2015 to 2019 check the status of the record pointed to by the pointer in the auxiliary memory location "X" is shown. This pointer points to the owner record of the group. The format for one Class 0 pointer is indicated in Figure 15e. If the record pointed to by the user pointer is found in the active state has been determined, the SRA part of the relevant pointer (see Fig. 15e) is in the Base registers loaded and the instruction is complete.

Details of Fig. 21B are now discussed

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Operation 2014 establishes the effective address of the member record in the address control unit (see 1319 in Fig. 13a) formed in that the segments only from the Base register BR is obtained and that the relative segment address SRA of the segmented address is obtained from the pointer X. that was called by operation 2007. In the 2015 operation, this will be the result of the operation Segmented address formed in 2014 used the D-toggle field of the data record from the main memory (see Fig. 15a for the description of the D-toggle field 1502 of a data record). As a result of this main memory call 2016 memory access exceptions such as "out of segment" or "outside of the physical memory ".

The 2-bit D-toggle that is called from main memory is transmitted from the data management unit (see 1321 in FIG. 13 a) to the arithmetic unit 1317. These Transmission takes place under the control of the firmware using microinstructions; in this way the Transfer effected from the register in the data management unit to the register in the arithmetic unit.

In operation 2019, the D-toggle field, which is now is housed in the arithmetic unit 1317, checked to see if it is zero. If this is the case, the Firmware branches out to exception handling 2020, which results in a record that was deleted by an exception is reported.

Incidentally, the D-toggle field must be equal to 1, that is the record active state, and the firmware branches to operation 2021. At this Operation becomes the relative segment address part of the SRA

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User pointer (see Fig. 15e) to the offset part of the Base register transferred (see 202 in Fig. 2). This transmission is a 15-bit right-most transmission standing 15 bits of the pointer, which is stored in the buffer location "X". There are only 15 bits transmitted because the EOS bit (15 ^ 0) is equal to 1 in the case of the user pointer (see FIG. 15e) and there in the case of the user pointer

the
by definition, the / EOS bit is set. A zero is erased in the first bit position of the SRZ field 202 of the base register, and accordingly the hardware / firmware converts this bit to a zero bit while the remaining 15 bits of the pointer are transmitted / earthed. The next operation is operation 2022, in which the instruction is now complete and in which the firmware branches to the next instruction.

The handling of the class 1 pointers is illustrated in FIG. 21C. Operation 2023 forms the effective address of the data record to which the member pointer is shown, which is stored in the auxiliary memory location "X" which is determined by operation 2007 according to FIG. 21A has been called. In operations 2024 to 2029, the status of the data record to which there is shown the pointer stored in the auxiliary memory location "X". This pointer shows on the user record of the group. The format for class 1 pointers is illustrated in Figure 15f. If regarding of the record pointed to by the user. pointer is determined to be in the active state, then the SEG, SRA part of the relevant pointer is loaded into the base register and the instruction is complete.

Details of Figure 21C will now be considered. In operation 2023, the effective address of the user # data record in the address control unit (see 1319 in Fig. 13a)

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formed by the fact that the segment only and the SRA address is obtained from the pointer called by operation 2007 and stored in the buffer at memory location "X" has been saved. In operation 2024, this segmented address formed by operation 2023 is used to to call up the D switch field of the data record from main memory (see FIG. 15a for an explanation of the D-toggle field of a data record). As a result of this main memory call, memory access exceptions 2025 occur such as "out of segment" or "out of physical memory".

The 2-bit D-toggle that is called from main memory is transmitted from the data management unit (see 1321 in FIG. 13 a) to the arithmetic unit 1317. This transfer takes place under the control of the firmware using microinstructions. In this way is the transfer from the register in the data management unit to the register in the arithmetic logic unit.

In operation 2028, the D toggle field that has been loaded into arithmetic unit 1317 is checked to determine whether it is equal to 0. If this is the case, the firmware executes a branch to the exception handling 2029 according to to which a data record that has been deleted by an exception is reported.

In addition, the D toggle field must be set to the data record active state, and the firmware branches to operation 203-0. In operation 2030, the rightmost 31 bits of the pointer contained in the intermediate memory location "X", which has been called from the main memory, is stored in the furthest 31 bit positions of the basic register BR on the right are loaded

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den (see Fig. 20t), box 1926). Only 31 bits are transmitted because the EOS bit 1551 is the user pointer (see 15f) is equal to 1 and since the SOS bit is set by definition in the user pointer and since it is actually desired is that the first leftmost bit of the base register is left at 0. The hardware / firmware moves the first bit of the base register to zero. The next operation is operation 2031, "where the command is now complete and in which a branch to the next instruction is made by the firmware.

Referring to Figures 21D and 21E, the handling of pointers will be discussed of class 2 or class 3. In operations 2032 and 2033, the area page line number address becomes of the data set referenced by the instruction, formed from the pointer contained in the It contains cache "X" that was called in operation 2007, and so does the third to tenth bits of the index register in the case of class 2 pointers present. In operation 2034, the Page descriptor (see FIG. 16b) of the page called, the number of which is specified in the area page line number. the Line number is then translated to a segmented address in operations 2036-2043, in accordance with that described above in connection with Fig. 16a Mechanism. The D-toggle field of the line shift field post (see 1602 in Fig. 16a) the operations 2047 to 2050 with respect to the state of the line (data record) checked. If the line is in the active state, the segmented address that corresponds to this line number will be is then loaded into the base register, the number of which is specified in the command format (see field 1926 in Fig. 20b). In operations 2053 Ms 2057, the index register corresponding to that in the base register field 1926 of the

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Command format specified number also with an area-page-line number or loaded with a page-line number in accordance with the pointer class. The command is then completed.

Details of FIGS. 21D and 21E are discussed below. At 2011, the case of a class 2 pointer is dealt with. The firmware branches to operation 2032 on class 2 pointers. There the area number for the area page line number is called from index register bits 2 to 9. The page line number is called from the buffer ^{location 11} X ". The area number is linked or concatenated with the page line number and then loaded into an intermediate register which may be referred to as the area page line register. This register is in the Computing unit 1317 housed.

In 2012, the case of a class 3 pointer will be dealt with. The firmware branches out to operation 2033, in which the contents of the buffer location "X" in the area-page-line intermediate register is transferred »

In the two operations 2032 and 2033, a branch is made to operation 2034, according to which the page descriptor is is called which corresponds to the page number which is given by the temporary register area page line. This The call is made by the firmware subroutine relating to the page definition described in connection with FIG. 17. As a result of this firmware subroutine, an exception 2035 regarding page-by-page calling. If the page descriptor has been called successfully, the Firmware over to operation 2036, in which the line number from the cache area page line to another Intermediate register W is transferred, which is located in the arithmetic unit (1317 according to FIG. 13a). This transfer of the line

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number to register W is a transfer of a number of bits identified by the shift count field of the page descriptor are given (see field 1623 in Figure 16b).

At operation 2037, the firmware calls the segment descriptor of the SEG number obtained from the page descriptor (see Figure 16b, box 1625). As a result of this memory call, memory access exceptions 2038 may occur. The through the segment descriptor called operation 2037 is used in the Operation 2039 is used to obtain the base address of the segment in question. As above with reference described on Fig. 16a, the beginning corresponds to a database page the beginning of the equivalent segment. Accordingly, in operation 2039, the base address of the segment is set to be Address of the page header (see 1601 in Fig. 16a) used, to get the maximum line number. This maximum number of lines or line number becomes an intermediate register Z transferred in the arithmetic unit 1317. As a result of the memory call at operation 2039, memory access exceptions Occur in 2040.

In operation 2041, the validity of the line number or line number W is checked by determining whether the absolute The value of W is less than the maximum number of lines Z If W is not less than Z, the Firmware performed for exception handling in which an exception 2042 relating to an invalid page format occurs. Otherwise, the firmware proceeds to operation 2043 where the 16-bit line offset field data word 1602 is called under an address that is determined by the segment base plus the length of the page header 1602 (81 bits) plus the number of lines W times 16 bits (these 16 bits represent the length of a single line offset field data word dar). As a result of this memory call

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2044 memory access commands can occur.

At operation 2045, the D-toggle field 1604 becomes the offset-line field data word transferred to a register in the arithmetic unit 1317. The firmware then branches to it 2046 (Fig. 21E).

Operation 2046 then goes over to operation 2047, according to which the D toggle field, which is now in the arithmetic unit 1317 is checked to see if it is the same. If this is the case, the firmware branches to the removal treatment 2048, indicating the presence of a the exception concerning the non-use of a row is reported will. Incidentally, in operation 2049, the D toggle field is checked to see if it is 1 or 3. Is one of those If conditions are met, a branch is made to exception handling 2050, one relating to the deletion of a line Exception is reported.

In addition, the D-toggle field must be equal to 2, whereby the Active state of the data set is indicated and the firmware branches to operation 2051. at of operation 2051, the segment number SSG of the database page currently in use is obtained from the page descriptor has been loaded (see Fig. 16b, field 1625) into the base register BR, the number of which is in the field 1926 BR des is given the instruction format shown in Fig. 20b. The segment only is transferred to the base register at bit positions 4 to 15., The next operation performed is the operation 2052 in which the offset portion of the line offset field data word 1603 in the SRA portion of the base register BR (Field 202 according to FIG. 2) is transmitted.

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At operation 2053, the pointer mode becomes of the group descriptor called by operation 2003 (see 1802 in FIG. 19a). When the operating mode equals 3, operation 2054 is performed to determine the rightmost 30 bits of the content of the intermediate storage location "X" (starting from bit 2) into the 30 bit positions furthest to the right of the index register IXR, starting at bit position 2. In response to operation 2054, operation 2056 executed according to which the instruction is completed and according to which the firmware executes a branch to the next instruction. There is a transition back to operation 2053 if the arithmetic unit has determined the pointer operating mode becomes that she is 2. The microinstruction flow branches to operation 2055 where the am Rightmost 22 bits of the pointer stored in the buffer location "X" (starting from the bit position of the pointer) in the rightmost 22 bits of the index register IXR, starting at bit position 10 of the index register. In response to operation 2055, operation 2054 is carried out according to which the command is completed and according to which the firmware branches to the next instruction.

In FIGS. 22A to 22D in a block diagram representation of a hardware realization of the relevant consulting a user database command illustrated in Figure "22A to 22C, the hardware logic is shown that actually stores data and various operations executing on the data relevant to the prospecting of a user Execute command. Referring to Fig. 22D, there is shown the control logic used to process transfers and operations on the data in the course of executing the command relating to the retrieval of a user. The control logic shown in Fig. 22D is often used as a loop or cycle

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counter logic denotes

The following briefly summarizes the operation of the control logic shown in FIG. 22D in order to facilitate the understanding of the hardware logic shown in FIGS. 22A to 22C. First, it can be seen that cycle 1 through cycle 7 flip-flops 2401 through 2407 define a series of seven consecutive time periods. The AO to A5 cycles 2411 to 2416 define a 6-cycle control sequence which is used to control the operations in the course of executing the database command relating to the retrieval of a user in the event that a virtual memory data record, a data record of the Pointer operation type 0, is being worked. The cycle BO, the cycle B1 and the cycle B4 in connection with the Α cycles (which will be explained further below) define a cycle control sequence which is used in the course of the execution of the hardware operations for the database command relating to the search for a user is that a virtual data storage set, a data set of pointer mode 1, is being worked on. A 14-cycle control sequence is defined by the CO cycle 2431 to C12 cycle 2444, which is used to control the hardware operations in the course of executing the database command relating to the search for a user in the event that a database data record, a Data record of pointer operation type 2 is being worked. The D1 cycle 2451 and the D11 cycle 2452, in conjunction with the C cycles, define a control sequence which is used in the course of controlling the hardware operations which are used to execute the database command relating to the search for a user in the event that a database data record, a data record of the pointer 3 type, is being worked on «,

22A to 22C are considered in more detail below. On "

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the inclusion of a command relating to the retrieval of a user, as indicated by the detector 2201 of FIG. 22A, the command is loaded into the command buffer 2202. The command buffer is located in the command fetch unit 1318 of the central processing unit 104. "As mentioned above, the command relating to the retrieval of a user which has been transferred to the command buffer 2202 is an XI format command as shown in FIG. 20B The MBZ field 1931 is compared directly with the O bits 2204 by means of a comparator 2203. If the comparator 2203 emits a signal indicating a mismatch, the presence of an exception relating to an illegal format field is determined, and an exception is determined for the illegal one Format field provided flip-flop 2205 is set. This causes the activation of the exception handling mechanism, the execution of the instruction relating to the retrieval of a user is then completed. If the comparator 2203 indicates a match, the execution of the instruction relating to the retrieval of a user continues, as described below. Let it be pointed out that the agreement signal of the comparator 2203, which rises to a logic value "1" when it is determined that the 14BZ field 1923 is equal to zero, is the input signal for the set input of the 1-cycle flip-flop 2401, which is shown in FIG 22D is shown «. Accordingly, the comparison match triggers the cycle sequences ^ Cycles 1 to 7.

The cycle 1 signal enables the AND gate 2206 to transfer the address syllable 1922 from the instruction buffer 2202 to the address control unit 2207 (see Fig. 22B). This transfer takes place via an OR gate 2217 which is connected to the AND gate 2206 is an address syllable If _o is dispensed sets the address control unit 2207, the address syllable in question in a memory address in order. The memory address established by the address control unit 2207

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is supplied to the memory address register 2209, Since the OR gate 2218 the cycle 2 signal at one of its inputs is supplied, is in cycle 2 that with the ODaR element 2218 connected AND gate 2219 enabled, the memory address in the memory address register 2209 to the ODL'R gate 2220 to transfer. The OR gate 2220 is in turn connected to the memory address register 2210 of the memory system 2213.

A user's respective instruction provided for the determination of the picking out detector 2201 is also connected to an inverting AND gate 2211 which in turn is connected to the memory system read / write Plipflop 2212 connected _o Sin from the respective detector having a logic value "1 "The output signal causes the output signal of the AND gate 2211 to appear with a logic value" 0 ", as a result of which the read / write flip-flop 2212 is set to zero. When the memory system 2213 has determined that the memory address register 2210 has been loaded and that the read / write flip-flop 2212 is in the 1 state, a memory read operation is initiated. As a result of a memory operation, memory access exceptions 2214 may occur. When such exceptions occur, the memory access exception flip-flop 2214 will be set to the 1 state. The exception handling is activated. Incidentally, the store operation will be terminated normally, and the store operation completion flip-flop 2215 will be set to the 1 suffix. Upon the transition of the memory operation completion flip-flop 2215 to a 1 state, the data read from the memory system 2213 has been transferred to the memory data register 2216 (shown in Fig. 22C). The transition of the memory operation complete flip-flop 2215 to the 1 state thus indicates that the group descriptor addressed by the address syllable of the instruction relating to the retrieval of a user (see FIG. 19A) is in the

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Storage data register 2216 has been accommodated.

At this point it should be pointed out that the output of the cycle 2 flip-flop 2402 according to FIG. 22D is also connected to the AND gate 2481 which is connected by the memory operation completion signal from the memory operation completion flip-flop 2215 is made transferable according to Fig. 22B. With the completion of the reading of the The group descriptor addressed by the command relating to the retrieval of a user becomes the cycle the cycle sequence triggered or initiated "

The K-field 1805 of the Gruppendeskriptors contained in the memory data register 2216 is connected to the AND gate 2221 which is made capable of transmission by the cycle-3 signal, as is illustrated in Figo 22C _o The output of the AND gate 2221 is in turn connected to one input of the comparator 2222. The other input of the comparator 2222 is determined by "O" bits 2223. If the comparator 2222 determines that the K field 1805 is not equal to zero, then the signal output by the comparator 2222 and indicating the mismatching rises to a logic value "1" and the unavailable group feature exception flip-flop 2224 becomes set to the "1" state. Exception handling is then activated and the command completes. If it is determined that the K field 1805 is equal to zero, the match signal output by the comparator 2222 connected to the AND gate 2482 in FIG. Flip-flops 2403 is enabled or activated to set the cycle 4 flip-flop 2404.

The P field 1802 of the memory data register 2216

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- 1D7 -

The group descriptor held is transferred via the AND element 2225, which is made transmittable by the cycle 4 signal. Accordingly, in cycle 4, the P field 1802 becomes over the AND gate 2225 transferred to the P register 2226 to which the AND gate 2225 is connected.

The shift field 1806 of the group descriptor contained in the memory data register 2216 is ^{fed to the UI 1} JD element 2227, which is also made transferable by the cycle 4 signal, as is illustrated in FIG. 22B. Accordingly, shift field 1806 is transferred to shift register 2228 in cycle 4. It should be understood that the cycle 4 signal is one of the input signals of the OR gate 2270, which is connected to the AND gate 2271. Accordingly, the AND gate 2271, which the BR field 1926 of the Command is supplied, made transferable, and the output of the AND gate 2271 is transferred to the BR base register input 2208 of the address control unit 2207.

If the address control unit 2207 with a base register number or base register number at its BR base register input 2208 is supplied, the resulting measure is that the content of the base register is read out, whose number has been entered. This operation is a typical cache read operation. The one from the The base register content delivered to the address control unit is transferred to the base register / output register 2230 of the address control unit submitted. The base register / output register 2230 controls one input of a dual input Adder 2229. The shift register 2228 is connected to the other input of the adder 2229, which previously has been loaded. The output of the adder 2229, which the contents of the base register BR with that by the

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The shift content of the register 2228 represents increased displacement field (see Fig. 2, 202) is fed to the AND gate 2231, as can be seen from Fig. 22A. The AND gate 2231 is made capable of transmission by the cycle 5 signal. The output signal of the AND gate 2231 is in turn an input signal for the OR gate 2217, which with the Address control unit is connected »The address control unit sets when it is addressed with the contents of the base register (see Fig. 2) this content is converted into a memory address. Accordingly, the output of the address control unit is 2207 again an address which is transferred to the memory address register 2209. As another input signal the input to OR gate 2218 is the cycle 6 signal is, as can be seen from Fig. 22B, in cycle 6, the address in the address register 2209 which corresponds to the OD ^ R element 2218 transferable controlled AND element. 2219 is connected via the OR gate 2220 to the memory address register 2210 transferred the storage system

the memory system 2213 again determines that its memory address register 2210 is loaded with a new address and that the read / write flip-flop 2212 is in the NuIl state a memory read operation is initiated. As a result of a memory read operation, Memory Access Exceptions 2214 Occur "If such exceptions occur, the memory access exception flip-flop 2214 set to the 1 state. The exception handling is activated. Otherwise, the memory operation becomes normal is completed, and the memory operation completion flip-flop 2215 is set to the 1 state (the memory operation completion flip-flop 2215 is reset to the null state upon initiation of any new store operation). With Completion of the storage operation is the data read from the storage system, which represent a database pointer

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(see Figs. 15e, 15f, 15g and 15h) to the storage data register 2216. It can be seen from FIG. 22D that the AND element 2483, with which the output of the cycle 6 foot flop 24o6 is connected by the memory operation completion signal from the memory operation completion flip-flop 2215 is rendered transferable. Accordingly, in cycle 6, After the memory operation is completed, cycle 7 is initiated by AND gate 2483, which is connected to the set input of cycle 7 flip-flop 2407,

Returning to Figure 22C, it should be seen that the P register 2226 is connected to a number of AND gates and to four flip-flops, which are connected to AS2241, BS2240, CS 2239 and DS 2238 are designated. The purpose of this particular logic is to set the pointer mode of operation of the data record with which the processing is involved and in the flip-flops A2245, B2244, C2243 and D2242 (specifically for storing the fact whether the pointers are of type 0, 1, 2 or 3, which is stored in the corresponding flip-flops A, B, C and D). To effect the decoding of the pointer mode, Bit no. 0 (the leftmost bit) of the P register 2226 is fed to the inverting AND gate 2232. Bit # 1 (the rightmost bit) of P register 2226 also becomes an inverting AND gate 2233 supplied. The AND gates 2234 to 2237 are used to decode the two bits of the P register 2226. That AND element 2237 receives the two inverted bit values of the P register from the inverting AND elements as input signals 2232 and 2233. Accordingly, the signal of the AND gate 2237 rises to a "1" link value when the Value in the P register is zero (binary 00). In this case, the cycle 7 signal would be transferable to AND gate 2237 make, which sets the AS flip-flop 2241 »Referring to Fig. 22D, it should be noted that the

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_ 11 Π—

AS flip-flop 2241 is used for this, the A cycle sequence to initiate, comprising the AO cycle 2411 through the A5 cycle 2416. The AS flip-flop 2241 is also with its output connected to the A flip-flop 2245. The A flip-flop 2245 stores that the P register 2226 has a zero value (that is, the virtual memory record in the pointer mode of operation of type 0). The AS flip-flop 2241 is also connected to its reset input on the output side. To Once the A flip-flop 22245 has been reset and the A cycle sequence initiated, the AS flip-flop is thus reset to zero.

The AND gate 2236 is the inverted P-bit Hummer 0 and the non-inverted P-bit No. 1 is supplied. Thus, in cycle 7, in which the AND gate 2236 becomes transferable is done, the BS flip-flop 2240 is set to the 1 state, if there is a value of 1 (binary 01) in the P register. Analogous to the case of the type 0 pointer mode, the BS flip-flop 2240, the B flip-flop 2244 is set, and the B-cycle sequence is initiated. The BS flip-flop 2240 resets itself after these operations are complete.

The AND gate 2235 is supplied with the non-inverted P bit No. 0 from the P register 2226 and the inverted P bit No. ₀ 1. Accordingly, the CS flip-flop 2239 is set in cycle 7 by the AND gate 2235, which is made transferable by the cycle 7 signal, provided the value in the P register is equal to 2 (binary 10). Analogously to the cases considered above, the CS flip-flop 2239 would set the C flip-flop 2243 (in which it is stored that a database data set, a data set of pointer mode type 2, is being used). The CS flip-flop 2239 also initiates the C cycle sequence. The CS flip-flop 2239 also turns on after the C flip-flop 2243 has been set and after

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Initiation of the C cycle sequence itself.

The AND gate 2234 receives the non-inverted P bit no. 0 and the P-bit No. 1 is supplied. Accordingly, in cycle 7, the AND gate 2234 is enabled or transferable is done, the DS flip-flop 2238 is set to the 1 state, if the P register 2226 contains a value of 3 (binary 11); this shows the existence of a database record, of a data record of the pointer operation type 3 ». After the DS flip-flop 2238 is set to the 1 state, it triggers the D cycle sequence off; furthermore, the relevant flip-flop causes the D flip-flop 2242 to be set to a database data record of pointer type 3 to be processed. The DS flip-flop 2238 is also with its output connected to its reset input, which causes the relevant flip-flop to self-activate after the above operations have been carried out resets.

It can be seen from Fig. 22D that the B cycle has fewer cycle periods than the Α cycle and that in some cases the output of a B cycle flip-flop is fed to an OR gate with the output of an A cycle flip-flop, to set another cycle flip-flop. This takes place in consideration of the commonality in the A-cycle operations (pointer type 0) and the B-cycle operations (pointer type 1). In those cases in which instruction operations of pointer type 0 and pointer type 1 require the same control sequence, the cycle A signal is set either by the previous A cycle signal or by the previous B cycle signal. An example of this is shown., The cycle A1 flip-flop 2412 and the cycle B1 flip-flop 2422 are connected to an OR gate 2484, which sets the cycle A2 flip-flop 2413 after a sequence of common A and B-cycle processes - at this point in time, the states of the pointer operation

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Type O and pointer operation type 1 have different measures - separate cycle A or cycle B flip-flops are set again. An example of this is as follows A3 cycle 2414, according to which the output 'of the A3 flip-flop 2414 is connected to the UkD-GIied 2486. This AND element becomes transferable by the Α signal from the flip-flop 2245 is made (indicating pointer operation type 0) to set the cycle A4 flip-flop 2415. The outcome of the Cycle A3 flip-flops 2414 is also with the ^ AND gate 2487, which is made transferable by the B signal from the flip-flop 2244 (display of the Pointer operation type 1) to the cycle 4 flip-flop 2423 set.

Also shown in Fig. 22D is the C cycle sequence (Pointer operation 3T? S 2) and the D cycle sequence (Pointer operation type 3) share a large number of cycle sequences again together, because of the commonality in the C-cycle operations and the D cycle operations. The notification mechanism that provides an indication of separate C-cycle and D-cycle operations is the same mechanism used in conjunction with the Cycle Α and Cycle B signals will. It should be noted that considering that the hand operation type 2 and the hand operation type 3 assume common operations, the CS flip-flop 2239 and the DS flip-flop 2238 with an OR gate 2489 are connected, which in turn is connected to the set input of the cycle CO flip-flop 2431. The cycle is GO thus the two-line cycle for the two C and D cycle sequences.

The link operations in Figs. 22A to 22C will now be discussed. It has already been described above how following cycle 7, cycle sequences A, B, C or D are initiated. First, let the operation be the A- and

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B cycle sequences considered In this context it should be noted that the SRA field of the pointer in the storage data register 2216 (1542 for a class 0 pointer or the field 1452 for a class 1 pointer) with the AND element 2248 is connected as shown in Fig. 22A. The cycle AO signal and the Cycle 30 signals are fed to the ODJiR gate 2247, which in turn makes the AND gate 2248 transferable. Either in cycle AO or in cycle BO thus becomes the AND element 2248 made transferable to transfer the SRA portion of the pointer read from memory to the SRA register 2249. It should also be evident that the SJiG field 1552 of the pointer (this field is legally important in the case that a pointer of class 1 is being worked on) from the memory data register 2216 to the UHD member 2250 will «, the AND gate 2250 is activated by the cycle BO signal released or made transferable, whereby the SEG field 1552 transferred to the SIG register 2316 in cycle BO will.

In cycle 31, the SRA register 2249, which is connected to the AND gate 2253 - which is enabled or made transferable by the cycle B1 signal - transfers the SRA register contents via the OR gate 2255 into the offset field of the EAX Register 2257 (the format of this register is the same as that shown for a base register 202 in Figure 2). The AND element 2254, to which the SEG register 2316 is connected, is also enabled by the cycle 31 signal to transfer the content of the relevant register to the SEG part of the EAX via the relevant OR element 2256. to transfer the register 2257 (d? r SlüG portion of the SAX register is the box shown in Figure 2 with _o 202 STN, STE).

If the pointer operation being worked on is given by a pointer of type 0, the cycle A1 signal outputs the Transfer of the SRA register 2249 via the AND element 2252

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and OR gate 2252 in the offset part of the EAX register 2257 free. The SSG part (or equivalents, namely STiI, STE) of the base register - output register 2230 - the one before has been loaded, as previously described - is supplied to the UM) -GUed 2251, which is carried out by the cycle A1 is made transferable. Accordingly, in cycle A1 the segment number of the base register via the OR gate 2256, to which the AND gate 2251 is connected, into the SSG part of the SAZi register 2257.

after the EAX register 2257 has been loaded, the Contents of this register - which is a segmented address of the format designated in FIG. 2 with 202 - transmitted via the OR gate 2217 into the address control unit 2207, shown in Fig. 22B. The address control unit 2207 sets, if you have a segmented address (the one in Fig. 2 with 202 format) is supplied, the address in question is converted back into a memory address. Accordingly, will the output signal of the address control unit 207 is transferred back to the memory address register 2209. There is another Input signal of the input signals of the OR gate 2218, which enables the AND gate 2219 or makes it transferable, is the cycle A2 signal (which is either based on the Cycle A1 or following cycle B1), then the address in the address register 2209 of the address control unit Transferred via the AND gate 2219 and the OR gate 2220 to the memory address register 2210 of the memory system 2213.

When the memory system 2213 again determines that its memory address register 2210 has been loaded with a new address and when the read / write flip-flop 2212 is in the NuIl state is then another memory read operation is initiated. As a result of a memory read operation, Memory access exceptions 2214 occur. If such exceptions occur, memory access exception flip-flop 2214

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set to the 1 state, and the exception handling limgsmechanismuG is activated. Otherwise, the memory operation is normally completed and the memory operation completion flip-flop 2215 is completed is set to the 1 state. At the end of the store operation the data read from the storage system, which represent the part of a virtual storage data set, which the D-field (or "D-flip field") 1502 according to FIG. 15a, transferred to memory data register 2216.

As shown in Fig. 22D, the output of the cycle A2 flip-flop 2413 is connected to the AND gate 2485, which is enabled or made transferable by the memory operation completion signal. To the termination of the store operation the AND gate 2485 is thus enabled, set cycle A3 flip-flop 2414.

In cycle A3, the AND gate 2258, which is generated by the Cycle A3 signal is made transmissible, D-field 1502 of the virtual memory data set from the memory data register 2216 to one of the two inputs of the comparator 2216 there. A series of zero bits 2259 are fed to the other input of the comparator 2260. If the comparator determines 2260 that the D-field 1502 is equal to zero, the match signal provided by the comparator 2260 increases to one "1" link value. As a result, the exception flip-flop 2261 relating to a deleted data record is in the 1 state set. The exception handling mechanism is then activated and the instruction completes. Furthermore the disagreement signal of the comparator 2260 rises to a "1" link value. With regard to on FIG. 22D it can be determined that the inequality signal of the comparator 2260 corresponds to the two AND gates 2486 and 2487 is fed. If there is an inequality state, either the AND element 2486 can be transmitted made - if the A signal 2245 is a pointer operation of the

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Type O indicates - or the AND element 2487 is transferable made if the B signal 2244 indicates a type 1 pointer operation. The AND gate 2486 causes, if it is through made the Α signal and the inequality signal transmittable is to set cycle A4 flip-flop 2415 to the Cycle A3 out. The AND gate 2487 effects, if it is by the B signal and by the inequality signal from the comparator 2260 is made transferable, the setting of cycle B4 flip-flop 2423 in response to cycle A3.

Since the inputs of the OR gate 2263 according to FIG. 22B are supplied with the cycle A4 signal and the cycle B4 signal, the AND gate 2362 is transferable in each of these cycles to read the SRA register 2249 or its content via the OR gate 2264, to which AND gate 2362 is connected, to the offset field of the BR base register input register 2267 (the BR input register 2267 has the format shown in Fig. 2 with 202). If a record of the Pointer mode 1 is being processed, the cycle B4 signal is set the AND gate 2265 in the state, the SBG register 2316 via the ODüR element 2266 into the SEG part of the BR input register 2267 (the SEG part is equivalent to the field STN, STS, as shown in Fig. 2 with 202).

Since the cycle A4 and cycle B4 signals are input signals of the OR gate 2270, through which the AND gate 2271 is made transferable, is the AND gate 2270 in FIG Each of these cycles enabled, the BR field 1926 of the instruction buffer 2202 in the BR area 2208 of the address control unit 2207 to transfer »If the address control unit 2207 has a BR register number in its BR area 2208 and when the BR input register 2267 is loaded with a new value, the address control unit writes enter the value in the BR input register 2267 into the base register using a normal buffer

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Write operation This means that the base register, whose base register BR number is specified in instruction error 1926, is has now been updated with a segmented address value that is the address of the member record of the Is the data record that was originally pointed to by the content of the same base register BR.

From a renewed consideration of FIG. 22D it should be apparent that the cycle A4 flip-flop 2415 and the cycle B4 flip-flop 2423 are each connected to the OR gate 2488 on the output side. Accordingly, the ODUR gate 2488 sets the cycle A5 flip-flop 2416 on either cycle A4 or cycle B4. Dfiss cycle A5-signal which is an input signal of the ODiiR gate 2272 is used to to set the command completion flip-flop 2246 as shown in FIG. 22C is seen _o The setting of the command completion flip-flop 2246 as well as the display of the Completion of the command to the central unit also leads to the resetting of the flip-flops A2245, 32244, C2243 and D2242, since each of these flip-flops receives the command completion signal at its reset input, as can be seen from FIG. 22C. It should be noted that only one of these four B'lip-flops is actually set to the 1 state, since the P value should only cause the original setting of one of the flip-flops »

The following are the C and D cycle sequences for data records of pointer operation types 2 and 3 considered in more detail. As above executed, the C and D cycle sequences each start with the cycle CO signal from the flip-flop 2431 shown in FIG. 22D. The flip-flop 2431 is set via the OR gate 2489, to which the CS flip-flop 2239 and the BS flip-flop 2238 are connected are. In cycle CO - for this purpose, go back to FIG. 22A - the AND gate 2274 ^ which is given by the Cycle CO signal is made transferable, supplied

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1-bit 2317 is transferred to the leftmost bit position of the Zv.'ischenspeicheradressregister 2275 »The BR field 1926 of the command buffer 2202 is fed to the AND element 2273, which is set by the cycle CO signal, the 3R-iumers from the instruction buffer 2202 to the rightmost three bit positions of the buffer address register 2275. The address of an index register, which corresponds to a base register BR in the manner described above, is thus loaded into the intermediate storage address register 2275 in the cycle CO. It should be pointed out that the buffer read / write flip-flop 2277 was previously in the iiull state when the command detector 2201 for the determination of a member command to be found emitted a signal which rose to a logic 1 value; accordingly, the output signal of the inverting AND gate 2211 drops to a KuIl logic value. The relevant AND element is connected to the ODÜR element 2278. The output signal of the QDÜR gate 2278, which in turn is connected to the buffer read / write flip-flop 2277, would initially be set to a full-tied., The buffer 2276 initiates a buffer read operation of the address contained in the buffer address register 2275, and on the determination that the latch address register 2275 has been loaded with an address and that the latch read / write flip-flop 2277 is set to the zero state 2202 is included. This is done upon loading the buffer _{address register 2275 in cycle CO 0.} At the end of the buffer operation, the index register read from the memory is transferred to the buffer data register 2318.

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In cycle C1, which only occurs when the pointer operation of the type 2 is present -. As shown in FIG 22D can be seen by means of the flip-flop 2432 - is the field 1572 (shown in FIG _o 15h is shown) of the index register in the area of part of the divisional Page line number register 2281 loaded. This transfer takes place via the AND gate 2319, which is made transferable by the cycle C1 signal. In cycle C1, the page line number part of the pointer contained in the memory data register 2216 - which register was previously read from the memory system 2213 - is loaded into the page line number part of the area page line number register 2281. This transfer takes place via the AND element 2279, which is made transferable by the cycle C1 signal.

In cycle D1, to which an operation of pointer mode 3 corresponds, as only shown in Fig. 22D by flip-flop 2451, the full area page line number becomes like this is illustrated in Fig. 15h - from the memory data register 2216, into which the pointer was previously after a memory read operation has been loaded into the entire area-page-line number register 2281 transferred. This transfer takes place via the AND gate 2280, which is triggered by the cycle D1 signal is made transferable.

In cycle D1, to which an operation of pointer operation type 2 corresponds, as is only apparent from Fig. 22D with the aid of flip-flop 2451, it becomes the full area-page-line number - as shown in Fig. 15h - from the memory data register 2216, in which the pointer was previously after a memory read operation has been loaded into the total area-page-line number register 2281 transferred. This transfer takes place via the AND gate 2280, which is triggered by the cycle D1 signal is made transferable.

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From Fig. 22D, it is seen that the cycle C1 signal or cycle C2 follows the cycle D1 signal. this will thereby causes the output of cycle C1 flip-flop 24J2 and the output of cycle D1 flip-flop 2451 to the OR gate 2492 are connected, which in turn is connected to the set input of the cycle C2 flip-flop 2433.

In cycle C2, the AND gate 2282 is transferable, whereby the transfer of the range page line register 2281 to the set page mechanism 2284 is enabled. the Operation of the relevant mechanism 2284 has already been described above; a hardware implementation for the mechanism in question is shown in FIG. Activation of the mechanism in question 2284 includes this Set enable page commit flip-flop 2283 caused by cycle C2 signal and load of the area page register 2285 into which the area page part of the area page line number register 2281 is transmitted via the AND gate 2282, which is made transmittable by the cycle C2 signal. The enable page lock flip-flop 2283 corresponds to the flip-flop 1851 shown in FIG. The Area Pages tab 2285 corresponds to register 1852 in FIG. 18. As described above, the operation of the paging mechanism 2284 lead to exceptions when working through pages. In this case it will be for the exception of the page-wise Enabled flip-flop 2286 is set and the exception handling mechanism is activated. The exceptional flip-flop 2286 corresponds to flip-flop 1884 in FIG. 18 “If an exception does not occur when working through the pages, the page descriptor that corresponds to the page number is which is given in the area page register 2285 is loaded into the page descriptor register 2289 (which corresponds to the register 1877 in Fig. 18). It also turns the page commit completion flip-flop 2287 set (which corresponds to the

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Flip-flop 1879 in Fig. 18 corresponds to) _β The format of a page descriptor as loaded into page descriptor register 2289 is shown in Fig. 16 and described above.

Referring to Fig. 22D, it should be noted that the page setting completion flip-flop 2287 is set to the 1 state in the event that the cycle C2 flip-flop 2433 in the 1 state is the AND gate 2493 has controlled transferable, which in turn initiated cycle C3 of the C cycle sequence

The cycle C3 signal makes the MD element 2291 transferable, which the shift counter field 1623 of the page descriptor into the Shift count register 2292 transfers,, This shift count is used to record the area page line number from the area page line register 2281 and the Move out the line number part of the relevant number and then the relevant line number in the ^ register 2296 to load. In addition, the segment number field 1625 of the page descriptor via the AND gate 2290, which made transmittable by the cycle C3 signal is transmitted to the address control unit 2207. The address control unit When it is supplied with a segment number, 2207 puts the base address of the segment in question in the address register 2209 from the address control unit 2207. Referring to Fig. 22B, in cycle C4, the address control unit 2207 output segment base address via the AND gate 2321, which is made transferable by the cycle C4 signal, is transferred into the segment base address register 2322.

The segment base address register 2322 is connected to one input of the adder 2325. The other input of the adder 2325 is connected to register 2323, which contains a value of 8 ,, This value of 8 corresponds to the shift from the beginning of the segment base of the maximum number of lines

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corresponding field, as can be found in the page header portion 1603 shown in Fig. 16a. The field relating to the maximum number of lines contains the value which indicates the maximum permissible line number to be used when reference is made to the specific page whose number is specified in the area page register 2285 _o In cycle C5, the output signal of adder 2325 , which represents the address of the field relating to the maximum number of lines, via the AND element 2324 and the OR element 2220, to which the AND element 2324 is connected, into the memory address register 2210 of the memory system 2213. The memory system 2213 initiates a memory read operation includes a determination that its memory address register 2210 has been loaded with a new value and that the read / write flip-flop 2212 is set to the zero state. As a result of the memory operation, memory access exceptions 2214 may occur. Such memory access exceptions cause the memory access exception flip-flop 2214 to be set and the exception handling mechanism to be activated. Otherwise, the memory operation is normally ended, and the memory operation completion flip-flop 2215 is set to the 1 state. With regard to FIG. 22D, it should be noted that the transition of the memory operation completion signal to the 1 state with the occurrence of the cycle C5 signal from the flip-flop 2436 which is in the 1 state makes the AND gate 2294 transferable, whereby the cycle C6 flip-flop 2437 is set to the 1 state, since the UHD element 2494 is connected to the set input of the cycle C6 flip-flop 2437. The transition of the memory operation completion flip-flop 2215 to the 1 state indicates that the addressed field relating to the maximum number of lines has been transferred from the memory system 2213 to the memory data register 2216. In cycle C6 the AND element 2300 is made transferable in order to transfer the field relating to the maximum number of lines from the memory data register 2216 to the Z register 2301 «

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Returning to the other measures caused by cycle C4, it can be seen from FIG. 22A that the area-page-line register 2281 controls the input of the shifting circuit 2294 via the AND gate 2293, which is controlled by the cycle C4 signal is made transferable _o The ¥ ert previously stored in the shift count register 2292 is also an input signal for the shift counter field input of the shift circuit 2294, via the AND gate 2326, which is enabled or made transferable by the cycle C4 signal . As shown in Fig. 22B, the output of the shift circuit 2294 is connected to the AND gate 2295 which is rendered transmissible by the cycle C5 signal. In cycle C5, the output signal of the shift circuit, which represents a line number received from the area-page line register 2281, is thus transferred to the W register 2296 via the AND gate 2295.

The Z register 2301 provides the one input signal for the Comparator 2297. The other input signal for the comparator 2297 is supplied by the W register 2296. If the comparator 2297 determines that the value in the W register is greater than or equal to the fourth in the Z register the W signal that is greater than or equal to the Z signal The signal is via the AND gate 2298 connected to the relevant comparator in conjunction with the cycle C7 signal setting the page format exception to be invalid Flip-flops 2299 ". When the invalid page format exception flip-flop 2299 is set to a 1 state, the exception handling mechanism is activated and the command is closed. If the comparator 2297 determines that the W value is less than the Z value, it becomes the condition that V is less than Z, the signal indicating the AND element 2332 is supplied and used for this purpose, the relevant logic element to make transferable.

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The W register 2296 is connected to one input of a multiplier circuit 2328. The register 2327, which contains the value 2, is at the other input of the cultivating circuit 2328. The multiplier circuit 2328 is a typical multiplier circuit implemented in hardware logic. Accordingly, the number of lines ¥ is multiplied by a factor of 2. In this case, this represents two 8-bit bytes of the storage system 2213. The "two bytes" form the length of a line offset field data word, such as 1604-6O3 in the line offset field 1602 according to FIG. 16a. The multiplication of the W line number by the size of the line offset field data word thus leads to the indexing of the correct line offset field data word for the line W in an address memory location. The output signal of the multiplier circuit 2328 is fed to the AND gate 2329, which is made transmittable by the cycle C6 signal. The AND element 2329 is in turn connected to an adding input of the adder 2330. The other input to adder 2330 is a value of 10 as stored in register 2331. The fourth of 10, the offset address in 8-bit bytes of the start of Zeilenversetzungsfelde.s 1602 is, as illustrated in Fig. 16a _o Accordingly .by the output signal of the adder 2330, the relative memory location of the row offset field data word the number of lines W addressed in the database page as shown in Fig. 16a and previously described. The output signal of the adder 2330 is fed to the AND gate 2332, which is made transferable by the cycle C7 ^ signal and by the signal output by the comparator 2297, which indicates that W is less than Z. The last-mentioned signal is a 1 logic signal when it has been determined that the number of lines W is less than the maximum number of lines Z from register Z 2301.

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The output of Ui ¹ JD-GIi ede s 2332, which represents the relative segment offset address of the line offset field data word of line number V /, is applied to adder 2333 as an input. The other input to adder 2333 is provided by segment base address register 2322. Accordingly, the output of adder 2333 represents the absolute address of the desired line offset field data advance of the line number or ". Line number ¥ represents. The output of the adder 2333 is guaranteed by the AND gate 2334, which is enabled or made transferable by the cycle C7 signal. The output signal of the AND gate 2334 is transferred to the memory address register 2210 via the OR gate 2220. When the memory system has determined that the memory address register 2210 has been reloaded and the read / write flip-flop 2212 is set to the null state, a memory read operation is initiated again. When memory access exceptions occur due to the memory read operation, the memory access exception flip-flop 2214 is set to the 1 state c and the exception handling mechanism is activated. Otherwise, the memory operation is normally completed and the memory operation completion flip-flop 2215 is set to the 1 state. From FIG. 22D it should be apparent that the AND gate 2495, which is connected to the set input of the cycle CB flip-flop 2440, is made capable of transmission by the cycle C7 and by the rise of the memory operation completion signal. In this way, cycle C8 is initiated. The rise of the memory operation complete signal also indicates that the desired offset field data word has been transferred to memory data register 2216.

The transmission of the D-field (or of the "D switch field"), as it is in field 1604 according to FIG. 16a is illustrated, of the displacement field data word above

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the AND gate 2302 is enabled to the comparator 230J, as can be seen from FIG. 22C. The other input signal for the comparator 2303 is provided by the register 2304, which contains the fourth zero. ¥ hen the comparator 2303 determines that the D-switching field of the line offset field data word ¥ equal to the value 0 is the number of lines, causing the coincidence signal output from the comparator 2303, the setting of the relevant non-use of a row except flip-flops 2305 _t where the agreement signal from the Comparator 2303 is supplied. Setting flip-flop 2305 will activate the exception handling mechanism and the instruction will be complete. Under other circumstances, the inequality signal of the comparator 2303 rises to a logic 1 value.

The output of AND gate 2302, which is the D toggle field of the line offset field data word of line number W is also applied to comparator 2306. The other input of the comparator 2306 controls the register 230Θ, which contains a value of 2. If the comparator 2306 determines that the D-toggle field is not the same 2, the inequality signal of the comparator 2306 rises to a 1-logic operation value. It should be evident that the inequality signal of the comparator 2303 and the Inequality signal of the comparator 2306 are fed to the AND gate 2309. If the D-toggle field is not equal to 0 or 2, then it must be 1 or 3; in either case, this is a line-deletion exception. Accordingly, the two Inequality signals of the comparators 2303 and 2306 are fed to the AND element 2309, which is transferable during the cycle C9 is made. This becomes the line erasure exception flip-flop 2310 is set when the D toggle field is 1 or 3. When the line erase exception flip-flop 2310 hits the 1 state is set, the exception handling mechanism is activated and the command completes. If the

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Comparator 2306 determines that the D toggle field of the line displacement field data word of the line number ¥ is equal to 2 , neither the line deletion exception flip-flop 2310 nor the exception flip-flop 2305 relating to the non-use of a line is set to the 1 state, which is why the command execution is continued .

The cycle C10 signal is used to do the line displacement part of the line offset field data word (see field 1603 in Fig. 16a) corresponding to line W via the AND gate 2312, which can be transmitted by cycle C10 is made to be transferred to the base register BR input register 2267. This is done through OR gate 2264 like this is shown in Fig. 22B. The line offset of the line offset field data word is placed in the CRA portion of the BR input register Transferred 2267, as indicated in Fig. 2 with 202. The cycle C10 signal is also used to enable AND gate 2311 to read segment number field 1625 from page descriptor register 2289 via the AND gate 2311 and the ODSR gate 2266 into the BR input register 2267 transfer. The segment number 1625 is transferred to the part STN, STE of the base register input register, as indicated in FIG. 2 in part 202.

Since the cycle C10 signal is another input signal of the OR gate 2270, which the AND gate 2271 is transferable controls, the BR field 1926 of the command buffer 2202 is an input signal for the BR area 2208 of the in cycle C10 Address control unit 2207 '. If the address control unit 2207 is supplied with a BR register number in its BR area 2208 and if the BR input register 2267 with a new value is loaded, the address control unit writes the value contained in the BR input register 2267 into the base register, the number of which is entered by a normal buffer write operation «Accordingly

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is the rsasis register whose basic register number is in the Befohlsfeld 1926 is given, now with the segmented Address value ε-.ktualisrt, which contains the address of the member data record which is indicated by the content of the index register corresponding to the base register BR.

From Fig. 22D it can be seen that following the cycle CIO flip flop 2442 either the cycle C11 flip-flop 2443 or the Cycle D11 flip-flop 2452 is set, depending on whether the recording pointer is type 2 or type 3 is present, which is indicated by the fact that either the C flip-flop 2243 in the 1 state or the D flip-flop 2242 in the 1 state is set. Setting the cycle C11 flip-flop 2443 is effected via the AND element 2496, and the setting of the cycle D11 flip-flop 2452 takes place via the AND gate 2497.

In cycle C11, the page-line code part of the area-page-line register becomes 2281 via the AND gate 2315, which is made transferable by the cycle C11 signal, transferred to the page-line part (field 1573 and field 1574 according to FIG. 15h) of the buffer data register 2318, as shown in Fig. 22A. If the pointer mode of type 5 is present, then the entire area-page-line register is opened in cycle D11 2281 via the AND gate 2314, which is made transferable by the cycle D11 signal, into the entire buffer data register 2318.

In each cycle of cycles C11 and D11, with regard to the fact that these two signals are input signals of the OR gate 2278, which is connected to the latch read / write flip-flop 2277, are the latch read / write flip-flop 2277 set to 1 This indicates that a cache write operation is to be initiated. the The address contained in the buffer address register 2275 is still the address of the index register at this point in time,

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in accordance with the BR-üasisregister number I926 in άθΠί instruction buffer for 2202 _G The buffer memory 2276 writes a new area-page line number in this index register after the cycle 011 signal or the cycle D1'i signal has caused the buffer memory Data register 2318 is to be loaded, and after the latch read / write flip-flop 2277 has been brought to the 1 state. The new area page line number is the address of the member record of the Ijuimnern record referenced by the base register BR of the instruction.

From? I <~. 22D it can be seen that cycle C11 flip-flop 2443 and the cycle D11 flip-flop 2452 with their outputs on the OD ^ -v element 2493 are included, which in turn is on the output side with the, set input of the cycle C12 flip-flop 2444 connected is. Accordingly, the cycle CI2 follows either the Cycle CI1 or cycle D11.

It can also be seen from FIG. 22C that the cycle C12 signal is applied to the bet input of the instruction completion flip-flop 2246 as a 1 signal. This indicates the completion of the database command relating to the retrieval of a user.

22D shows the detailed logic or combination circuit for the cycle counter control logic of the hardware implementation of the command relating to the search for a user illustrated in FIGS. 22A to 22C The cycles A0 to A5 with the flip-flops 2411 to 2416 represent the A cycle sequence that executes the part of the hardware operation that is defined for a pointer operation type 0, a virtual memory data set. The cycles BO to B4 with the

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Flip-flops 2421 to 242 ^ form the B cycle sequence which carries out the part of the hardware operation which is defined for a pointer drive type 1, a virtual memory data record. In certain cases, the A cycle sequences are used to perform operations for cycle B (type 1 of the pointer drive) because of the similarities between type 0 and type 1 operations to 2441 form the C cycle sequence which carries out the hardware operation which is specific for a pointer operation type 2, the database data record. ! / Le Cycles D1 to D11 with the flip-flops 2451 to 2452 form cii'3 D cycle sequences which the hardware operation executes, which is specific for a pointer mode of operation 3> the database data record. In several cases, C-cycles are shared by D-cycles, owing to the commonality between operations for records of the type 2 and type. 3

Each flip-flop as shown in FIG. 22D is a synchronous flip-flop. Accordingly, a clock system is used to trigger the logic state changes in each of these flip-flops. The clock signal is fed to the clock input of each of these flip-flops. The output signal of each of the flip-flops in this control counter logic is also fed to the respective reset input. Accordingly, setting a cycle flip-flop to the 1 state results in the flip-flop in question being reset to the 0 state one clock period later. In the event that the next following clock cycle depends on a different logic state than precisely on it, cs, 3 the previous clock cycle signal is a 1 signal, which is the case, for example, when the memory operation completion signal rises to a 1-fourth, the output signal is of the UKD-GIiedes, which brings about the link-like determination of the states in question - not the direct output signal - fed to the reset input for the previous clock cycle.

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The match signal from the comparator 2203 according to FIG. 22A is fed to the set input of the cycle 1 flip-flop 2201. After the MBZ field 1925 of the command relating to searching for a user has been checked to the effect that it has a value of 0, cycle 1 is initiated. The output of cycle 1 flip flop 2401 is with the set input of the cycle -2 flip-flops 2402. The output of the cycle 2 flip-flop 2402 is connected to the UKD gate 2481. The AND gate 2481 is switched to the transferable state by the memory operation complete flip-flop signal from the memory operation complete flip-flop 2215 As shown in Fig. 22B, accordingly, the output of UKD gate 2481 rises to a logic 1 value after the store operation is completed, at which point the command pertaining to retrieving a user is ready for the next The output of AND gate 2481 is fed to the set input of cycle 3 flip-flop 2403.

The output of the cycle 3 flip-flop 2403 "is connected to AND gate 2482. The AND gate 2482 is made transferable by the match signal from the comparator 2222 as shown in FIG Combination value when the comparator 2222 determines that the K field 1805 of the group descriptor which has been addressed by the command relating to the retrieval of a user is equal to 0. The output signal of the AND gate 2482 is the set input of cycle-4 -Flip-flops supplied to 2404.

The output of cycle 4 flip-flop 2404 is with the set input of cycle 5 flip-flop 2405. The outcome of the Cycle 5 flip-flops 2405 is connected to the set input of the cycle 6 flip-flop 2406 connected.

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The output of cycle 6 flip-flop 2406 is AND gate 2483 connected. The AND gate 2483 is activated by the memory operation completion signal from the memory operation completion flip-flop 2215 made transferable. The output of the MD element 2483 is connected to the set input of the cycle 7 flip-flop 2407 connected »

As described above, one of the following flip-flops will be set following cycle 7: AS2241, B32240, CS2239 or DS2258 (see Figure 22C). These signals initiate either the A-cycle sequence, the B-cycle sequence, the C-cycle sequence or the D-cycle sequence.

The cycle AO flip-flop 2411 is replaced by the AS flip-flop 2241 set. The output of the cycle AO flip-flop 2411 is with connected to the set input of cycle A1 flip-flop 2412. That Cycle BO flip-flop 2421 is set by BS flip-flop 2440. The output of the cycle BO flip-flop 2421 is with the Set input of cycle B1 flip-flop 2422 connected. The exits of the cycle A1 flip-flop 2412 and the cycle B1 flip-flop 2422 are connected to the OR gate 2484. Of the The output of the OR gate 2484 is in turn connected to the set input of the cycle A2 flip-flop 2413. Accordingly, it follows cycle A2 either to cycle A1 or to cycle B1

The output of cycle A2 flip-flop 2413 is with the AND gate 2485 connected. The AND gate 2485 is rendered transferable by the memory operation completion signal or released. The output of AND gate 2485 is connected to the set input of cycle A3 flip-flop 2414.

The output of cycle A3 flip-flop 2414 is with the two AND gates 2486 and 2487 connected. These two AND gates

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are used to select the continuation of either a Α cycle or a B cycle, depending on whether a type 0 or type 1 pointer operation is present. The two AND gates 2486 and 2487 also receive an additional enable input signal, the inequality signal supplied from the comparator 2260 according to FIG. 22C. This signal is used to indicate that the virtual memory data item has a D toggle field that is not 0 (data record deleted). The last enable input signal for the AND gate 2486 is the Α signal from the flip-flop 2245. If the pointer mode of type 0 is present and if the A signal 2245 is accordingly a 1 logic signal, the AND gate 2486 accordingly inputs 1 logic signal. The cycle A4 flip-flop 2415, to whose set input the AND gate 2486 is connected, is set to the 1 state. If the pointer mode of type 1 is present and if the B signal of the flip-flop 2244 is accordingly a 1-logic operation signal, the output signal of the AND element 2487 rises to a 1-logic operation value “Since the AND element 2487 has ⁴ ” Set input of cycle B4 flip-flop 2423 is connected, cycle B4 is initiated.

The outputs of cycle A4 flip-flop 2415 and cycle B4 flip-flop 2423 are connected to the OR gate 2488. Accordingly, the output of OR gate 2488 rises a 1-logic operation following either cycle A4 or following cycle B4. The output of the OR gate 2488 is connected to the set input of cycle A5 flip-flop 2416. Following cycle A5, the command completion flip-flop becomes 2246 must be set.

The two flip-flops CS2239 and DS2238 are with their outputs connected to the OR gate 2489. The OR gate 2489

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O5

is connected to the set input of the cycle CO flip-flop 2431.

The output of the cycle CO flip-flop 2431 is on the two AND gates 2490 and 2491 connected. These two AND gates are used to select the continuation of either the C-cycle sequence or the D-cycle sequence, namely depending on whether the type 2 or type 3 pointer operation is present. Accordingly, the second enable input becomes for the AND gate 2490 formed by the C signal from the flip-flop 2243 (see Fig. 22C). When the pointer operation of type 2 is present and if the C signal 2243 occurs accordingly with a 1-logic operation, the output signal rises of the AND gate 2490 to a 1 logic operation value. That Cycle C1 flip-flop 2432, at whose set input the AND gate 2490 is connected, it is set to the 1 state. When there is type 3 pointer operation and when accordingly the D signal of flip-flop 2242 occurs as a 1 logic signal, the output signal of the AND gate 2491 rises to a 1-logic operation value. Since the AND gate 2491 at the set input of cycle D1 flip-flop 2451 is connected the cycle D1 is initiated.

The outputs of cycle C1 flip-flop 2432 and cycle D1 flip-flop 2451 are connected to the OR gate 2492. Accordingly, the output of the OR gate 2492 rises a 1-logic operation value following either a cycle C1 or following a cycle D1. The exit of the OR gate 2492 is connected to the set input of the cycle C2 flip-flop 2433.

The output of cycle C2 flip-flop 2433 is to the AND gate 2493 connected. The AND gate 2493 is activated by the page setting completion signal from the page setting completion flip-flop 2287, as shown in Fig. 22A. The output of the AND gate 2493

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is connected to the set input of flip-flop C3 flip-flop 2434. The output of cycle C3 flip-flop 2434 is with the Set input of cycle C4 flip-flop 2435 connected. The output of the cycle C4 flip-flop 2435 is connected to the set input of the Cycle C5 flip-flops 2436 connected. The output of the cycle C5 flip-flop 2436 is connected to the AND gate 2494. The AND gate 2494 is activated by the memory operation completion signal of transferable to memory operation completion flip-flop 2215 made. The output of AND gate 2494 is connected to the set input of cycle C6 flip-flop 2437.

The output of cycle C6 flip-flop 2437 is connected to the set input of cycle C7A flip-flop 2438. The outcome of the Cycle C7A flip-flop 2438 is connected to the set input of the cycle C7 flip-flop 2439 connected.

The output of cycle C7 flip-flop 2439 is connected to AND gate 2495. The AND gate 2495 is activated by the memory operation complete signal released or made transferable. The output of the AND gate 2495 is with the set input of the cycle Ce flip-flop 2440 connected. The outcome of the Cycle C8 flip-flop 2440 is connected to the set input of the cycle C10 flip-flop 2442 connected.

The output of the cycle CIO flip-flop 2442 is with the two AND gates 2496 and 2497 connected. These two AND gates are used to select a continuation of either a C-cycle or a D-cycle, and that too depending on whether the type 2 or type 3 pointer operation is present. The second release signal for the AND gate 2496 is the C signal from flip-flop 2243. if type 2 pointer operation is present and accordingly the C signal from the flip-flop 2243 is a 1 logic signal,

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The output signal of the AND gate 2496 rises accordingly a 1-link value. It also turns the cycle C11 flip-flop 2443, to whose set input the AND element 2496 is connected, is set to the 1 logic state. If the Pointer operation of type 3 is present and if the D signal of the flip-flop 2242 is accordingly a 1-link signal, it rises the output signal of the AND gate 2497 to a 1 logic value at. Since the AND gate 2497 is connected to the set input of the cycle D11 flip-flop 2452, the Cycle D11 initiated.

The outputs of cycle C11 flip flop 2443 and cycle D11 flip flop 2452 are connected to the OR gate 2498. Accordingly, the output of the OR gate 2498 rises to one 1 logic operation value either following cycle C11 or following cycle D11. The output of the OR gate 2498 is connected to the set input of the cycle C12 flip-flop 2444. Following cycle C12, instruction completion flip-flop 2246 will be set, as in Figure 22C is illustrated.

The search series database command is a firmware / hardware command, in the case of successive checks of the respective database data record (see FIG. 15b) in one area (File), starting with the page and line number of the area given by an index register, until the next active record is determined. The database address of the specified in the range-page-line form The data record (see Fig. 15h) is then loaded into the index register. The search series command has that shown in FIG. 20A GROP format.

The firmware flow chart for the search serial command is illustrated in Figures 23A through 23C. At operation 3001

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the format of the command is checked according to the firmware flow chart. In operation 3003 it is checked whether or not the starting page of the referenced area is in memory. Then in the operation 3005 the page descriptor of the relevant page (see Fig.i6b) called. Through operations 3007 through 3009, the page number P is obtained from the reference index register. Furthermore, the line number or line number W is obtained from the reference index register, and then the line number ¥ is increased by 1. Accordingly the search for the next active data record begins with the data record following the data record followed by the Index register is shown or indicated. Operation 3010 calls the segment descriptor of the segment number, which corresponds to the area page number (the area number is the area number of the index register). the Match between a page and a segment is in the manner described above. By operation 3012 will get the maximum number of lines from the page header (see Fig. 16a).

FIG. 23A is discussed in greater detail below. First, in operation 3001, the MBZ fields I9OI and 1903 checked to see if they are 0. This check for 0 is carried out by the fact that the command from the command calling unit (see Fig. 13a, IFU1318) is transferred to a register in the arithmetic unit 1317. If the If the hardware check determines that the MBA fields are not zero, the firmware branches to exception handling as illustrated by operation 3002 in Figure 23A. This exception is called a Forbidden Format Field Exception designated. If the MBZ fields are 0, the firmware proceeds to operation 3003 according to FIG the area and the page are transferred from the index register in the intermediate storage unit 1315 to the arithmetic unit 1317 will. The reference index register is a register

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whose number is given by the base register BR number (Box 1902 of Figure 20A). A check is made by the side mount firmware subroutine shown in FIG to determine whether the page corresponds to the area page whose number is contained in the main memory. If the Page is not in memory, a page-through exception 3004 occurs. If the If the page is in main memory, operation 3005 calls the page descriptor of the pages. the Memory access exceptions 3006, such as the "out of main memory" exception, may result from this main memory call appear.

At operation 3007, the page number contained in the index register is given its number by BR is transferred to an intermediate register P, which is contained in the arithmetic unit 1317. Which by the number of bits of this Given length is equal to the shift count field 1623, as shown in Figure 16b. At operation 3008 the number of lines is entered by BR into an intermediate register W in the arithmetic unit 1317. Which by the number of bits The length given this number of lines is equal to 22 minus the shift count field 1623. In operation 3009, the The main adder of the arithmetic unit is used to increase the content of the line number register W by 1. During the operation 3010 the segment descriptor of the SEG number obtained from the page descriptor is called (see the field 1625 in Fig. 16b). As a result of this memory call, memory access exceptions 3011 can occur. In operation 3012, the maximum number of lines is retrieved from the page header I6OI using the base address obtained from the segment descriptor called in operation 3010. The maximum called The number of lines is stored in an intermediate register Z in the arithmetic unit. As a result of this main memory call

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Memory access exceptions 3013 can occur. On the In operation 3012, the hardware / firmware branches to 3020 of Figure 23B.

According to FIG. 23B, the line number W which addresses the data record is checked to determine whether it is active State. A comparison is made to determine whether the number in question is greater than the maximum number of lines Z is. If this is the case, the firmware branches out to operation 3022 at which determines whether this is the last page of the range. If it is determined in operation 3022 that the the current page is the last page of the area, the command has not been successful with regard to that Finding an active data set; an exception 3023 relating to the last data record is thus reported. If that is If the present page is not the last page, the firmware proceeds to operation 3024 and operation 3025 further, according to which the content in the page number P register is increased by and according to which the line number is set to zero. Operation 3026 is then performed which checks the new page to see if it is in main memory is available. If it is in main memory, the firmware proceeds to operation 3028, according to which the page descriptor of the new page P is called. The firmware then branches to the 23C, where the last line of the new page is checked for the presence of the active state.

Referring now to Fig. 23B. In operation 3021, the arithmetic unit main adder is used in the comparison, operating state is set, and the content of the intermediate register W is compared with the content of the intermediate register Z. if the number of lines W is not greater than the maximum number of lines Z or

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- 14O -

equals these lines Z, the firmware branches to FIG. 23C, namely to operation 3030. If the If the number of lines W is greater than the maximum number of lines Z or equal to this number of lines Z, the firmware will branch to operation 3022 to determine whether the current page P is the last page of the range. at of operation 3022 becomes the last page indicator 1626 of the page descriptor called in operation 3005 checked. If this indicator is found to be equal to 1, the firmware is executing a Branch to exception handling, in which an exception 3023 relating to the last record is recorded.

If the indicator relating to the last page has been determined by the firmware to be 0, leads the firmware branches out to its operation 3024, according to which the content of the page number register P is incremented by one in the main adder of the arithmetic unit. Operation 3025 is then performed, according to which the hardware / firmware introduces an O value into the line number register W. Then operation 3026 is performed in which the paging firmware subroutine (see Fig. 17) is used to check whether the described by the area page Page exists in main memory. If the relevant page is not available in the main memory, so an exception 3027 relating to page-by-page execution occurs. If the page is in main memory, operation 3028 is performed, according to which the page descriptor for page P is called from main memory or is picked up. As a result of this main memory call, memory access exceptions 3029 may occur. On the Following operation 3028, the firmware branches to operation 3030, as illustrated in Figure 23C is.

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According to FIG. 23C, the actual check is carried out with respect to the active state of the line whose database address is given by the area-page-line number, whose number is actually contained in the arithmetic unit, intaelches the number in question was transferred from the index register in the buffer memory. The page number is in the temporary register P housed. The line number is in the intermediate register W. The line field element (see the Field 1610 in FIG. 16a) is called in operation 3031. In operation 3031, a check is made as to whether this line is in the active state or not. This check is carried out in that the D toggle field (see field 1604 in FIG. 16a) of the line displacement field element 1603 is checked. If the D-toggle box equals Is 0, 1, or 3, the record is not in the active state and the firmware proceeds to operation 3034 further, in which the number of lines ¥ is increased by 1 and in which the firmware branches to operation 3021 according to FIG 23B. This is used in preparation for the examination of the next record (line) in the area. If the D-toggle field is equal to 2, the record (line) is in the active state and the command can now be completed successfully. Operations 3036 and 3037 load the address of the active state Dataset. At operation 3036, the base register BR is assigned the segmented address of the record loaded. At operation 3037 the index register is loaded with the page and line W numbers. The area number in the index register remains the same. The command then ends in operation 3038.

Referring now to Fig. 21C. Starting with operation 3031 the firmware calls the 16-bit line

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displacement field element 1602 at an address that by the segment base address of the page plus the length of the page header part 16O2 (81 bits) plus the number of lines ¥ times 16 bits is given. These 16 bits represent the length of a single line displacement field element. As a result of this Memory access exceptions 3032 may occur during memory calls.

At operation 3033, the D toggle field 1604 becomes the offset line field element transferred to a register of the arithmetic unit 1317. Operation 3033 now becomes the D toggle button checked, which is contained in the arithmetic unit to determine whether it is equal to 0, 1 or 3. These reviews are carried out in an adder in the arithmetic unit. If the D toggle button is found to have one of these values the firmware branches to operation 3034, according to which the intermediate register W is increased by 1 in its content is increased. The main adder of the arithmetic unit is used to increase the register content. On the In the direction of operation .3034, the firmware branches to operation 3020 in accordance with FIG. 23B.

If the firmware detects that the D-toggle pad has a Has a value of 2, which is the active state, the firmware branches to operation 3036 in which the SEG number 1625 of the one called in operation 3005 Page descriptor is transferred to the base register BR, the number of which is given in the command format, field 1902 is. The shift of the SEG number from the page descriptor to the base register (which is in the address control unit 1319 is included) takes place under the firmware control. In the Operation 3036 becomes the displacement portion of the displacement field element 1603 also transferred to the SRA part of the base register BR. The segment number is in the bit positions 4 to 15 of the base register are transferred. The dislocation

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is transferred to bit positions 18 Ms 31 of the base register. Following operation 3036, the firmware branches to operation 3037 in which the intermediate register P is transferred to the index register, the number of which is given in the base register field BR1902 of the command format, The line number intermediate register W is also transferred to the index register. The number of bits in the page and line numbers are also determined from the shift count field 1623 of the page descriptor called in operation 3005 has been (the bits of the page number are equal to the shift count, the bits of the line number or line number are equal to 22 minus the shift count). On the Following operation 3037, the firmware branches to operation 3038, where the command completes and in which control is transferred to the next command.

Referring now to FIGS. 24A and 24B, the hardware is shown in a block diagram. required to execute the serial search database command. In Fig. 25 is shown the control logic that is used for Follow-up transmissions and operations on the data is used in the course of executing the series search command. the The control logic shown in Figure 25 is often referred to as cycle counter logic.

For the purpose of facilitating an understanding of the hardware logic illustrated in FIGS. 24A and 24B, let us say Operation of the control logic shown in Fig. 25 is briefly summarized as follows. First of all it should be evident that the cycle 0 through cycle 13 flip-flops 3301 through 3319 a row, of 14 consecutive time periods. B1 through B3 cycles 3320 through 3322 is a 3 cycle control sequence set that can be repeated. At the end of the B cycles

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cycle no. 8 of the main cycle sequence is repeated. The C1-biw C5 cycles 3330 through 3334 lay a second series of Sequences that can also be executed repeatedly. At the end of the C cycles, cycle 13 of the main sequence is initiated. D1 through D3 cycles 3341 through 3343 define a third group of sequences. At the end of the D cycles, that will be Command completion flip-flop 3298 is set, ending execution of the serial search command.

Referring now to FIG. 24A, a closer look is given. On the inclusion of a serial sacn command, as generated by the serial search command detector 3201 is displayed, the command is temporarily stored in the command buffer 3202. The command buffer is located in the command calling unit 1318 of the central unit 104. As already mentioned above, the serial search command supplied to the command buffer 3202 is in the GROP format as shown in Fig. 20A. The MBZ field 1911 is directly linked to the O bit 3204 by means of the comparator 3203 compared. If the comparator 3203 outputs an inequality signal, an invalid format field exception has been determined and the forbidden format field flip-flop 3205 is set. This activates the exception handling mechanism causes. The execution of the serial search command is then completed. When the comparator 3203 indicates a match, execution of the serial search command continues as described below will.

It should be noted that the output from the comparator 3203 Agreement signal that has a 1 linkage value increases when it is determined that the MBZ field 1911 is equal to 0, as an input signal to the set input of the cycle 0 flip-flop 3301 is fed. Accordingly, finding a match in the comparison in question solves the

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Main cycle sequence with cycles 0 to 13.

The BR field 1912 of the instruction buffer is connected to the AND gate 3206, which is made transferable by the cycle 0 signal. Accordingly, in cycle 0, the BR field is entered into the rightmost three bits of the buffer address register 3281. With regard to AND gate 3293, which was also controlled by the cycle 0 signal to be transferable, it should be noted that in cycle 0 a 1-bit from the 1-bit flip-flop 3282 also into the leftmost bit position of the buffer Address register 3281 is entered. Latch 3283 operates in the typical manner of known buffers. If the temporary storage address register 3281 is loaded with an address, the content of the relevant address is accordingly read out into the temporary storage data register 3217. In this case, the actual value read from the latch 3283 will be the index register, the number of which is given by the BR base register number from the instruction buffer. 3202. This index register contains an area page line number as described above .

In cycle 1, AND gate 3218 is made transferable, thereby transferring the contents of the buffer data register via the OR gate 3219, to which the AND gate 3218 is connected, into the page fixing mechanism 3225 is enabled. The operation of the paging mechanism has already been described above; a hardware implementation for the mechanism in question is shown in FIG. Activation of the paging mechanism includes setting the activation paging flip-flop 3223, which is caused by the cycle 1 signal via the OR gate 3285. Charging also takes place of the area page register 3226 in which the content of the

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Buffer data register is loaded. The activation paging flip-flop 3223 corresponds to flip-flop 1851 shown in FIG corresponds to the register 1852 in FIG. 18. As described above, the execution of the page setting mechanism 3225 can be Exceptions to the page-by-page implementation. In this case the exception flip-flop 3224 is set and the exception handling mechanism is set is activated. Otherwise, the page descriptor which is the one in the area-page register specified page number or page number is loaded into the page descriptor register 3222 (which corresponds to the register 1877 according to FIG. 18). The page setting completion flip-flop 3228 is set (this flip-flop corresponds to the Flip-flop 1897 according to FIG. 18). With reference to Fig. 25, it should be noted that the page setting completion flip-flop, that in the 1 state when there is a 1 link signal is set in cycle 1, the AND gate 3303 makes transferable, which in turn, cycle 2 of the Main cycle sequence initiates. The paging complete flip-flop remains in the 1 state until the paging mechanism is re-activated by setting the activation page lock flip-flop 3223 and loading area page register 3226.

The format of the page descriptor loaded into the page descriptor register 3227 is shown in Figure 16b. By the The AND element 3229 is capable of transmission for a cycle 2 signal which transfers the shift field count field 1623 of the page descriptor to the shift count register 3230. This shift counter setting is used to determine the area-page line number from the intermediate register 3217 and the line number part of the relevant number or number and to load into the W register 3249. During cycle 2, AND gate 3221 transmits,

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which has also been enabled by the cycle 2 signal is, the area portion 1572 of the temporary storage data register 3217 into the area register 3222 in which the relevant area part is saved for later use.

The value stored in the shift count register 3230 is subtracted from a value 22 stored in the register 3235 is. This subtraction is done in a subtracting circuit 3236. This new value, which is the number of bits in represents the line number, is from the output of the subtraction circuit 3236 via the AND gate 3237, which by the Cycle 3 is made transferable, transferred to the OR gate 3239, which in turn uses the Input signal for the shift circuit 3243 forms. aside from that the contents of the buffer data register 3217 via the AND gate 3241, which is determined by the cycle is made transferable, and the OR gate 3242 is input to the shifting circuit 3243 in order to be shifted will. The output of the shift circuit is with the AND gate 3245 (Fig. 24B), which is made transmittable by cycle 4. The output signal is thus in cycle 4 the shift circuit, which represents the number of lines - those from the index register addressed by the command has been received - transferred via the OR gate 3248 into the W register 3249, in which the relevant Number is saved for later use.

In cycle 5, the value stored in shift count register 3230 is stored Value obtained from the 1623 page descriptor field was, via the AND gate 3238, which is made transferable by the cycle, and the OR gate 3239 to the shift count input of the shift circuit 3243.

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The content of the buffer data register 3217 is transferred to the shift value input _{c of} the shift circuit 3243 via the OR element 3240, which is made transferable by cycle 5, and the OR element 3242. In cycle 6, the shifted output signal of the shift circuit 3243 vrelches represents the page number which has been obtained from the index register which was addressed by the instruction, via the AND gate 3244 and the OR gate 3246 to the P register 3247. The page number stored in the P register 3247 will be used later.

The W line number in the W register 3249 is fed to one input of the adder inputs of the adder 3253. The flip-flop 3252, which contains a value of 1, is connected to the other input of the adder 3253. The output of the adder 3253 represents the number of lines, which is increased by ¹ ^ m 1. This output signal is fed to AND gate 3254, which is made transferable by cycle 7. Accordingly, in cycle 7, the number of lines Vi increased by 1 is transmitted via the AND element 3254 to the OR element 3256, to which the AND element 3254 is connected, and fed back to the OR element 3248. The output of the OR gate 3248 is in turn connected to the W register 3249, in which the increased value of the number of lines is stored.

In cycle number 8, the segment number field becomes 1625 of the page descriptor register 3227 via the AND gate 3230, which is made transferable by cycle 8, into the address control unit 3207 transferred. When a segment number or segment number is supplied to the address control unit, the Base address of the segment descriptor of the relevant segment is read from the address control unit into the address register 3209. The segment base address contained in the address register 3209 is transmitted via the AND gate 3266, which is determined by the

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Cycle 9 signal is made transmittable. The output signal of AND gate 3236 is in turn entered via OR gate 3267 into memory address register 3210 of the memory system 3213 transferred. It should be noted that the Serial search command detector 3201 is also connected to the inverting AND gate 3211, which in turn is connected to connected to memory system read / write flip-flop 3212 is. The signal emitted by the series search command detector leads, in the event that it is a 1-link signal, to that the output signal of the logic element 3211 is an O logic signal is. As a result, the read / write flip-flop 3212 is set to the 0 state. If the memory ^ system 3213 has determined that memory address register 3210 has been loaded and that read / write flip-flop 3212 is set in the O link state, it becomes a memory read operation initiated. As a result of a store operation, look-up access exceptions 3214 may occur. if such exceptions occur, the memory access exception flip-flop 3214 is set to the logic 1 state. The exception handling mechanism is activated. Otherwise, the memory operation is normally ended and the memory operation completion flip-flop 3215 goes into the 1-link state set. On the transition of the memory operation flip-flop 3215 to the 1 logic state, those from the Memory system 3213 has been transferred to the memory data register 3216. The transition of the storage operation completion flip-flop 3215 in the 1 logic state leads to the AND gate 3268 being made transferable will. Thereby, the segment base address read out from the memory system is set in the segment base address register 3284 in which the relevant value is saved.

In cycle 9, the AND gate 3231 is also made transferable, which the display signal 1626 relating to the last

GOPY

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Page from the page descriptor register 3227 to store the value of the display signal relating to the last page in the flip-flop 3232.

With regard to Fig. 25, it should be noted that the Cycle 10 flip-flop 3314 is set via AND gate 3318, that by the cycle 9 signal and the memory operation complete signal is made transferable.

The segment base address register 3284 is one of the adder inputs of adder 3270 connected. At the other input of the adder 3270 is the register 3269, which contains the value contains. The output of the adder 3270 is connected to the AND gate 3271, which can be transmitted by the cycle 11 signal is made. The output of AND gate 3271 is transferred to the OR gate 3267, which in turn controls the memory address register 3210. The thus in the Address stored in memory address register 3210 represents the address of the line field size field in the page header of the Area page address from buffer data register 3217. This is a page header 1702 as shown in FIG 16a is shown. Accordingly, the storage system 3213, activated by loading memory address register 3210 will read the line field size from the storage system. As a result of the memory operation, memory access exceptions can occur 3214 occur. When such exceptions occur, the memory access exception flip-flop 3214 goes to the logic 1 state set. The exception handling mechanism is activated. Otherwise, the memory operation becomes normal terminated, and the memory operation completion flip-flop 3215 is again set to the logic 1 state. With regard to 25, it should be noted that AND gate 3216 is activated by the cycle 11 signal and by the memory operation complete signal is made transferable to accordingly

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to set the cycle 12 flif plop 3317. So begins the Cycle 12 after the storage operation has been completed and indicates the transfer of the line field size via AND gate 3274 the Z register 3275 free.

The Z register 3275 provides an input signal for the comparator 3276. The other input signal for the comparator

3276 supplies the W register 3249. If the comparator 3276 detects that the value in the W register is greater than or equal to the value in the Z register, a Signa! indicating that W is greater than or equal to Z. This signal, which is fed to the AND gate 3277, is enables the setting of B-cycle flip-flop 3278. The AND element

3277 is controlled to be transferable by the cycle-13 signal. The B-cycle flip-flop 3278, which is set to the logic 1 state, in turn routes the B-cycle sequences B1 to B3 via the flip-flops 3320 to 3322 according to FIG.

If the comparator 3276 determines that the W value in the ¥ register 3249 is less than the Z value in the Z register 3275, a signal is output which indicates that W is less than Z. This signal, which is fed to AND gate 3278 , together with the cycle 13 signal, sets the C cycle flip-flops 3279 free. Setting the C cycle flip-flop 3279 initiates C cycle C1 through G5 like this 25 can be seen on the basis of flip-flops 3330 to 3334.

Consideration of FIGS. 24A and 24B reveals the measures that result from the B cycles. It should it can be seen that the AND gate 3233 is controlled transferable by the cycle 31, which the value in is stored in the flip-flop 3232 which is its indication regarding of the last page 'saves to the set input of the Concerning an exception regarding the last record

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Flip-flops 3234 is transmitted. So if that of the Page descriptor register 3227 with regard to the display element relating to the last page is a 1-link signal, the exception flip-flop relating to the last data record is activated 3234 is set and the exception handling mechanism is activated. If the one on the last page Display value is an O-logic signal, occurs does not raise the exception relating to the last record.

If the exceptional condition relating to the last data record does not exist, cycle B2 becomes the AND element 3250 made transferable, creating an O value of the Register 3251 via the OR gate 3248, to which the AND gate 3250 is connected, to the W register 3249 transferred ^ As a result of cycle B2, W register 3249 is reset to 0. Cycle B2 becomes also made the AND gate 3257 transferable. It should be noted that the P register 47 with the one Adder input of the adder inputs of adder 3258 connected is. A 1 value, which is stored in flip-flop 3259, is fed to the other input of adder 3258. The output of adder 3258 becomes the AND gate 3257, which is transferrably controlled by cycle B2. The relevant signal is sent via the OR gate 3246 transferred to P-Register 3247. As a result of cycle B2, a P value plus 1 is thus entered in the P register 3247 loaded.

In cycle B3, the new value of P-register 3247 with the Contents of the area register 3222 linked or combined via the AND gate 3220 in order to be included in the page definition mechanism 3225 to be loaded. The AND gate 3220 is accordingly connected to the OR gate 3219, which in turn is connected to the area page register 3226 of the page setting mechanism 3225. The cycle B3 signal

7 0 9 8 10 AO 9 9 3

is also used to activate the paging flip-flop 3223 to be set via the OR gate 3285.

As described above, the operation of the page setting mechanism 3225 could cause a paging exception to occur. is If so, the relevant exception flip-flop 3224 is set and the exception handling mechanism is activated. Otherwise, the page descriptor becomes as shown in Fig. 16b is the page whose number is contained in the area page register 3226 into the page descriptor register 3227 is loaded and the page setting complete flip-flop 3228 goes into the logic 1 state on End of the operation of the mechanism set. Activation of the paging mechanism causes the paging complete flip-flop 3228 transferred to the O state until the processes of the relevant mechanism have been completed will. From Fig. 25 it should be seen that the cycle 8 flip-flop 3312 via the OR gate 3210 can be set if the cycle B3 signal occurs as a 1 logic signal and when the page setting completion signal occurs again with a 1 linkage value. The reason for this lies in that the output of the OR gate 3210 is connected to the AND gate 3311, which is thereby capable of transmission the paging completion signal is made to rise. Accordingly, at the end of the cycle 8 flip-flop 3312 becomes Activity of the paging mechanism set back to the 1-link state. Cycles 8, 9, 10, 11, 12 and 13 are executed again in the manner previously described.

The following are the execution measures of the C-cycles C1 through C5, which are initiated by setting the C-cycle flip-flop 3279. It should be evident

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be that the AND gate 3262 is transferable in cycle C1 is made as illustrated in Fig. 24B. The other input to AND gate 3262 is the output of the multiplier circuit 3261. One of the inputs to the multiplier circuit 3261 is the content of the W register 3249. At the other input of the multiplier circuit 3261 is the register 3260, which contains a value of 2. Accordingly, the number of lines ¥ is multiplied by two-, which in this case represents 2Bytes of the memory system 3213. The two bytes form the length of the line offset data word, as 1604-1603, in the line offset field 1602 according to Figure 16a. The multiplication of the W-line number with the The size of the line offset data word thus leads to an indexing of an address which contains the correct line offset data word for the W line. The output of the multiplier circuit 3261 is fed to the AND gate 3262 which is made transmittable by the cycle C1 signal. The AND gate 3262 is in turn with a connected to the adder inputs of adder 3263. The other A value of 10, which is stored in register 3264, is fed to the input of adder 3263. The value of 10 represents represents the offset address, in bytes, of the beginning of the line offset field 1602, as shown in Figure 16a. Accordingly, the output of adder 3263 addresses the relative storage location of the line offset data word of the line number W in the relevant page, as shown in FIG. 16a and as previously described. The output of the adder 3263 is connected to the AND gate 3265, which is made transferable by cycle C2. The output of AND gate 3265 is the input for a further adder 3286. At the other input of the adder 3286 is the segment base address register 3284. Accordingly the output of adder 3286 represents the absolute Address of the required line offset field data word

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the line number W. The output of the adder 3286 is connected to the AND gate 3287, which can be transmitted by the cycle C3 is made. The output signal of the AND gate 3287 is transferred to the memory address register via the OR gate 3267 3210 transferred. When the memory system 3213 has determined that the memory address register 3210 has been reloaded and that the read / write flip-flop 3212 is in the O logic state is set, a memory read operation is initiated again. As a result of the memory operation you can Memory access exceptions 3214 occur. When such exceptions occur, the store access exception flip-flop becomes 3214 set to the 1 link state, and the exception handling mechanism is activated. Otherwise, the memory operation is normally ended and the memory operation completion flip-flop 3215 is set to the logical 1 state, indicating that the desired offset field data word has been transferred to the storage data register 3216. From Fig. 25 it is seen that the cycle C3 and the rise of the store complete signal enables the set input to the cycle C4 flip-flop 3333 rises to a 1 logic operation value, whereby cycle C4 is initiated.

The cycle C4 enables the transfer of the D-switchover field, of the field 1604 of Figure 16a, the line offset field data word via the AND gate 3272 to the comparator 3230. The register is located at the other input of the comparator 3273 3288, which contains a value of 2.

When comparator 3273 determines that the D toggle button of the line offset field word of the W line number is not equals 2, the inequality signal together with the cycle C5 signal makes the AND gate 3255 transferable, to get the output of adder 3253 (that is the

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ταπί 1 increased number of lines in the register ¥ 3249) over that OR gate 3256 and the OR gate 3248 (at which the OR gate 3256 is connected). The OR gate 3248 is in turn connected to register W3249. Accordingly, the content of register W 3249 is increased by 1 again. As can be seen from Fig. 25, the change of state causes of cycle C5 flip-flop 3334 activates cycle 13 flip-flop 3319. This is done with consideration that the output of cycle C5 flip-flop 3334 via the OR gate 3318 with the set input of the cycle C13 flip-flop 5319 is connected.

If the comparator 3273 determines that the D toggle field is equal to 2, the comparator asserts the match signal 3273 the D-cycle flip-flop 3288. The D-cycle signal activates the D-cycle sequence of cycles D1 to D3.

In cycle D1, the offset portion of the offset line field data word becomes (see field 1603 in Fig. 16a) accordingly of the line W via the AND gate 3289, which is made transferable by the cycle D1 signal, into the Base register BR input register 3292 transferred. This displacement field of the line displacement field data word becomes transferred to the offset field of the base register input register 3292, as indicated at 202 in FIG. In addition, the segment number field 1625 of the page descriptor 3227 via the AND gate 3291, through the cycle D1 signal is made transferable, transferred to the segment portion of the BR input register 3292. the Segment number is transferred to the STN, STE field of the base register, as illustrated in field 202 of FIG is. Finally, as part of cycle D1, the BR field of instruction buffer 3202 is accessed via AND gate 3290, the is made transferable by the cycle D1, transferred to the BR part 3208 of the address control unit 3207.

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If the address control unit 3207 has a BR base register number is supplied in its BR area 3208 and when the BR input register 3292 is loaded with a new value, the address control unit writes the value contained in the BR input register 3292 into the base register, and by a normal cache write operation.

It should be seen that the read / write flip-flop 3295 of the auxiliary memory 3283 initially in the O-state under display a read operation is set by the action of the detector 3201 serving to detect a serial search command which is connected to the inverting AND gate 3294. Since the for the determination of a series search

a "1" signal

befehles provided detector 3201 / emits, the output signal drops of the inverting AND gate 3294 to an O logic value, which is entered via the OR gate 3299 into the Buffer read / write flip-flop 3295 transferred as a 0 value will. In cycle D2, however, the cycle D2 signal, which is a 1 signal, becomes the OR gate via the AND gate 3 ^ 01 3299 and into the latch read / write flip-flop 3295 is transferred as a 1 value, causing a read / write operation is shown. In addition, in cycle D2, the content of the W register 3249 becomes the line number part 1574 of the area page line number transferred in the buffer data register 3217 via the AND gate 3297, which is carried out by the cycle D2 signal is made transmittable. In addition, the content of the P register 3247 becomes the page number part 1573 of the area page line number in the temporary storage data register 3217 via the AND gate 3296, which is made transferable in cycle D2. The area number part 1572 of the area page line number of the Latch data register 3217 has remained unchanged since the latch was first during cycle 0 was read out. In addition, the address is in the intermediate

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Memory Address Register 3281 is the address of the index register, corresponding to the BR base register number in the Instruction buffer 3202. The buffer memory 3283 writes the new area page line number into this index register, after the cycle D2 signal loads the latch data register 3217 and setting the cache read / write flip-flop 3295 in the 1-link state.

The cycle D3 signal becomes the set input of the command completion flip-flop 3298 supplied. Accordingly, the cycle D3 signal sets the command completion flip-flop to the logic 1 state. Through this the end of the recurring search database command is displayed.

Referring to Figure 25, the detailed logic circuit for the cycle counter control logic is that shown in Figures 24A and 24B Hardware implementation of the serial search command illustrated. The flip-flops 3304 bis provided for cycles 0 to 13 3319 define the main cycle sequence of the control logic. The flip-flops 3320 to 3322 provided for cycles B1 to B3 define the B cycle sequence. The ones provided for cycles C1 to C5 Flip-flops 3330 to 3334 define the C cycle sequence. The flip-flops 3341 to 3343 provided for cycles D1 to D3 define the D cycle sequence. Each in Fig. 25 The flip-flop shown is a synchronous flip-flop. Accordingly a clock system is used to trigger the logic state changes in each of these flip-flops. In which Clock system, a clock signal is fed to the clock input of the respective flip-flop. With each flip-flop the flip-flops this one Control cycle counter logic, the output signal is also fed to the respective reset input. Accordingly a cycle flip-flop set in the 1 state becomes a Clock period later reset to the 0 state. The result of this type of flip-flop connection is occurrence a series of consecutive cycle pulses.

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The agreement signal supplied by the comparator 3203 in accordance with FIG. 24A becomes the set input of the cycle-O flip-flop 3301 supplied. After the MBZ field 1911 of the serial search command checked for the value 0 has been, cycle 0 is accordingly initiated. The output of the cycle-O flip-flop 3301 is at the set input of cycle 1 flip-flop 3302 is connected. The exit of cycle 1 flip-flop 3302 is connected to AND gate 3303. The AND gate 3303 is activated by the page setting completion flip-flop signal released or made transferable by the page lock mechanism 3225. Accordingly, the output signal of the AND gate 3303 rises to a logic 1 value when the page fixing mechanism has finished his operation. At this point the serial search command is ready to move on to the next step to pass over its execution. The output of the AND gate

3303 is directly connected to the set input of the cycle 2 flip-flop

3304 connected. The output of cycle 2 flip-flop 3304 is connected to the set input of cycle 3 flip-flop 3303. The output of cycle 3 flip-flop 3305 is connected to the set input of cycle 4 flip-flop 3306. The outcome of the Cycle 4 flip-flop 3306 is connected to the set input of the cycle 5 flip-flop 3307 connected. The output of the cycle 5 flip-flop 3307 is with the set input of the cycle 6 flip-flop 3308 connected. The output of cycle 6 flip-flop 3308 is connected to the set input of cycle 7 flip-flop 3309.

The output of cycle 7 flip-flop 3309 is OR gate 3310 connected. The output of the cycle B3 stage 3322 is connected to the other input of the OR gate 3310. Accordingly, the next sequence after the cycle can either be by the cycle 7 signal or by the cycle B3 signal activated .. The output of the OR gate 3310 is connected to the AND gate 3311. This AND element becomes

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by the page setting completion signal from the page setting completion flip-flop 3228 made transferable. The AND gate 3311 is at the set input of the cycle 8 flip-flop 3312 connected. The output of the cycle 8 flip-flop 3312 is connected to the set input of cycle 9 flip-flop 3313. The output of cycle 9 flip-flop 3313 is on connected to AND gate 3318. This AND gate is activated by the memory operation completion signal from the memory operation completion flip-flop 3215 made transferable. After cycle 9 and after the store operation is complete the output signal of the AND element 3318 thus rises to a 1-logic operation value. Since the AND gate 3318 at the set input of cycle 10 flip-flop 3314 is connected, follows then cycle 10. The output of cycle 10 flip-flop 3314 is connected to the set input of cycle 11 flip-flop 3315. The output of cycle 11 flip-flop 3315 is at the AND gate 3316 connected. This AND gate is also activated by the memory operation completion signal from the memory operation completion flip-flop 3215 made transferable or released, which is in a 1-link state proceeds to the completion of the operations in the storage system. The output of the AND gate 3316 is at the set input of the Cycle 12 flip-flops 3317 connected.

The output of cycle 12 flip-flop 3317 is at the OR gate 3318 connected. The output of the cycle C5 flip-flop 3334 is also connected to the OR gate 3318. This OR gate 3318 is at the set input of the cycle 13 flip-flop 3319 connected.

The B cycle sequence is activated by the B cycle flip-flop 3278, whose output is connected to the set input of cycle B flip-flop 3320. The output of cycle B1 flip-flop 3320 is at the set input of cycle B2 flip-flop 3321

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connected. The output of cycle B2 flip-flop 3321 is connected to the set input of the cycle B3 flip-flop 3322. As previously stated, the output of the cycle is B3 flip-flop 3322 also connected to the OR gate 3310, which is connected via the AND gate 3311 to the set input of the cycle 8 flip-flop 3312 is connected.

The C cycle sequence is set by the C cycle flip-flop 3379 activated whose output is connected to the set input of cycle C1 flip-flop 3330. The output of the C1 flip-flop 3330 is connected to the set input of cycle C2 flip-flop 3331. The output of the cycle C2 flip-flop 3331 is at the set input of cycle C3 flip-flop 3332 is connected. The outcome of the Cycle C3 flip-flop 3332 is connected to AND gate 3340. The AND gate 3340 is activated by the memory operation completion signal enabled by memory operation complete flip-flop 3215 or made transferable. The outcome of the AND gate 3340 is connected to the set input of cycle C4 flip-flop 3333. The output of cycle C4 flip-flop 3333 is connected to the set input of cycle C5 flip-flop 3334. As has already been stated above, is the output of cycle C5 flip-flop 3334 on the OR gate 3318 connected, which in turn is connected to the set input of the cycle 13 flip-flop 3319.

The D-cycle sequence is generated by the D-cycle flip-flop 3288 activated, which is activated at the set input of the cycle D1 flip-flop 3341 connected. The output of cycle D1 flip-flop 3341 is connected to the set input of the cycle D2 flip-flop 3342. The output of the cycle D2 flip-flop 3342 is at the set input of the cycle D3 flip-flop 3343 is connected.

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The record check database ^ command is in firmware / hardware executed machine instruction which calls a data record descriptor (see Fig. 19b) which has a related data record type contains. Then the data record type of the data record to be checked, to which the base register is called and a comparison is made. The status code of the status register becomes in accordance set with the results of the comparison. The audit record type command is in XI format, as shown in 20B is shown.

The firmware flow chart for the Audit Record Type command is shown in FIG. At operation 4001 of the firmware flowchart the format of the command is checked. Operation 4003 then calls the record descriptor, that contains the related record type. Then, in operation 4005, the record type is determined by the base register addressed data record is called, and in operation 4007 the actual comparison of the two data record types takes place. In operations 4008 and 4009, the status code is set in accordance with the result of the comparison. A status code of 1 is set if the data record types are the same, or a status code of 0 is set, if the record types are not the same. Operations 4010 and 4011 terminate the hardware / firmware command.

In the following, FIG. 26 will be discussed in more detail. First, in operation 4001, the MBZ field 1923 of the command (see Figo 20B) checks whether it is 0. This check for 0 takes place in that the command from the command calling unit (see FIG. 13a, IFU 1318) is transmitted to a register in the arithmetic unit 1317. If the in this register The hardware test carried out determines that the MBZ field

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is not 0, the firmare branches to exception handling as indicated in FIG. 26 with 4002. This exception is called a Forbidden Format Field Exception designated. If the MBZ field is 0, the firmware proceeds to operation 4003, in which a call of 4 bytes for the main memory takes place at an address which is derived from the address syllable AS 1922 of the command. This address formation occurs in the address control unit (see ACU 1319 in Figure 13a). As a result of the call to memory you can Memory access exceptions occur, as indicated by 4004 in FIG. Some examples of memory access exceptions are "outside of segment", "segment does not exist" or "outside of main memory". The first 25 bits of the The four bytes called up or called up represent a data set descriptor as described in connection with FIG. 19b has been.

At operation 4005, a call is made to main memory to determine the record type of the record addressed by this command to obtain. The data record referred to by the command is addressed via the base register BR, which can be found in the 1926 field of the order. This call to main memory is a call for two bytes, whereby the first 10 bits represent the type of record for both virtual storage records and database storage records, as illustrated in Fig. 15a (field 1501) and in Fig. 15b (field 1510). This type of record, the is called is transmitted to the data management unit 1321. As a result of this memory call you can Memory access exceptions 4006 occur. After the 10 bits representing the record type from the storage unit 102 (see FIG. 1) are transmitted to the data management unit 1321, the firmware controller then transmits the 10-bit data record type of the addressed data record to the arithmetic unit 1317.

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At this point the arithmetic unit now contains both the reference data record type indicated by the address syllable and that was called in operation 4003, as well as the record type of the record that was called by the command addressed via the base register and called in operation 4005. In operation 4007, the firmware the comparison between the record type of the record addressed by the base register and the related record type the end. This comparison is carried out by the main adder unit of the arithmetic unit using the comparison function. If the firmware control determines an equality between the two compared data record types, the firmware executes a branch to operation 4009. If the comparison leads to an inequality, leads the firmware branches out to operation 4008.

If the firmware shows a match between the record type of the addressed record and the related record type and if the branch was made in operation 4009, the status code of the status register (see 207 in FIG. 2) set to 1 by the hardware / firmware. Operation 4011 is then carried out, in which the command is completed and in which the hardware / firmware executes a branch to the next command.

When the comparison between the record type of the record and the related record type results in an inequality result leads to the branching to the operation 4008, in which the status code of the status register 207 by the Firmware / hardware is now set to zero. Following operation 4008, the firmware applies a branch to operation 4010, which completes the instruction and branches to the next instruction will.

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Referring now to FIG. 27, in a block diagram representation there is shown the hardware required to execute the audit record type database command. To the inclusion of a test data record type command as a display signal The relevant command is temporarily stored in the command buffer 4202 by the test data record type command detector 4201. The command buffer is located in the command calling unit 1318 of the central processing unit 104. As above mentioned, the audit record type command transferred to the command buffer 4201 has the XI format as shown in Fig. 20B is shown. The MBZ field 1923 is immediately linked to the O bits 4204 compared by means of the comparator 4203. When the comparator 4203 has a disagreement signal outputs, a forbidden format field exception has been detected and the forbidden format field flip-flop 4205 becomes set. This activates the exception handling mechanism. The execution of the audit record type command will then be completed. If the comparator 4203 indicates a match, execution of the audit record type command continued as described below.

The determination of a test data record type command by the test data record type command detector 4201 also leads to the fact that the output of descriptor read / flip flop 4208 a 1 value is set. The output signal of this flip-flop is referred to as the descriptor read signal. The AND element 4206 is through the descriptor read signal and through the match signal from comparator 4203 enabled b2W. Made transferable to the address syllable 1922 to the address control unit 4207. When an address syllable is supplied, the address control unit sets 4207 converts the relevant address syllable into a memory address. The memory address established by the address control unit 4207 is transferred to the memory address register 4209. Of the

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The contents of the memory address register 4209 are in turn transferred to the memory address register 4210 of the memory system.

The audit record type command detector 4201 is also on the inverting AND gate 4211 connected, which in turn is connected to the memory system read / write flip-flop 4212 is. The 1 signal emitted by the relevant detector leads to the output signal of the AND element 4211 occurs with a logic 0 value, which leads to the read / write flip-flop 4212 being set to the 0 state will. If the memory system 4213 has determined that the memory address register 4210 has been loaded and that the Once read / write flip-flop 4212 has been set to the 0 state, a memory read operation is initiated. As a result Memory access exceptions 4214 may occur during a memory operation. If such exceptions occur, will the memory access exception flip-flop 4214 is set to the 1 state. The exception handling is activated. Furthermore the memory operation is terminated normally, and the memory operation completion flip-flop 4215 is set to the 1-link state. On the transition of the memory operation completion flip-flop 4215 in the 1-link state are the data read from the memory system 4213 to the memory data register 4216 has been transferred. The transition of the memory operation complete flip-flop 4215 to the 1 logic operation state in connection with the 1-link signal occurring descriptor read signal enables the record type field 1821 of the just read from the storage system Record descriptor from storage data register 4216 through AND gate 4217 to the descriptor record type register 4218 is to be transferred.

Bs should also be noted that the outcome of the Memory operation completion flip-flops 4215 with the reset

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input of the descriptor read flip-flop 4208 is connected. Accordingly, the transition of the memory operation completion flip-flop 4215 to the logic 1 state causes the output signal of the descriptor read flip-flop 4208 to drop to a 0 value. Since the descriptor read signal to the inverting AND gate 4238 is supplied, this causes lowering of the descriptor read signal on a OW _e rt, that the output signal of the inverting AND gate 2238 rises to a 1 value. As a result, the data record type read flip-flop 4220 is set to the 1 logic state, namely, since the output of the AND element 4238 is connected to the set input of the data record type read flip-flop 4220. The output of this flip-flop 4220 is referred to as the record type read signal.

The BR base register field 1926 of the instruction buffer 4206 is connected to the AND gate 4221. This AND element is enabled or made transferable by the data record type read signal. The rise of the data record type read signal to a 1 link value thus causes the base register field BR 1926 to be transferred to the base register input 4222 of the address control unit 4207 via the connection of the AND element 4221. If the base control unit 4207 is supplied with a base register number at its BR base register input 4242, the resultant action consists in reading out the content of the base register whose number was entered. This operation is a typical cache read operation. The base register content from the address control unit is output via the OR gate 4223 to the base register output 2224 of the address control unit. The output of the base register or the base register output. 4224 is in turn connected to AND element 4225, which is enabled or made transferable by the data record type read signal. The output of AND gate 4225 is to address control unit 4207

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tied together. When the content of a base register is supplied to it, the address control unit sets this content into a memory address.

Accordingly, the output signal of the address control unit 4207 also again represents an address which is transferred to the memory address register 4209, which in turn is a Transfer to the memory system memory address register 4210 makes.

If the memory system 4213 determines that its memory address register 4210 has been loaded with a new address and that the read / write flip-flop 4212 is in the O-logic state is also a memory read operation initiated. As a result of a memory read operation, memory access exceptions 4214 may occur. If such Exceptions occur, the memory access exception flip-flop 4214 is set to the logic 1 state. The exception handling is activated. Otherwise, the memory operation is normally ended and the memory operation completion flip-flop 4215 is set to the 1-link state (The memory operation completion flip-flop 4215 goes into the O logic state upon initiation of any memory operation postponed). At the end of the storage operation, the data read from the storage system, the represent the data record type (1501 or 1510 according to FIGS. 15a and 15b) of a data record to the memory data register 4216 transferred to.

The data set just read from a data set in the storage system and transferred to the storage data register 4216 is fed to AND gate 4226. This AND gate is activated by the data record read signal and by the memory operation completion flip-flop 4215 made transferable.

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At the end of the second store operation that occurred during execution this command has been executed, the record type of the record that was read via the AND gate 4226 transmitted and fed to the comparator 4227 on the input side. The other input signal to the comparator 4227 provides a descriptor record type register 4218 which has previously been loaded with a record type selected from the descriptor read in the first store operation has been obtained.

If the comparator 4227 determines that the two types of records being compared are the same, that gives The equality signal output to the AND element 4233 means that a binary value 01 is transferred from the register 4232 to the OR gate 4234 free. If the comparator 4224 determines that the two record types are not the same, it returns the inequality signal fed to the AND gate 4231, the transmission of a binary value 00 from the register 4230 to the OR gate 4234 free. It should be seen that the memory operation complete flip-flop 4215 is connected to AND gate 4228 connected. This AND element is read by the record type signal released or made transferable. The output of AND gate 4228 is with the set status code flip-flop 4229 connected. It follows that this flip-flop 4229 is set in the 1 logic state after the second memory read has been completed (reading the record type of the record to which the audit record type command has been pointed). The exit of the set status code flip-flop 4229 is with the AND gate 4235 connected, which thus puts the OR gate 4234 in the state, a binary value 00 or 01 in the status code register 4236 to which the AND gate 4235 is connected. The status code register actually becomes through the first two bits of the status register

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formed as shown in FIG.

The transition of the set status code flip-flop 4229 to a 1 logic state also causes the command completion flip-flop 4237, to which the output of the flip-flop 4229 is connected, is set to the 1 logic state, and at the same time that the status code value in the status code register 4236 is determined or set. That Set command completion flip-flop 4237 to a 1 logic state indicates the completion of the check record type command.

The unload database command is a firmware / hardware command that writes the pointer for a data set into main memory. The pointer is made up of a base register for virtual memory data records (see FIG. 16a) and an index register for database data records (see Fig. 16b). The pointer mode in the command format indicates whether the Pointer is a virtual memory pointer or database record format pointer. The discharge command is in XI format as illustrated in Figure 20B.

The firmware flowchart for the unload command is shown in FIG. At operation 5001 of the firmware flowchart the dj * s format of the command is checked. Then definitely operation 5001, whether the record is a virtual storage record or a database record, or not, and a branch is then made to operation 5003 or to operation 5005 to transfer the to write the pointer type in question, either from the base register or from the index register. The command is terminated after the memory write operation.

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28 is discussed in more detail below. First of all, operation 5001 creates the MBZ field 1923 of the command (see 19b) checks whether it is 0. This check for 0 takes place in that the command from the command calling unit (see FIG. 13a, IFU 1318) is transmitted to a register in the arithmetic unit 1317. If the in this register If the hardware test carried out determines that the MBZ field is not 0, the firmware branches exception handling, as indicated by 5009 in FIG. 28. This exception is called a Forbidden Format Field Exception designated.

If the MBZ field is 0, the firmware proceeds to the operation 5002, in which the P field 1925 of the command (see FIG. 20B) is checked in the arithmetic unit. This P field contains the pointer mode as described above. As has been stated, the storage records are virtual Class 0 or class 1 pointers. The database records are class 2 or class 3 pointers. The arithmetic unit thus checks the 2-bit P-field 1925 in order to carry out a check with regard to the value 0 or 1. If If this state is present, a branch is made to operation 5005, whereby the data record is from the virtual Storage type is. If the arithmetic logic unit determines that the 2-bit P-field 1925 is equal to 2 or 3, the record is a database data record, and a branch is made to step 5003.

A write occurs at operation 5005, where the firmware branches for virtual memory records into main memory an address entered by the address syllable 1922 (see Fig. 20B) is given. The contents of the base register to be written into main memory is from the address control unit 1319 to the data transfer

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management unit 1 ^ 21 transferred. The hardware main memory write mechanism then effects the transfer from the data management unit 1319 to the main memory (see Fig. 1). As a result of this main memory write 5008 memory access exceptions may occur. The address syllable AS1921 is formed in the address control unit 1319. In response to the main memory write of operation 5005, the firmware branches to the Execute operation 5006, which completes the command. Firmware control is transferred to the next command.

If the pointer class had been class 2 or 3, the firmware would have branched to operation 5003. During this operation, the content of the index register, the number of which is given by the BR field 1926 of the command, is stored in the main memory 102 is written at the address which is derived from the address syllable AS 1922. The content of the The index register is transferred from the buffer memory 1315 to the data management unit 1319. The hardware main memory write mechanism then transfers the data from the data management unit to the main memory. As a result Memory access exceptions 5007 may occur during this main memory write. The address formation is carried out in the address control unit 1319 carried out for the address syllable AS. The main memory write in the operation Towards 5003, the firmware branches out to operation 5004, at which the command is completed and in which control is transferred to the next command.

Referring now to FIG. 29, it is a block diagram representation the hardware required to execute the unload database command is shown. on the inclusion of an unloading order, as indicated by the

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Unload command detector register 5201 is displayed, the Command stored briefly in command buffer 5202. The instruction buffer is located in instruction fetch unit 1318 of the central processing unit 104. As mentioned above, the load instruction transferred to the instruction buffer 5202 has the XI format, such as this is shown in Figure 20B. The MBZ field 1923 is compared directly with the O bits 5204 by means of the comparator 5203. When the comparator 5203 has an inequality signal returns, an invalid format field exception has been detected and the invalid format field flip-flop 5205 is set. The execution of the discharge command is then completed. If the comparator 5203 finds a match indicates, the continuation of the discharge command is continued as described below.

The detection of a discharge command by the discharge command detector 5201 also causes the AND gate 5206 to be enabled or made transferable. This is the transfer of the BR field 1926 to the buffer address register 5207 allows. A high order bit 5208 is transferred to the buffer address register 5207. The buffer address register then contains an address of an index register, which is a database pointer as described above. The cache address register 5207 is used to read an address from the buffer 5209. This is the same buffer as shown in FIG. 13 by buffer 1315. The ones from the cache 5209 read out data is transferred to the temporary storage data register 5210. With the AND element 5211, a decision is made as to whether this data read into the buffer data register 5210 is made further processed. This AND element is made transferable when it is determined that the bit 0 or

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the P field 1925 in the command buffer has a value of 1. 3in fourth of 1 is determined when the P field equals a Has a binary value of 2 or 3, i.e. a database record type record is present. When the IM) member 5211 is replaced by the P-bit 0 is made transferable, the contents of the temporary storage data register 5210 are transferred to the OR gate 5217 and then into the memory data register 5218.

The base register BR 1926 is also transferred from the instruction buffer 5202 to the address control unit 5212. These The unit is the address control unit 1319, as shown in FIG. 13a which describes the central unit. When a base register number is supplied, the address control unit reads 5212 the contents of the relevant base register into the register 5214. Register 5214 is on the AND gate 5215 connected. It should be seen that the bit 0 of the P field 1925 of the instruction buffer 5202 corresponds to the inverting AND gate 5216 is connected, which in turn is connected to the AND gate 5215. Accordingly, the AND gate becomes 5215 made transferable or enabled under the condition that the bit with the number 0 of the P-field 1925 a Has a value of 0, i.e. when P is equal to 0 or 1, for virtual memory records. Is a release is done by the AND gate 5216, the content of the Base register 5214 transferred from AND gate 5215 to OR gate 5217 and to memory data register 5218.

After the unload command detector 5201 has detected an unload command and after the command is entered into the command buffer 5202 has been transmitted, the address syllable 1922 is via the AND element 5230 is transmitted to the address control unit 5212. The AND gate 5230 is determined by the match signal from made transferable to the comparator 5203, which, as previously described, is a condition that then exists

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is when it has been determined that the MBZ field 1923 a Value of O. The address syllable 1922 associated with the address control unit 5212 is transferred to a memory address. The one through the address control unit Memory address formed 5212 is transferred to register 5213, the memory address register. The content of the In turn, memory address register 5213 is transferred to memory address register 5219 of the memory system.

At this point, has the storage system 5220 in its memory data register 5218, either an index register - if the discharge command indicating that record database is carried out on a - or even a base register - if the discharge command has indicated that it is carried on a virtual data storage set out _o The memory address register 5219 of the memory system contains an address which is the address at which the contents of the memory data register 5218 are to be written. When the memory system 5220 determines that the memory data register 5218 and memory address register 5219 have been loaded, a memory write operation is initiated. The memory system is commanded to perform a write operation because the read / write flip-flop 5224 has been set to the 1 state by the unload command detector 5201. As a result of a memory write operation, memory access exceptions 5221 may occur. When such exceptions occur, memory access exception handling is enabled. Otherwise, the memory operation is normally ended, and the memory operation completion flip-flop 5222 is set to the 1-logic state. Upon the transition of the memory operation completion flip-flop 5222 to the 1-logic operation, the command completion flip-flop 5223 is set to the 1-logic operation, whereby the completion of the discharge command is indicated.

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List of terms

Absolute address The physical address of a hardware byte in the main memory.

Address development A hardware function that consists of a number of address elements to form an absolute Address calculated / which indicates a memory location in main memory,

Addressing Localization of an object through a number of virtual logical and physical Middle.

Address room A group of logical segmented addresses corresponding to a process, which the central unit is allowed to convert into absolute addresses while the process is being carried out.

Address space word One of two words in a process control block, which indicates the segment table word order. The latter defines those assigned to the process Segment tables.

Adressensilbc A logical address that can be determined by the hardware of the central processing unit, usually the operand of an instruction.

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Analyzer / Translator That part of a static link unit that which first directs the flow of control language to the connection unit; if the control language is correct the analyzer / translator converts these into tables and other structures for use by the static Connection unit around.

Asynchronous processing Simultaneous activation of more than

a process.

Auxiliary memory Consists of 64 flip-flops for storage various system states and is * in the calculator.

Base register The main element in segment addressing is identified by its number in each Address syllable selected.

Boundary Address Register A visible hardware register which defines the lowest memory address accessible to the firmware / software is.

call

See Procedure Call - Inward Call, Outward Call.

Central processing unit Part of the computer, which the circuits for controlling the interpretation and the exercise of commands.

channel

Communication link between the processor subsystem and a peripheral subsystem. There are physical and logical channels. A physical channel _N is the hardware connection between the on / off control unit IOC and the Pg-7 0.9 810/0993

peripheral control unit PCU. * A logical channel is a software connection path between main memory and a single peripheral device.

Channel input command Command in a channel program.

Channel Command Word An element of a channel input command. Two channel command words form a channel input command .

Channel program A sequence of commands that enable a specific input / output operation to be carried out cause by a peripheral device.

Complementary code A code in some commands that goes together defines the function of the command with the operation code.

Compilation unit The single object code module that is used during compilation or assembler a procedure in a processor with a highly developed program language results, the compilation unit is not an executable Unity, it is connected.

Simultaneity Obvious simultaneity.

Conditional field
(Condition Field) A 4-bit field in a branch instruction. Each bit in the field corresponds to the setting of a condition code in status register bits 0 and 1.

Contest Indicator A hardware structure in the auxiliary memory, which indicates that a new input command is queued and possibly a priority content

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Data address space

A group of logical data record addresses which are accessible to a process via data management; it consists of four elements: logical fields, logical records, database pages and
Files.

Data descriptor A command structure which, in indirect addressing, is used for the description a certain data treatment is used.

Decor

The functional properties or the structure of a computer system.

Decor extension mode An operating mode that enables the system to operate in emulation mode.

Descriptor A 32- or 64-bit field which is used in the Address expansion of each data field is used. It is only one of many pointing addresses in the present addressing scheme.

Device adapter descriptor block A block of data that contains any number Differentiation of descriptor explanations with the exception of semaphore descriptors contains. No other dates are allowed.

Electronic circuits for adapting a specific device to a peripheral control device.

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Device adapter interface

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Interface between a device adapter and its associated peripheral control device.

Device control A software unit for processing device-specific parameters.

Dispatcher The firmware that is responsible for the allocation of processes in the central unit is.

Allocation A field within the command format or a data descriptor which supplies information about the relative position of a segment.

Shift addressing A form of indirect addressing in which the operand is in relation to either on the basis of an immediate segment or on the current position counter.

Dynamic addressing

Editor (Editor) An addressing process which, during execution, leads to the resolution of references defined within the process group.

That part of a static connection unit that forms and outputs any or all of the information that results from the connection of a certain procedure .

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Effective address

(Segmented address)

181 -

In contrast to the physical one, a logical address, which consists of a Segment table number, a segment. t 'table entry number and a relative Segment address exists. These elements show the way to a specific segment descriptor, which is ultimately indicates the selected segment.

Emulation mode A computer mode of operation in which another computer is started and which appears to be running on the other computer.

Exception An exception occurs when the hardware recognizes the presence of a state

that requires special processing.

Event Anything that is detected in a system by a process and for one other process may be of interest.

Firmware That part of a hardware process that uses a type of microprogram control.

G _r D name The one used by the hardware as a reference to a

Semaphore used name. The G segment name is the number of the entry in the G table which contains the segment descriptor; D is the relative address in the segment.

G segment A segment that contains the semaphores by using the G, D names and the associated storage reallocation options (G table) can be addressed.

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- .182 -

G table

A table for memory reallocation (localization of a G-segment), when the G, D name is used.

Gate control
(Gating)

A way of controlling access to procedures in a segment through the use of procedure descriptors.

General register A 32-bit register available for the execution of processes, which generally contains binary data
or contains data in bit form of a bit string. Certain general registers can be used for indexed addressing (GR8 to GR15).

index

A data structure that is retained and processed by the system. The structure only appears to the user in the form of a key that he uses
Indicating purposes of access or positioning to a particular data record process.

Index

Modifying an address with signed arithmetic values, by adding something.

Index register

A general register that is used for indexing (GR8 to GRl5).

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Indirect addressing An addressing process in which one address is used to generate another Address is used instead of determining the actual data.

Indirect base addressing The type of indirect addressing in which a data descriptor with a ^v base register number and an offset is found under the address referred to.

Indirect segment addressing The type of indirect addressing a data descriptor with a segment address at a selected address Is found.

Indirect segment descriptor A type of segment descriptor which contains information for addressing another segment descriptor instead of the segment itself.

command

The working unit of a central processing unit that is recognizable to the programmer.

Command counter A register assigned to the current process, which contains the segment addresses of the next instruction of the Contains procedure.

Interleave The successive access to memory modules, to reduce the memory access time sffu.

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Interruption The interruption of a process in the system as a result of the occurrence of a Event.

Interrupt Process A process that is started when an interrupt occurs.

Inward call If one is within a ring zone running procedure calls the running of a procedure in a lower ring zone.

Input / output control device A unit that provides the basic

Control for a special input / output subsystem effected.

I / O processor Potentially asynchronous system processes, primarily involved in moving data between peripheral memories or input / output devices and main memory are busy.

J.P. Tables A collection of logical addresses for the Localization of a process control block.

job
Job control language A unit of work in the system.

A language used to describe a job and its parts.

Job step

The body of a job that is required to perform one of the tasks specified by an instruction in the program defined in the job control language.

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Job step table A system table which is used for the Definition of the first part of a process name, i.e. used for locating the process group table will.

Linked Module The output of the static link unit. It's a consolidated group of compilation units whose cross-references by the static connection unit have been resolved.

Logical processor A collection of hardware tools and control information for execution of a process.

Main memory

Magne tb ands expensive device The total addressable memory space from which commands are executed or from which data can be loaded directly into registers.

Peripheral subsystem associated with the elements of a tape recorder.

Large storage control unit

Storage management The elements of a peripheral subsystem associated with large storage facilities.

Operating system options for assigning, rearranging and sharing a physical memory.

Message The from a source or to a destination information transmitted, with neither source nor destination

is a file. _{A AA} _

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Microinstruction same as microinstruction word and memory control word.

Microprogram A group of machine codes used in can be used to execute control functions of a processor.

Multiplex The sharing of resources such as a memory; usually achieved through time division.

Multi programming

The simultaneous exercise of two or more programs through a single one Computer.

Native mode operation "of a computer in its own" Effective range.

Offset

In address development, the number of bytes after the start of a segment, at which an addressed part of the segment begins.

Operating system A system of basic software for the support of the effective Use of the user software.

Away call If a procedure running in a ring zone, another procedure calls for execution in a higher ring zone.

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Peripheral control unit -A self-contained micro-programmed

Processor, which channel programs for the implementation of input / output operations executes.

Peripheral system interface A standard interface for transmission and control between independent peripheral control units and input / output units.

Physical data structure A complete definition of the data organization as it is physically recorded on a storage medium.

Physical input / output

That part of an operating system that handles the transfer of data between sets and controls the memory and peripheral or terminal devices.

Physical storage The hardware used to store data. It is made up of various types of recording media and read / write hardware.

P operation Privileged command

A machine instruction with a semaphore which causes the process to enter the waiting state or to receive a message.

A command that must be carried out in ring 0.

Procedure A named software function or algorithm that can be executed by a processor without concurrency: a Fortran subroutine, a gobol program, an internal procedure

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in the program language I.

Procedure call A mechanism for creating a stack frame within a Stacking segments.

Procedure descriptor A word that contains the place and entry point of a procedure.

Procedure segment A type of segment, the content of which is a procedure, several procedures, or one Represents part of a procedure.

Process

The orderly execution of instructions by a processor without concurrency either centrally or with input / output.

Process address space Memory addresses which are selected during a specific process can or to which the control can be transferred.

Process control block A hardware-defined and determinable one Data structure that contains the information to determine the status of a process at any time to be able to.

Process group A group of related processes usually those that are necessary to carry out a single job step are.

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Process Group Builder That part of the static connection unit, whose use leads to the linked module.

Process Group Loader A possibility of the operating system, which brings about the final decisions in a linked module and a feasible process group then loads the process group into memory and executes it sets in motion.

Process connection An entry point in a prepared process or a waiting one Process queue.

Process state

The dynamic state of a central processing unit process, for example ongoing, prepared, waiting or suspended.

Process switching The hardware function that controls a process from the central unit and connects another to it.

Process synchronization The function that coordinates the asynchronous activity between the processes. This function generally includes semaphores and the P and V operations.

processor

A unit which receive and process data, provide results and control their operation sequence in accordance with a stored program may be _N; general term for central unit, peripheral processor or hardware

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ware / software processor.

program

The specification of procedure-determining and related information, which is necessary to solve a problem, i.e. the orderly collection of commands, which is executed by the computer in order to carry out a user job or a specific Phase of such a job.

Program execution The activity of a process in accordance with the program specification.

Protective function The function guaranteed by hardware and software to prevent mutual interference of processes or the unauthorized sharing of address space.

P table (process group table) A hardware-defined data structure with input points, each of which points to the origin of a process control block indicates. The P table entry points also point to the entire group of process control blocks that are a process group at any given time contain. It is also called a process group table.

Q / PR / RDY. The queue of a process is prepared.

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Queue

Preparation state (ready state)

An ordered list of input variables, which are based on Informatiom or wait for access,

which on information a process

A process state in which no processor is assigned, but all necessary ones Tools with the exception of the processor for the transition to the run state are prepared.

Relative address

Relocation

Return

ring

The incrementally defined place of one object in relation to another.

Moving a segment from one location in main memory to another including the adjustment of all necessary references to its previous one Location.

The function and the operations which are necessary for the operation of a procedure at a point that immediately follows the point where it entered another procedure has passed.

A protection attribute of a segment which restricts the read, write and execution access of a process to that segment. The ring also provides the degree of privilege is a process for reading, writing, or performing operations.

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Transfer of control (rolling-in)

Perform the operations necessary to control a process based on. a transferring a new process.

Removal of control (rolling out)

Carrying out the operations necessary to control a processor through end a process.

Running condition

The dynamic state of a process connected to the central unit, which is currently running.

Intermediate memory (scratch pad memory) 256 memory locations in the arithmetic unit for Storage of control information for the central unit, also known as local memory.

Scheduling

Scientific register

Α · ί.

segment

Determination of the sequence of the individual operations.

A 64-bit register which is used when processing binary floating point numbers is used. In the present system this has four scientific registers in the scientific option.

_. more cohesive. . , A .. main storage space, which is treated as a unit.

Segmentation The division of main memory into logical groups called segments Place of division into a single linear memory space.

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Segment base

The running origin of the segment. This is one of the fields in a segment of the crypto word.

Segment descriptor

The entry point in a segment table which defines the parameters of a segment or indicates a segment descriptor.

Segment number The identification of a specific segment consisting of a segment table number, which selects one of the segment tables of the process, and a segment table input parts the selected table.

Relative segment address The final one during address development Value to be added to the segment base to get the absolute address obtain.

Segment table

Segment table entry point A table with segment descriptors, which defines the addressability of a process for its segments. The collection of segment tables of a Process determines the address space for that process.

A place in a segment table. Each segment table entry point is a segment descriptor.

Segment table word The entry into a segment table word arrangement, which indicates the segment tables of a process. The arrival

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Order is denoted by one of two address space words in the process control block.

semaphore

Data structures for controlling the exchange of information between processes.

Semaphore block

A block of data that only has semaphore descriptor declarations contains.

Stack memory
(Stack)

A mechanism that takes in data, stores it and enables it to be retrieved according to the principle that the information entered last is output first. It consists of one Number of adjacent parts, which are called stack frames.

Stack active area

That part of a stack frame that is currently in use which a reference to a reserve area, the command counter of the caller, Parameter space and local variables contain, in short, the data of the current running frame, which are most likely useful for the execution of the called procedure.

Stack base words

A group of three words in a process control block that make up the segmented Contains addresses of the stack memory segments for rings 0, 1 and 2 associated with the process.

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Stack frame

A contiguous portion of the stack segment that contains the stored Contains data for a single procedure call.

Stack operation The operations for storing and retrieving of information in and from the stack. In practice, the processing of reference addresses on the information contained in the stack.

Stack Overflow Trying to put more information on the stack than is available in this memory space. This condition is determined by the hardware.

Stack register See T register.

Stack segment · The segment of a process which whose stack contains.

Static connection unit
(Static Linking) An intermediate step between compiling a source procedure and executing the object form of such a procedure. The link releases the external references to and from this procedure.

Status register

Save away from home
(Swapping)

An 8-bit register, which identifies the status of the currently running procedure.

Relieving the main memory space occupied by a segment by reloading

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of the segment in a secondary storage. The actual rewriting in the secondary memory can be suppressed, if the segment has not been changed since the last readout.

Synchronization A fixed time allocation, for example the synchronized execution of two or more processes.

System basis A fixed area in the main memory, which serves as the root for all information structures.

Task

Smallest unit of the work determined by the user, which consists of only one single stream of commands that do not occur at the same time.

T register A hardware register visible to the software, which contains the segmented address of the top of a procedure stack.

Aufzeichnungsgerät- control unit the elements of the peripheral subsystem connected to recording devices such as maps = - are punch and readers, strip punches and readers and line printers in connection.

User Process Group The internal representation of any job step as opposed to a system process group that is independent of any job.

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Vacancy indicator

A hardware structure which indicates that the process which is in the central processing unit has expired, has exposed itself, i.e. that no Process is in the central unit. It is then located in an auxiliary register of the arithmetic unit.

Virtual memory

An addressing method that allows the programmer to code without regard allowed on the physical size of the memory. A virtual storage control system ensures the exchange of segments between the main memory and the secondary memory.

V operation

Ab. £ ancf-semaphore A machine instruction for notification of the completion of an event within of the process. A V operation is performed on a specific semaphore.

Semaphore with non-programmed jump or breakpoint.

Field class

A group of similar field values, each field value from a different one Record originates in the same record class and the field values are used to store the same Property to be used. For example, all field values for the age within the record class for the Employees.

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Field value A data element which is assigned to a data record / which represents the value of some property of the system element represented by the data record. The value can be represented by a character string, a number, a Boolean ¹ value or any data which can be interpreted as the value or which lead indirectly to the value.

Member A role that a record is related to a group appearance plays.

Pointer pointer An item of information related to the Identification of a system element within an information structure is used. The content of the reference address can be a unique symbol that represents the system element or the address of the system element is identified in some address range.

Database hint address

A pointer whose content is based on an address range which is different from the normal addressing range of the computer. Database reference addresses are typically equipped with address ranges which are larger than the hardware-supported addresses and therefore offer some options for indirect addressing, which circumvents the problem of continuously unused memory space.

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Intersegment pointer

Virtual memory pointer

A pointer, the content of which is determined by the partially virtual memory address of the system element to be addressed is formed. The missing segment part of the virtual Memory address is the same as that of the segment of the inter-segment pointer and is thus implicitly known.

A pointer, the content of which is determined by the virtual memory address of the address to be addressed System element is formed.

record

A data element that describes an object in the actual environment. For example, a “personal ¹¹ data record represents an employee.

Record class

A group of similar records that are defined so that each record only satisfies a single record class. For example, all "personal" data records.

Record descriptor

An information structure that is used in the creation, recognition and destruction of data record structures. The record descriptor refers to a single record class.

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group

Group class Group descriptor

User A group is a collection of one or more data records. It uses a "user" record that defines the group. It also has zero, one, or more "member" records. A group can be ordered to refer to the following:

"first member"
"last member""nextmember""previousmember"

A group class is a named collection of groups based on rules for:

Group roles

Group appearance selection group order

A group can be a member of only one group class be. A data record can only be a member of one group within a group class.

An information structure which is used in the initiation, the insertion, the retrieval and removal of data sets in relation to group structures · A Gruppendescriptor refers to a single Gruppenklasee.

A role that a record plays in relation to a group. A group occurrence exists during the period of time during which a record is in the user role exists.

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-ΖΟΪ -

Abbreviations:

ACU (address control unit)

ALU (arithmetic and logic unit)

AS (address syllable)

ASW (address space word)

BAR (boundary address register)

BCD (binary coded decimal)

BR (base register)

CCE (channel command entry)

CCU (channel control unit)

CMRN (the callers maximum ring number)

CCW (channel command word)

CET (current state entry time)

CIA (control store interface adapter)

CJP (currently executing process)

CPU (central process unit)

CU (compilation unit)

CSU (control store unit)

D (displacement)

DMU (data management unit)

DA (device adapter)

EAR (effective address ring)

EXW (exception word)

GR (general register)

GTW (G-table word)

IC (instruction counter)

IFU (instruction fetch unit)

Address control unit arithmetic unit

Address syllable

Adress en Raumwo rt Address limit register

Binary coded decimal digit

Base register channel input command channel control unit

maximum ring number of the caller

Channel command word

Entry time of the current state

Control store interface adapter

Process currently running central processing unit compiler unit Storage control unit displacement data management unit device adapter effective address ring Exceptional word general register G table word Be f eh 1 s ζ Sh lwe rk Command fetch unit

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I / O (input / output)

IOC (input / output controller)

IPQW (internal process queue word)

IR (index register)

ITBR (indirect to base register)

ITS (indirect to segment)

J (job)

JCL (job control language)

JTW (J-table word)

LCT (logical channel table)

LIFO (last-in-first-out)

LSU (local store memory or scratch pad memory)

HBZ (must be zero)

MOS (metal oxide semiconductor)

MAXR (maximum ring number)

MSC (mass storage controller) MTC (magnetic tape controller) NFS. (Non-functional status)

NPRN (new process ring number) NJP (new process replacing the

currently executing process)

PCB (process control block)

PCT (physical channel table)

PCU (peripheral control unit)

PL / I (programming language / one)

PMW (process "main word)

Input / output input / output control

Internal process queue word

Index register

Register for indirect basic addressing

indirect segment addressing

job

Job control language J table word logical channel table

last entered / first removed local memory or intermediate memory must be zero
Metal oxide semiconductors

maximum ring number at which a procedure can be executed. It is found in the segment descriptor SEG _ßp .

Large storage control unit Magnetic tape recorder control unit

non-functional condition ^:

new process ring number

new process to replace the current process process control block physical channel table peripheral control unit program language / l process main word

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Q / PR / RDY (queue of processes ready)

RD RHU

RPW RSU

RTO SBW SEG SKW

EP

PD

STN STR STW STWA

WR WTA

(read ring)

(reserved for hardware use)

(running process word) (reserved for software use)

(ready time accounting)

(residual time out) (stack base word) (segment number) (stack word)

(segment containing entry point)

(segment containing procedure descriptor)

(scientific register) (segment relative address) (segment table entry)

(segment table number) (status register) (segment table word) (segment table word array)

(T-register, stack register)

(unit record controller)

• s (write ring) (waiting time accounting) queue of the process prepared

Reading ring

reserved for hardware use

current process word

reserved for software use

Availability time calculation

Remaining time
Stack base word .segment number
Stack word

the segment containing the entry point found in the procedure descriptor having

Segment containing the procedure descriptor scientific register .relative segment address

Segment table entry point

Segment table number status register

Segment table word

Segment table word arrangement

T-register, stack register

Recorder control unit

Writing ring
Waiting time calculation

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Claims (1)

- 204 claims Internally programmable data processing system with one having several addressable memory space segments Memory whose memory space segments are each defined by upper and lower variable limits and furthermore in at least a page are subdivided under a specific shift address within the respective segment and which includes an identification page number, each of the intended pages Used to store a large number of files from database records, which are in groups of database records are grouped, each group including at least one user record, further each of said pages offset address information for designating any one of the database records of a selected group contains the named groups from a specific memory location on a selected page of the existing pages, wherein at least one index register is also provided, which is used to store a selected database index address serves, comprising a database reference address for the formation of an address of a specific database data record, wherein each of the database records includes at least one database pointer, which is composed of an area, page and line address, the relevant area address for defining a specific file of the database data records serves, whereby the page address is used to define a specific group of the database records is used within the relevant file and where the line address is used to define the particular one database record serves, characterized by a command hardware that is responsive to a serial search command and comprising: a) segment number generator means which operates on an area derived from the relevant command 709810/0993 and addresses page address and generates a segment number from this address; b) an address conversion device, which the relevant Converts segment number into an absolute address, which is used to define the corresponding page in relation to a system base serves; c) a display element determination device, which is controlled by the address translation device within the relevant Page defines a display element which is used to determine the availability of a selected database data record serves with respect to the relevant display element; and d) a charging device defined by the indicator member setting device controls the corresponding area, page and line number in the corresponding index register in the event that the selected database record is available. 2. System according to claim 1, characterized in that devices are provided which, depending on the area and page address derived from said command, request an exception in the event that the relevant page is not available. 3. Plant according to claim 1 or 2, characterized in that progressively testing test facilities are provided, which is controlled by the display member setting means, the display members in the relevant page in series and Check progressively one after the other until a display element is accommodated in the relevant page, its associated data record is available on the relevant page. 709810/0993 4. Plant according to claim 3, characterized in that devices are provided by the test devices a serial check is controlled to determine and progressively check the display members make those display members that the data records are associated in a second page, and that the test is continued until a display element in the relevant second page is housed, its associated database record in the second concerned Page is available. 5. Plant according to one of claims 1 to 4, characterized in that that devices are provided that controlled by the loading devices, the relevant side and Convert line number to segment number and offset address. 6. Plant according to claim 5, characterized in that charging devices are provided that include the relevant segment number and the mentioned offset address in load a base register. 7. Plant according to claim 6, characterized in that conversion devices are provided that convert the mentioned segment number and the offset address into an absolute Convert address with respect to the system base in such a way that the database record is determined relative to the system base is. 8. Installation according to claim 1, characterized in that each group of database records has at least one number record has that each of the user and member records is assigned a record descriptor which is used for Description of the associated data record is used to ensure that the 709810/0993 Record descriptors are stored in certain other segments of the relevant segments that an arithmetic unit (ALU) is provided, which is used to perform arithmetic and logic operations on any data or addresses of the segments, data records or descriptors concerned. That the command hardware is used a test data record type command specifies that a selected database data record is a database data record is of the type described by its associated record descriptor and that the command hardware includes the following elements; a) a retrieval device for retrieving the selected a database data set in the arithmetic unit, b) a retrieval device for retrieving the associated Descriptors of the relevant one selected database data record; and c) a comparison device in the arithmetic unit for comparing the type of the one called up in the arithmetic unit Database data record with the type of database data record that is described in the associated descriptor and to provide an indication of whether or not a mismatch has been made. System according to Claim 8, characterized in that the test data record type command has an address syllable which to display a segment number of one of the specific remaining segments in which the relevant associated The data record descriptor of the relevant one selected database data record is stored, and that a memory device is provided which responds to the address syllable in question and which is connected to the comparator for the purpose of storing the segment number of the address syllable in question. 709810/0993 10. Plant according to claim 9, characterized in that the address syllable has an offset address which denotes the address of the associated data record descriptor of the relevant one selected database data record within the relevant one segment of said certain further segments, and that the storage device with the Comparator for storing the relevant displacement address is connected _o 11. Plant according to claim 10, characterized in that conversion devices are provided that contains the address of the associated data record descriptor of the relevant one convert the selected database data set into an absolute address. 12. Plant according to claim 10 or 11, characterized in that that a plurality of base registers are provided and that the test data record type instruction has a base register address which is used to designate one of the base registers provided in a plurality which are in the segmented address are included, namely to determine the relevant one selected database data set. 13. Plant according to claim 12, characterized in that the relevant one base register of the plurality of Basic registers both the segment number of the segment in which the relevant one selected database record is stored, as well as the offset address within the relevant segment of said one selected database record. 709810/0993 14. Plant according to claim 13, characterized in that conversion devices are provided which said Segment number and the offset address of a selected database record of the database records convert into an absolute address. 15. Installation according to claim 1, characterized in that each group of database records has at least one member database bank record has that each database data record at least one reference address for a particular connection Database records and also to connect certain groups of database records that each pointer has consists of a segment number and an offset address which are used to define certain Database records serves that each of the database records is also assigned a record descriptor, the to describe the associated database data record that the data record descriptors in certain other segments are stored, that each group of database records also has a group descriptor is assigned, which is used to describe the associated group and a shift address of the relevant Supplies reference address in a first database record of the relevant group of associated records, that the group descriptors are stored in certain further segments, that a large number of basic registers is provided, each of the segment number of any of the segments concerned and one associated with the segment number Offset address store that offset address for addressing from the beginning of an associated Segment of any data within the associated segment that an arithmetic unit is provided that with information exchange channels with the base registers, the index registers and the system base for the execution of 709810/0993 Arithmetic and logic operations based on any data or addresses of the segments concerned, Database records and descriptors is connected that a command hardware is provided, which is based on a user search command to the user data record of a specific database data record of a group entered first allows to determine that the user search command includes a base register address (BR) used for identification a first base register is used in which a first segmented address of the relevant database data record is stored that the segmented address consists of a first segment number and a first offset address of the database record that the user search command further comprises an address syllable which is used to identify a second base register which a second segment number and a second offset address of the group descriptor associated with the database record and that the command hardware includes: a) a database data record retrieval device which, depending on the first base register address, the Retrieves database data set in the arithmetic unit (ALU), b) a device which, through the database data record calls, controls the group descriptor in the device the arithmetic unit (ALU) calls up, c) a device that controls the beginning by the shift address in the relevant group descriptor of the database record of a user reference address in the relevant database record addressed ^ and d) a device that calls up the user reference address in the arithmetic unit (ALU). 16. Plant according to claim 15, characterized in that the Instruction hardware includes means responsive to the first base register address and the first 709810/0993 retrieves segmented address in the arithmetic unit as well as the converts relevant first segmented address into a first absolute address, through which the relevant Database record is set relative to the system base that a facility is provided that is based on the Address syllable identifies the second base register of the base register, and the second segment number and the converts the second offset address into a second absolute address, which is used to define the relevant database data record associated group descriptor is used, and that a device is provided that the user reference address into the index register. 17. Plant according to claim 16, characterized in that a device is provided by the index register controlled converts the address of the database data record into a third segmented address, which is a includes a third segment number and a third offset address for addressing the user record (the is a specific database record of the database records). 18. Plant according to claim 17, characterized in that means are provided which loads the third segmented address into said first base register. 19. Installation according to claim 18, characterized in that said group of database records is in one page one of the mentioned segments is housed that the relevant page under a certain area and Page address is accommodated that the relevant page has a data record status display element under a specific line address contains, and that facilities are provided that the presence of a database record allow to determine in the relevant page. 709810/0993 20. Plant according to claim 19, characterized in that devices are provided which are based on the determination of the relevant database data record Allow the group descriptor to determine the type of the reference address (pointer) it contains. 21. Plant according to claim 20, characterized in that the relevant reference address is an area, page and Has line address of the user record. 22. System according to claim 20, characterized in that the reference address is a page and line address of the user data record having. 23. Plant according to one of claims 20 to 22, characterized in that that the pointer contains a segmented address consisting of a segment number and an offset address of the user record. 24. Plant according to claim 15, characterized in that a device is provided which, controlled by the arithmetic unit, stores the user reference address in said to accommodate the first base register. 25. System according to claim 1 with a command hardware that the database pointer from the index register in response to an unload command containing an address syllable to be unloaded and accommodated in the database record, characterized in that the command hardware includes the following elements: a) a transfer device that points to the aforementioned database reference address this database pointer into an equivalent segmented number of a segment implements which a selected database record 709810/0993 saves in a selected group, b) a memory device, which is defined by the conversion device and by the address syllable in said Unload command controls a shift address of the relevant one selected database data record to save from a specific address in the named segment, c) an address generation device which is generated by the conversion device and by the storage device controls an absolute address in the memory of the relevant one selected database record allowed to generate, and d) a device that is controlled by the conversion, storage and address generation device in the Database reference address stored in the index register in the relevant one selected database data record allowed to accommodate. 26. System according to claim 25, characterized in that a plurality of index registers is provided and that furthermore Devices are provided which, in response to the named unloading command, address a specific index register through the address syllable. 27. Plant according to claim 26, characterized in that devices are provided which have short-term storage make the contents of the particular one index register. 28. Installation according to one of claims 25 to 27, wherein the discharge command address syllable is a shift address within of the relevant segment of which supplies a selected database data record, characterized in that a) that facilities are provided which provide an address to define the area within it a large number of files are stored in said main memory, 709810/0993 b) that facilities are provided which provide an address for defining a page in which at least one of a plurality of files provided is stored in the main memory, and c) facilities are provided which convert the area and page addresses into a segment number, which serves to identify the segment in which the relevant files area and the relevant Files side are housed. 29. Plant according to claim 28, characterized in that the discharge command hardware further comprises a device which provides an offset address within the designated page through which a particular Database record is set in the relevant one selected group. 709810/0993