DE2609640C2 - Digital control system - Google Patents

Description

systems according to the invention,

F i g. Fig. 2 shows a first embodiment of a digital alteration circuit according to the invention and

F i g. 3 a second embodiment of a digital Change circuit according to the invention.

According to FIG. 1, a central processing unit 6 is connected to a series / parallel conversion and counting device 4. The device 4 feeds a digital / analog converter 8, which in turn acts on an actuator 10. The central processing unit 6 generates a controlled variable in digital form and enters this into the counter 4. The converter 8 converts the stored converts the digital variable of the control deviation into an analog signal which influences the actuator 10

The digital system further comprises a clock generator 12, a pulse generator 2 for generating a variable frequency, a switch 18 and a gate 19. The operator can use the switch 18 actuate by moving it from its central position into one of the two extreme positions in each of the Both extreme positions, a signal is transmitted to the device 4, which indicates in which direction the Switch has been operated. Furthermore, in each of the two extreme positions of the switch 18, the OR gate 19 fed a signal to generator 2. Depending on the coming from the gate 19 Signal, the generator 2 generates a sequence of pulses with a steadily increasing frequency, these pulses can be derived from the clock pulses of the clock generator 12.

The pulses from the generator 2 become the counting device 4 fed and. they increase or decrease the count stored in the counter 4, as the case may be which of the two lines of switch 18 is live. Since - as will be shown - the When the frequency of this pulse train is initially low, actuation of switch 18 will initially cause an slight change in the value stored in device 4. If only a minor change is required, the operator can immediately stop operating the switch 18, whereby the generator 2 is reset, so that when the switch 18 starts again with the initial low frequency pulse train. But it's going to be a big change of the stored value is required, the operator must put switch 18 in the actuated position keep. The frequency of the output of the generator 2 pulses increases, so that the stored Value experiences a change with a steadily increasing rate of change and thus a large one Change can occur within a short period of time. At any point in time, the sudden release occurs of the switch 18 to a reset of the generator 2, so that starting from the set value in turn, fine adjustments can be made.

In generator 2, the clock signal generator 12 incoming pulses are fed to two counters 14 and 16 connected in series. The counter 14 generates different pulse trains of different frequencies, which are divided by frequency division of the clock frequency result and the counter 16 generates timing signals which are obtained by frequency division of the lowest Represent the frequency of the counter 14. The counter 16 is normally in the reset state, and it is only enabled for counting when the output of the OR gate 19 denotes Takes the value "1" As long as the output signal of the OR gate 19 takes the value "0", there is the counter 16 in the reset state. The counters 14 and 16 are connected to a logic circuit 3, the various pulse trains of the counter 14 selects, the selection under the control of the Counter 16 is made so that the frequency of the selected pulse trains increases. Choose for this purpose successive timing signals of the counter 16 pulse trains with increasing frequency of the counter 14 from.

The selected pulse trains are fed to the device 4, these being composed as a composite Show pulse train with steadily increasing frequency.

According to FIG. 2 shows a first embodiment of the generator 2. The counter 14 has four stages and the counter 16 has three stages. The counter 14 thus generates pulse trains with the frequencies

if

which are fed to the gates 20, 21, 22 and 23, respectively, wherein / represents the frequency of the clock generator 12. The counter 16 counts up to the value 8 depending on the output signal of the counter 14 with the lowest frequency Ir-) and the last two stages of the counter 16 are connected to a decoder 24, which the logic states A ^- OO, ΛΌ1, X 10 and ΛΊ1 decoded accordingly and where X indicates that the state of the first stage of the counter 16 is irrelevant. The AND gates 23, 22, 21 and 20 are prepared accordingly by these four decoded states. The pulse trains with the frequencies

f f f, f
^and

are thus sequentially through this AND gate selected and the selected pulse trains are combined by the OR gate 25, which the device 4 controls.

Furthermore, the last count to be decoded of the counter 16, which prepares the AND gate 20, is additionally inverted and connected to an AND gate 26, which connects the counter 14 to the counter 16. Through this the effect is that when the last count of the counter 16 is reached, the counter 16 has this count retained by no further pulses of the counter 14 are switched to the counter 16, so that the counter 16 cannot be returned to its initial state. So once is the pulse train with the highest frequency has been selected by the gate 20, this pulse train remains for the duration the actuation of the switch 18 is also effective. The output of the OR gate 19 is the Counter 16 supplied so that the counter 16 assumes the initial reset state as long as the switch 19 is not actuated and is only released for counting when the switch 19 is actuated will. The output signal of the OR gate 25 is presented as a datier pulse train, the Frequtnz doubles successively three times in the same time periods.

According to FIG. 3 shows a further embodiment of the generator 2. The counter 14 has four stages and the counter 16 has five stages. The counter

14 thus generates pulse trains with the frequencies

fff. f ^and

on lines 30, 31, 32 and 33. The last three Stages of the five-stage counter 16 thus generate pulses with the frequencies

ff , f
T28 "'" 256 " ^and 512

on lines 34, 35 and 36. These pulses and pulse trains are generated by means of three NOR gates 37-39. downstream NAND gate 40-43 and a further downstream OR gate 44 logically combined with one another.

Initially, the output of the OR gate 19 has the value "0", which means that the counter 16 is on the count Is held at zero. If the switch 18 is actuated, the output of the gate 19 assumes the value "1" and the counter 16 starts counting. All three output lines 34-36 of counter 16 initially point the value "0". Line 34 is the line which first assumes the value “1” when counter 16 begins to count. After the same time interval has elapsed, the line 35 has the value “1” and afterwards When the double time interval has elapsed, the line 36 has the value “1”. The impulses on these lines act as timing signals, only the initial changes on these lines are significant.

If the output of gate 19 takes the value "1", so the NOR gate 37 is primed by lines 34-36 to put the pulse train on line

33 to let through. The gate 37 reverses the pulse sequence, but this is of no importance. as well the gate 40 is prepared to pass the output pulse train of the gate 37. This also takes place again a reversal. As soon as the output of the gate 19 assumes the value "1", the Pulse train with the lowest frequency of the counter 14 selected for passage to the OR gate 44 and thus given to the device.

After a certain period of time, the line

34 has the value "1". As a result, the gate 37 is blocked, whereby the passage of the pulse train with the lowest frequency on line 33 is blocked. Gate 38, however, was enabled from the start has been and remains enabled so that the pulse train on line 32 will pass this gate can. Now that the signal on line 34 has also assumed the value "1", that too is Gate 42 prepared so that the pulse train passing through the gate 38 via the gate 41 to the OR gate 44 can arrive.

After the same period of time has elapsed, line 35 assumes the value “1”. Gate 39 was from the start on prepared and remains prepared so that the pulse train on line 31 can pass this gate. The value "1" on the line 35 now also prepares the gate 42, so that the gate 39 passing pulse train can now pass through the gate 42 to the OR gate 44. At the same time Time gate 38 is blocked, whereby the pulse train on line 32 is cut off.

After twice the period of time, the signal on line 36 assumes the value "1". This will make that Gate 43 prepared so that the pulse train on line 30 reaches OR gate 44. Simultaneously the gate 39 is blocked, whereby the passage of the pulse train on the line 31 is blocked.

With the circuit described above, the pulse train with the lowest frequency becomes first selected. Then the pulse train with the next higher frequency is used for the same period of time selected. Then the pulse train with the next higher frequency is used for twice the period of time selected and finally the pulse train with the highest remains for the remainder of the switch actuation Frequency is decisive.

1 sheet of drawings

Claims (5)

1 2 gate (43) from the first stage of the frequency divider Claims: (14) and the last of the m-2 stage outputs of the counter (16) is controlled. 1. Digital control system with a digital storage element storing the control deviation, a 5 nem between the digital storage element and a Actuator-switched digital / analog converter and a switchable by a manual switch The invention relates to a digital control system according to Clock generator for changing the content of the digital generic term of claim 1. tal storage element, characterized thereby. Such a digital control system is, for example, records that between the clock generator (12) se from the magazine "BBC-Mitteilungen", 2/3, 1972, and the digital memory element (4) a change pages 109 consecutive, known There can be with a Circuit (2) is switched, which has: manual switch depending on the direction of his an actuation controlled by the clock generator (12) and the actuation position a clock generator Frequency divider (14), 15 gate with different frequencies to a digital one a storage element can be connected to the output of the frequency divider (14) in order to closed control deviation released by the hand switch (18) must be increased in fine or coarse steps. bar counter (16) for generating timing signals or to reduce them. The saved rule deviation len. and chung acts after digital / analog conversion a logic gate circuit (3), the gate of which is connected to 20 analog actuator. To correct the rule deviation the outputs of the frequency divider (14) and at least the clock generator must have different Frc- at least generate some outputs of the counter (14) connected. sen are to be at its output a in the memory. Based on this well-known digital control system cher member (4) to generate inputtable pulse train, star, it is the object of the present invention, its frequency with the duration of the actuation of the 25 to design this so that depending on the Hand switch (18) is increased. Duration of switch actuation the frequency of the 2. Digital control system according to claim 1, given clock pulses is increased so that starting characterized in that the step outputs of the from a fine step change of the Rcgelabwci frequency divider (14) on one of the inputs of chung this depending on the duration of the switching AND gates (20,21,22,23) and a few steps out of action also changed rapidly and gradually outputs of the counter (16) via a decoding circuit can be. The solution to this problem succeeds according to (24) on the other inputs of the AND gate the characterizing features of the claim (20-23) are performed and that the summarized 1. Further advantageous embodiments of the digital th outputs of the AND gates (20-23) to the control system according to the present invention Storage element (14) are placed. 35 can be found in the subclaims. 3. Digital control system according to claim 2, there- from US-PS 38 26 991 it is already known for characterized in that with the highest deco change the digit count in an analog memory element of the counter (16) the input of the same stored control deviation a change for incoming pulses is blocked. Provide circuit that when operated by means of 4. Digital control system according to claim 3, 40 of a switch generating an increasing voltage, characterized in that between the output which in the control system for the purpose of changing the of the frequency divider (14) and the input of the counter deviation signal is introduced. There leads cilers (16) an AND gate (26) is connected, the ne actuation of the switch initially only to a slight one Input the output pulses of the frequency change of the automatically generated rule deviation divider (14) and its other input, the inversion signal, so that fine adjustments can be made tated highest decoded count of the counter (16) can be. However, in a dangerous situation is fed. , the operator presses the switch longer 5. Digital "control system according to claim 1, there- 'actuate, whereby the change of the automatically characterized in that with an η-step Fre- generated control deviation signal corresponding to the sequence divider (14) of the logic gate circuit (3) runs n - 1 50 ler, so that large changes can be made within short-NOR gates (37-39) and / 1-NAND gates zer time has approximated, (16) m-2 stage outputs are selected that this can be reset by releasing the switch of the changed NOR gate (37) of the series of all m-2 circuit circuit, so stage outputs of the counter (16) and the In the known case, the NOR gate (38) essentially consists of m- 3 stage outputs of the change circuit from a counter (16) and the step output n— \ of the fre- charging circuit for a capacitor, which is more or quenzteilers (14) etc. applied that the less linearly charged and its voltage last NAND gate (40) of the series is then integrated by the signal 60 in order to specify a signal essentially of the switch (18) and the output of the last parabolic course of the rising output i-NOR gate (37), the penultimate NAND gate (41). With the present invention, a circuit arrangement is specified for the first of the m-2 stage outputs of the counter, with the digital lers (16) and the output of the penultimate NOR gate a corresponding effect is achieved. ters (38), the third from last NAND gate (42) of the 65 using two shown in the figures of the drawing the second of the m-2 stage outputs of the counter (16) of the exemplary embodiments presented is the invention in the ΓοΙ- and the output of the third from last NOR gate (39) are described in more detail. It shows etc. is applied and that the first NAND Fig. 1 is a schematic block diagram of the control