DE2527933C2 - Method and circuit arrangement for the determination of external DC voltages independent of interference voltage in telecommunication systems, in particular telephone systems - Google Patents

Description

"/ second measurement phase switchable inverter (N) is connected to an integrator (T) that is a memory

'& f (C) of the integrator (T) to a comparator (G) Attached is that comparator output with a fine gate circuit (L) is a result memory (E)!, that the gate circuit (L) further comprises • at a timing (Z ) connected to the

- ■ - ■ Sequence and duration of the individual measurement phases (d, e), the calming phases and the

'! Door opening ^ determined

3. Circuit arrangement according to claim 2, characterized in that the load resistance (RL) can be changed for a quantitative measurement.

4. Circuit arrangement according to claim 2, characterized in that outside the two measuring phases (d, ejder input (R 6) of the integrator (T) via a contact (K 4) with a reference potential (U) ^ is connected.

■ 5. Circuit arrangement according to one or more of the preceding claims, characterized in that the load resistor (RL) is connected to the same reference potential (U) as the input (R6) of the integrator (T).

6. Circuit arrangement according to claim 2, characterized in that the result memory (E) has an output memory (S / Venthä! T.

The invention relates to a method and a circuit arrangement for determining external equal voltages in telecommunications, in particular telephone systems, with a positive or negative statement based on a predetermined limit value, independent of interference voltage,

There are two types of malfunction in telecommunications systems Noticeable particularly unpleasantly. These are external DC voltages, for example earth potential or another potential, the size of which can be between zero and the exchange voltage, which is carried out by Contact with live or earthed

ίο Parts arise and external alternating voltages, for example from railway line current (16 ² / j Hz) or from technical alternating current (50 Hz), which are inductively or capacitively coupled into office facilities, especially lines.

The object of the invention is to determine external DC voltages, which can be superimposed by interfering AC voltages, based on an adjustable, predetermined limit value.
It is a number of circuit arrangements

to known, which eliminate induced external alternating voltages, in particular from cables, to ensure the reception of characters. Some, for example those described in German Patent No. 20 28 897, use transformers for this purpose, which, however, have to be very large and heavy because of the low frequency of traction currents. Other circuit arrangements, for example according to German Auslegeschrift 1190 052 or! 6 16 449, use two amplifiers with which the interference AC voltages with opposite polarization are recorded, amplified and added.

The invention solves the known problem in a different way. The solution according to the invention is characterized in that the measurement in two

Measurement phases take place, before each of which a settling time is provided that the duration of each measurement phase changes after the shortest period of time, in the full periods of all expected interfering alternating voltages occur that in the first measurement phase the

DUT is connected to the measuring circuit under idle conditions, in the second measuring phase but the input of the measuring circuit is subjected to an adjustable load that in each Measurement phase that comes from the recorded and preprocessed

processed external voltage is integrated, and that the integration result of the second Measurement phase is subtracted from the integration result of the first measurement phase, the result of this Arithmetic operation forms the good or bad result of the measurement.

By inserting the inverting amplifier for the 2nd measurement phase, the circuit arrangement only needs a set of devices, in particular just an impedance converter and an integrator, and a single one Integration storage. This not only has the advantage that the effort can be kept low, but also, that no duplicated devices with identical measured values, such as gain factors, characteristics, etc., are required are.

Each measuring phase only includes whole-number periods of the expected interfering alternating voltages. Through this is only integrated over entire periods, so that the negative components of the parasitic oscillations oppose the cancel positive.

Compared to the circuit arrangements with transformers, the circuit arrangement according to FIG The invention also has the advantage that it can be made smaller and lighter.

Further advantages emerge from the example of the invention which is shown in FIGS is described, while FIG Measurements required are shown in FIG. 2 curves shown, which arise at the individual points of the circuit arrangement according to FIG. 1, in FIG a circuit arrangement is shown in which, for example, the circuit arrangement according to FIG will.

According to Fig. I, the disturbing external voltages settle from a DC voltage component UFG and an AC voltage component UFW together, the via an external resistance /? /% which is, for example forms at the point of contact, get into the telecommunications network. With this circuit arrangement will be For example, the speech wires in a coupling including any external lines of the Coupling network, which for example lead to another switching network, for the presence of foreign circuits examined.

The interference voltage UFW should / ÜR this example from glSEBahnsirom (16Vj Hz) and the technical change I ^ current (50Hz) resulting Da? S5 alternating current are included gan in a period of 3J§ # lBahnstromes three /-numbered periods of the technical ^l, is the Schwingungsi; duration, set a period of the track current, ie 60 ms for _ _jf fi1} ny measurement phase.

f '& The external voltages to be measured are tapped ^{at f:} point M by a test input circuit P

Jfen. Since the voltage against which the external fault resistance to be determined is related. in the individual case κ Ä 'is not known, instead of which only a possible range P fl can be used as a basis, the principle of s ^ measurement boils down to the internal resistance of a

ii) to qualitatively determine unknown voltage source. u n $ | Qualitanv means in this case that fine by the meter ι :: Γ · Pass / Fail statement regarding a pre-admit'p- is formed insu limit. This can only be carried out in two measuring phases, in the case of idling and load.

vijj The load case is formed by the fact that the ^ II measuring input with a load resistance RL against ■ $ Φ. ! a reference voltage U is applied.
S "f§tJ, The test input circuit P is followed by an impedance

-J ^ fund voltage converter which has a negative feedback f ^"r 'contains jOperationsverstärker Vl. Its non-inverting ψ irender input. Just v, ie the same inputs f'" t of the subsequent operational amplifier, a, {resistance RK to reference potential U laid . Task vdes impedance converter W is high, about to ΐ:,: fitting 4 ^ investigating external circuit resistance RF X .. "external voltages to avoid Sättigungsef-, j J ffekten to reduce and the subsequent integrator; 7 low impedance and can not be influenced from the outer * ^ To control network.

The inverter iV connected to the impedance converter VV occurs, activated via contact Kl, only during the second measurement phase, the load phase. * in action. As a counter-coupled operational amplifier V2 , it rotates the measurement voltage offered by the impedance converter in the phase by 180 ^c and at the same time amplifies it by the factor by which the input amplitude at point Af has fallen for the borderline case of the cross-circuit resistance. when the resistance value RF is equal to the load resistance RL . If the input amplitude is reduced to 50%, the gain factor of the inverter is Λ / i.e. 2.

This completely compensates for the amplitude that has dropped at measuring point M in the load. The inverter N thus enables a defined evaluation of an external fault resistance with regard to a predetermined limit value regardless of the unknown level of the external voltage applied to it.

The following integrator Γ consists essentially of an operational amplifier VZ, an integration memory C designed as a capacitor and an integration resistor composed of the resistors R 5 and R 6. The input side of the operational amplifier V3 is connected to reference potential U via a contact K 4 and is only released for control by the upstream stages for the duration of the two measuring phases.

The integrator T is followed by a comparator C , which is equipped with a free-running operational amplifier V4.

The comparator G is followed by a results memory E with a gate circuit L and with a 1-bit memory SPiür the measurement result at the output of the measurement.

The timely activation of the individual contacts as well as the output of the memory transfer pulse / takes care of the timing Z

The following processes take place in detail.

At the beginning of the test, the start signal is given to the time control Z via input 5. According to FIG. 2, this is the time r0. The fast-switching relays K 1 and K 3 are excited at the same time. The use of only such relays is advisable in order to keep the integration time exactly.
., The measuring arrangement is then connected to point M with contact K 1. In the presence of a fine interfering direct voltage UFG and an interfering alternating voltage UFW, a voltage curve arises there, as in curve 1 in FIG. 2 shown.

At the same time, the contact K 3 opens, via which, as well as via the resistor R 7, the capacitor C in the integrator T has previously discharged. The initial condition of the first measurement phase c / is thus achieved.

After a short settling time that lasts up to time / 1, during which the measuring arrangement has time to settle, the input voltage at measuring point M is evaluated in no-load operation, ie with negligible loading of the high-value input resistance Λ t of impedance converter W, up to time 12 . To do this, by opening contact K 4 for the duration of a 16Vj Hz penode (60 ms), the measurement signal weakened by the impedance converter W reaches the integrator T while bypassing the following inverter N (rest side of contact K 2) . The voltage curve 2 at input and 3 at the output of the inverter N smd is identical, as can be seen from FIG.

..j At the end of this first measuring phase d, when the contact K 4 closes again at time / 2, the integration capacitor C holds the result as a charging voltage value at the output of the operational amplifier V3 over the following switching phase until the beginning of the second measuring phase.

At the beginning of the switching phase at time 12 , the load resistance RL is applied to the measuring point W by actuating the contact K 5 and the test input circuit P is given the opportunity to adjust to the changed conditions. During this settling time, contact K 2 also switches the inverter Λ / into the cable run.

At time (3 , the second measurement phase begins as a load phase, the integrator T via contact K4 being activated again for a period of 60 ms This can be seen clearly in Fig. 2. The hatched areas ρ and q are enclosed by the curves 3, 4 and the reference voltage U. These areas represent the integration result of the two measurement phases q is smaller than the area p. so the curve 5 ends in the area m. that is above the reference line U, in the other case below this reference line.

The course of curve 3 clearly shows that the external alternating voltage, which limits the areas ρ and q , does not affect the size of these areas. It does not matter whether the interfering AC voltage UFW has been coupled inductively or capacitively into the line leading to point M.

The starting condition of the load phase e for the integrator T is that charge which was obtained as a result of the idle ^{phase d and which is 1} in the capacitor C-store. This storage device C is now reloaded up to a voltage f to be evaluated, which is lower in the case of permissible external leakage resistances, higher in the case of impermissible ones and, in the limit case, equal to the reference voltage U. In the first case the quantity / is in the range m, in the second in the range π and in the third it is equal to zero. Accordingly, the operational amplifier V4 in the comparator G switches its output to the other operating position in the former case. At the point in time / 5, the timing control Z applies a memory transfer pulse / to the gate circuit L, so that coincidences of signals are present at the inputs of the gate circuit for a positive statement. This sets the memory SP. In the second case, the comparator G does not switch through, the measured value memory SP is not set, which is evaluated as a bad statement. In the borderline case, the statement is indefinite.

This circuit can also be used by adding a further gate circuit and a memory expand so that a bad statement and / or the borderline case is also displayed.

In Fig.2 the reference voltage U is entered, which is a certain value away from the voltage zero (F.rdpotential). This difference is necessary in order to be able to determine earth faults.

As in Fig. 1, different values can be specified for the load resistance RL as limit values for the external resistance RF to be measured by a higher-level control if the measuring arrangement is expanded accordingly with a program-controlled limit value specification. In addition to the described qualitative determination of external conclusions with a good / bad statement with regard to a given limit value, depending on the additional effort, one arrives at a more or less fine quantitative evaluation if one undertakes a nesting of areas and approaches the effective value more and more in several successive measuring steps. The value RL reached in the last measurement, which provides the first borderline case A = 0 or the first positive statement, is then also the value of the resistor RF in the selected example (gain factor 2 of the operational amplifier V2 in the inverter N). Such a quantitative measurement is interesting, for example, when statistical measurements go beyond routine testing. Results are to be obtained. το The measuring arrangement described can also serve as an indicator for recognizing faulty or deliberately applied potentials. An example of this is shown in FIG. 3 shown.

A concentrator KT is connected to the coupling network KN via a longer line. One of several subscribers served by him is denoted by Tn 1, and his associated subscriber circuit is denoted by TS.

In addition, one of many subscribers Tn 2 is connected directly to the coupling network KN . Both lines leading to the coupling network KN can be influenced by external AC voltages UFW which, as shown, occur between the wires a and b . In addition, a resistor RFi is drawn between wire a and earth, which is intended to represent a short to ground.

In the coupling network KN , a resistor RFl is indicated, which symbolizes a connection to an adjacent, potential-carrying wire. A number of sets are also connected to the switching network KN , of which a switching set VS is shown here.

Finally, a test device Pr is also connected to the coupling network, which has an external fault measuring part FM, for example according to FIG. 1 contains. This external fault measuring part FM can optionally be connected to wire a or wire b .

With the help of this external fault measuring part FM it is not only possible to measure external voltages UFG within the coupling network KN and the lines connected to it, possibly influenced by interfering AC voltages, but other measurements can also be carried out over only one wire, in which the usual direct current loop measurement methods can be carried out lead to no result. For example, the opening of coupling contacts in the concentrator KT can be monitored. For this purpose z. B. in the concentrator KT via the subscriber circuit TS potential applied to the corresponding wires and the external fault measuring part FM causes to check against this from the coupling network KN via the concentrator connection line, which may be heavily influenced by interference voltage. Normally, between the measuring device | W and the counterpotential, there is the following rule: open? Kpnp ^: tkpritakt, the measuring arrangement FM then does not respond (positive statement). In the event of a hooked Kpppelkpntaktij, the measuring arrangement delivers a negative message, since the linear resistance of the subscriber circuit TS can be assumed to be significantly smaller than the resistance RF.

For this purpose 3 sheets of drawings

Claims (1)

Claims; NW ι, method for the determination of external DC voltages independent of interference voltage in! Pernmelde-, in particular telephone systems, with a good or bad statement, based on a predetermined limit value, characterized in that the measurement takes place in two measuring phases (d, e) , before which a settling time is provided so that the duration of each measurement phase (d, e) is measured according to the shortest period (60 ms) in which full periods of expected interfering alternating voltages (UFW; 50 Hz, I6V3 Hz) occur, that in the first measuring phase (d) the device under test (M) is connected to the measuring circuit under no-load conditions, but in the second measuring phase (e) the input (M) of the measuring circuit is subjected to an adjustable load (RL) that in each measuring phase (d, e) that from the ^ Recorded and preprocessed foreign chip fejt'nung (UFG, UFW) obtained signal (4) integrated J ^ ird, and that the integration result (9) of the second measuring phase (e) is subtracted from the integration result (p) J of the first measuring phase ^, the result of this arithmetic operation (C) forming the good or bad statement of the measurement. ■ • h 2. Circuit arrangement for performing the ^ method according to claim 1, characterized in that a load resistor (RL) during the second measuring phase (e) can also be connected to the object to be examined (M) \ n of a test input circuit (P) is that the object (M) via an impedance converter (W) and via a during the