DE2422798C3 - Time division multiplexing - Google Patents

Description

Reception point in relation to the time one Forwarding of the relevant PCM messages from the PCM receiver - where ilie ci; is respective PCM message signal forming, within a time faclis from cyclic to cinandci -following in Si transmitted to the pulse frame from the row fans Signal elements from the PCM transmitting station to the PCM receiving station transmitted in series and in the PCM receiving station within such a Zcilfach Weilergcleilet in parallel form - known. consequently in the PCM receiving station in Parallcll'orm present signal elements of a PCM news signal these signal elements together with a pulse one within each Zeitfaehs / umindesi query pulse sequence supplying two pulses for archiving a control signal are linked, with its Aulireien the development of the relevant signal elements is initiated. This well-known seduction makes it possible. PCM Naehriehlensignale, their times of occurrence within a relatively wide range in the wavy time spaces, from the respective To be able to forward PCM reception strlle without dall it is necessary to have to change the forwarding time within the respective time slots. The forwarding of the signal elements forming the respective PCM sewing signal can be started with Aul When a pulse occurs, a takeover pulse sequence occurs graze whose every pulse is between two pulses the Abrageimpulsfoh'c is emitted: hereby fluctuations in the point in time of the occurrence of the respective PCM news signal can occur around the point in time the occurrence of a pulse of the inquiry pulse train be balanced in the way. that depending on the overrun of the point in time at which in itself a change in the point in time at which the PCM message signals are taken over takes place within the following Zeillacher, the takeover point in question from the the first-mentioned point in time is relocated. d. h .. there for the takeover brings about a certain hysteresis.

The known method makes it possible in an expedient manner to compensate for phase fluctuations occurring on the transmission link, called litter, of the world that is malignant on the PCM transmission with reference to the relevant wording in the time-sharing exchange. In many cases, however, phase fluctuations caused by liuercrschcinungcn will not have to be compensated for; Ii. This can be due to the fact that the line multiplex transmission line and the time-division multiplex switching device work asynchronously with one another anyway. In such an F ^: aH, even when the known method is used, the risk of falsification of information transmitted or to be transmitted in a telecommunication network arises. The object of the invention is to describe a multiplex arrangement in which this disadvantage does not exist.

According to the invention, this is achieved in that the output in the internal word cycle or on the output side in the send-like external word clock also designed as a 1-word buffer memory is controlled such an I-word intermediate memory, which is controlled in the external word clock, at the beginning since ig in each one of the two evenly against each other staggered intermediate word tack is controlled and a further lciliingsindividiielle I-word conflicting rule is followed. the input side is controlled in the internal word clock, and that in each case a predetermined (irenz amount Exceeding or falling below phase difference between the pulse frames of an external wording And that of the currently effective inter-word measure in the pulse frame of the Zwisehcn-Woritaki Change to the other between-worit tact

■ ο between two time slots of two remote message time channels takes place, between whose time slots in the pulse frame of the external word clock a time slot one next to the actual telecommunication Zeilkanals provided special Zcitkanals is, whereby vermin

At most, a time subject of the next the actual I'ernnieldc target channels provided special Zcitkanals is suppressed or doubled.

The invention has the advantage of phase shifts between the pulse frames one on one PCM time multiplex transmission line authoritative l.eilungsbittaki or the corresponding external Word clock and the pulse frame of a maligebenden in a PCM time-division multiplexing system internal world clock without impairment of the information transmitted in the telecommunication channels even with asynchronous operation of Zeil muli iplex switching equipment and time division multiplex transmission line to be able to take into account.

In a further embodiment of the invention, a predetermined limit can be exceeded in each case Phase difference between a pulse frame of the receptive external word and a pulse frame of the inter-word clock in the pulse frame of the inter-word clock with a shortening of the time slot of one in addition to the actual lernmeldc time channels provided synchronization Zeil channel connected change to the other Zwisehcn-Wortiaki take place at the mitigation device side at most, the relevant line compartment of this Synchronisicr Zcilkanals is suppressed: each in the case of a phase difference between a pulse frame that falls below a predetermined limit of the receiving external word clock and a pulse frame of the intermediate world clock can in further Embodiment of the invention one in the pulse frame of the inter-word clock with an extension of the line compartment a synchronizing Zcitkanals provided next to the actual Fcrnmessage channels Change to the other intermediate word pitch take place, at most the relevant time subject of the next the actual Fernmeldc time channels provided synchronization time channel is doubled. the Mediation equipment rope suppression or doubling of a time factor of the z. B. in a PCM system 30/32 with 30 telecommunication time channels, a synchronization time channel and a signaling time channel already provided synchronizing Zcilka

The connection of the telecommunication time channels in the time-division multiplexing device is unaffected: in order to also enable normal use of the synchronization time channel, in a further embodiment of the invention, between the ⁶ S series-parallel converter and the 1-word converter following it. Intermediate storage a AusblcndccinrictHUiig and / odir between the parallel-write converter and the previous I-Worl-Zwtschcnvpeieher

652p

a fading device for fading in or out of in such a way in addition to the actual Eernmelde Zcilkiinälcn provided special time channel over the PCM time division multiplex transmission line transmitted or to be transmitted PCM-Wörlern be provided.

The invention can preferably be used in the case of the composition several asynchronously operated PCM time division multiplex transmission lines in a line multiplex switching facility, in In a further development of the invention, the output or input signal controlled in the internal word clock 1-word buffer of a plurality of PCM time-division multiplex transmission lines via / u the coupling cables associated with the connecting lines can be connected to a coupling switch with a common one Time division multiplex rails are connectable. In the case of this time-multiplex switching device, it can in particular be act to a concentrator, in which in a further embodiment of the invention each between those controlled on the output side in the internal word file 1-word buffer and the associated coupling switch a PCM-PAM decoder and between the input-sensitive 1-word buffer, which is controlled in the internal word cycle, and the associated Koppclschalicr a PAM-PCM coder is inserted and to which a concentrator Mulliplexschiene forming common time division multiplex rail a plurality of subscribers combined in the concentrator each via one with a PAM subscriber circuit connected Zeil channel switch is connected.

The invention is described below with reference to the drawings for example explained in more detail. It shows

E i g. 1 a time-division multiplexer. in which a multiplex arrangement according to the invention is realized.

E i g. 2 and 3 illustrate the position in time of clock pulse frames of a time division multiplex arrangement according to FIG of the invention and

E i g. 4 further circuit details.

E ig 1 shows schematically a time division multiplex concentrator to the extent necessary for understanding the invention. in which a time division multiplex arrangement according to the invention is implemented. This concentrator may combine a plurality of telephone subscribers TIn, each of which can be connected periodically in pulses to a concentrator time division multiplex rail ZMS via a time channel switch ZS connected to a PAM subscriber circuit TS . This should be connected to a central switching device, which is no longer shown in the drawing, via a switch shown in FIG. 1 PCM time division multiplex transmission line KM LG ML · Via the PCM transmission line. the. corresponding to the 4-wire operation, a receive time division multiplex line KML and a transmit time division multiplex line GMI. includes, the individual PCM words are each at a number of, for example, eight time elements comprising a number of time elements corresponding to the number of bits per PCM word, of time zones occurring cyclically one after the other in palsframes of a line clock rate defining the time elements on the time division multiplex transmission line KML-GML transferred in serial form. In the according to Fig.! the concentrator connected to the time division multiplex transmission line KML-GML , the one / one PCM words are transmitted in parallel within a time frame of time fields that occur cyclically one after the other in the pulse frame of an internal word clock that is decisive in the time division multiplex concentrator. In this case, a transmission-indiviclucller sericn-parallel-converter SlI 'is provided in the concentrator receptacle S, to which an input cable via a clock Meuerleilung wee in a receiving cable external word clock corresponding to the time division multiplex receiving line KML relevant transmission line KML

ίο and on the output side via a clock control line \\ / e ir each of two equally offset intermediate world clocks with the period de; internal word clock controlled I-word buffer HZ follows, which leads to a further individual lcitungs, on the output side via a Takisteuerlei development as in the internal word clock controlled -Spei rather Zl ; On the transmission side, a transmission line individual parallel-series converter S \ P is provided to which an output cable via a control line we:

precedes in a send scitigcn external word act driven memory Zl which corresponds to the line bit clock which is decisive on the line multiplex send line GMl. The output side driven in the internal memory Woritaki Zj is also formed as an I-word-Zvi-page memory, as is the ausgangsseilig driven in scndeseitigen external word clock memory ZH. This 1-word buffer memory ZH, which is driven at the input via a clock control line wys the one of the two equally offset intermediate text files, is connected to a further line-specific 1-word buffer memory / Z. the eingangsscitig übet a Takisteucrleitung "is in the inietnen Woritaki is driven.

According to E i g. The 1-word buffer ZJ , which is driven at the output or input in the internal word clock. IZ of a plurality of PCM Zcitmultiplex-Übercrtragungsieiiungen KMl.-GML via coupling switches kkm which can be actuated for the respective lines associated with coupling phases. mkg can be connected to the concentrator mulliplex rail ZMS , with a PCM-PAM decoder between the 1-word buffer Z) controlled on the output side in the internal word file and the associated coupling switch and a PCM-PAM decoder between the input-side 1-word buffer / A PAM-PCM coder is inserted into Z and the associated coupling circuit. The circuit arrangement according to FIG. 1 the connection with the time division multiplex rail ZMS is designed in such a way that the decoder or encoder kkm via a hybrid circuit G to a common coupling switch which realizes the coupling sounder mentioned. mkg are connected, which enables the connection to the time division multiplex rail ZMS.

For clock control is shown in FIG . 1 indicated that the line bit clock derived with the help of a flywheel circuit S from the time division multiplex receive line KML and decisive on the time division multiplex transmission line on the one hand to the serial-parallel converter S \ P and the ParaHei-serial converter SV via control lines be each as a transmission line cable Stcuertakt is supplied and on the other hand is entered into a counter ZeS with a count volume corresponding to the number of bits per PCM word, which thereupon at its output wc an external line bit clock corresponding to the time division multiplex transmission line

609653/339

Ά 652e

Outputs word clock whose clock mini-pulses each define the beginning of a digit or its first line element, the pulse frames of this external word clock lagging or leading by one time factor in relation to the line bit clock pulse frame. The internal word clock is shown in the circuit arrangement according to FIG. I derived from a clock generator BiCi operating with a clock frequency corresponding to the Lcitungsbitlakil'requcn / , whose clock pulses are input to a counter Z / 8 with a count volume corresponding to the number of hits per PCM word: from the output 3 of this counter Z corresponding to the third count step / 8 the internal word clock is picked up via a line wi , the clock pulse pulses of which in turn define the beginning of a time salmon or its first time element.

The two-word clocks are also derived from the clock generator BKJ via the counter XiS , namely according to P i g. I from the output I of this counting device Z / 8 corresponding to the first counting step via a line / a the one intermediate word file and from the fifth counting step responsive output 5 of the counting device Z / 8 via a line / b the other intermediate word clock. With the help of a bistable flip-flop Λ Β , one line ra or the other line / b is kept through to one of the clocks / / / leading the respectively effective inter-word clock via a logic circuit. to which the already mentioned clock signals w / e and n / s according to I i g. I connected directly.

At this point, a look at the drawings Fi g. 2 and 3 thrown, which illustrate the timing of the various clock pulses. In lines bc) in lines bc) the line bilt clock is shown: in lines uci ^ the receiving cable external Woritaki. In lines iit's ^ the scnd-side external word taki The illustrated direct connection of the clock control line u cc leading to the serial parallel converter SIP and the 1-word buffer / Z and the clock signaling line \\ cs leading to the Γ word buffer Z /: 'and the parallel serial converter .SV with the clock wc of cmpfangsseitige and the transmission-side external word clock übcrcin each other. in lines wi) of the internal Wortiakt is shown in a corresponding manner, and the line / a) and κύ / ¹ / intrinsically the two evenly staggered intermediate Wortiakte. the in each case to two line elements are offset from the internal word clock shown in lines wi) In lines ncc, / and ucs ^ isi indicated that a pulse frame each has 32 line compartments 0, 1, 2, ... 30, 3 1, where the time slots 0 may be the time slots of a synchronization line channel Ksynch provided in a PCM system 30/32 in addition to 30 Fcrnmcldc line channels and a signaling line channel .

In practical operation, the frequency and / or phase position of the l.ettiingshittakts decisive on the time-division multiplex transmission line KMl.-GML and that of the ßittakts of the clock generator HKi, which is decisive for the Kon / eniralorbbetrieb, never completely coincide, so that there are changes in the mutual phase position of the clock pulse frames of the PC'M-Zcitmuhiplcx transmission line and the time-division multiplex switching device connected to it. namely of the time division multiplex controller. Such changes will occur if several asynchronous time division multiplex transmission lines are interconnected with one and the same time division multiplex auxiliary devices operating in an internal clock.

LIm such changes without falsification of information to be transmitted in a telecommunication time channel To be taken into account is now in each case with a predetermined limit amount exceeding or falling below Phase difference, between the pulse

■ o men an external word act [lines wcc) in FIG. 2 and 3] and those of the currently effective Zwisehen-Woritakts [lines wzu. wzb) in Fig. 2 and i] in the pulse frames of the intermediate word clock, a change is made to the respective other intermediate word clock between two lines (31 and 1 in FIGS external timing [lines »cc) in FIG. 2 and 3] of a special time channel Ksynch , provided in addition to the actual i'ernnielde time channels K \ ... K 31, is located, with at most one line slot 0 of the special time channel Ksynch provided in addition to the actual notification time channels Ki ... K3 [ being suppressed on the distribution device side or is doubled. To an overwriting

² th of the predetermined limit will occur if the line frequency frequency is greater than the bit clock frequency of the clock generator BiC of the sound arrangement according to FIG. such relationships are shown in FIG. 2, in which the maximum permissible phase difference between a pulse frame of the receiving external word clock and a pulse frame of the intermediate word clock is indicated by 1. The predetermined limit will be undershot if the line bit clock frequency is less than the bit clock frequency of the clock generator BIO of the circuit arrangement according to FIG. is: such relationships are the illustration in FIG. 3, in which the minimum phase difference between a pulse frame of the receiving external word clock and a pulse frame of the intermediate word act mil K is indicated.

Consider first the case of a higher line bit clock frequency. In Fig. 2 will become such a Case in a wandering of the external clock pulse frames

[Lines bc). wecj \ to the left, where the phase difference 1 will increase.

In the left part of FIG. 2 it is assumed that the one intermediate word table according to line κ; »/ ¹ was previously effective, as shown in line ws.ac. w / bc) is indicated for the cell fans 30 and 31. Frgibi yourself now. that the phase difference between a pulse frame of the external word clock on the receiving side and a pulse frame of the inter-word clock exceeds the predetermined limit 1, an in the pulse frame of the inter-word clock with a shortening of the Zcitlachs 0 of the next to the actual telecommunication time channels K I ... K 31 provided synchronization Zcitkan; ils Ksynch connected change to the respective other intermediate word clock according to line sb) vorgcnom-

men. like this from line wsac. -w / .bc) can be seen ta F i g. 2 indicates that this happens when the seventh time element of time slot 0 of the receiving external word clock at least partially falls within a predetermined limit range, as shown in FIG

Line a) is shown. This limit time range can be formed by the first time element of the time slot 0 in the interim schcn-Woruakt / a and the eighth digit of the time slot 31 preceding it. For this purpose granular

New. as shown in FIG. I can be seen, the output I corresponding to your first Ziilschrili and the output 8 of the counting device ZiS corresponding to the light counting step in the circuit arrangement according to FIG. I via an OR gate to the Kingiing ./ dor bistable flip-flop circuit / Aß, whose clock input is supplied via an AND gate Usy each time a Unischaltimpuls is fed to the output of the I-word buffer IY. as well as an equivalence element connected to a .Synchronisierwortgeber Sy with the determination of the occurrence of the synchronisicrworis in the 1-word buffer memory tZ and thus the presence of the time slot 0 of the learning word file and one with an input to the output 7 of the '5 counter corresponding to the seventh counting step ZcS connected gate circuit LK unlock the AND gate Usy with the lirreich of the seventh counting step.

In the right part of FIG. 2 it is assumed that the other intermediate text according to line / b) has been effective so far. like this on line n / ac. w / bc) for the time slots 30 and 31 is indicated. The result is that the phase difference / between a pulse frame of the receiving external word clock and a pulse frame of the intermediate word clock overshoots the limit I. a corresponding change to the intermediate Wmiiakt / a) now takes place in the pulse frame of the intermediate word clock with a shortening of the time slot 0 of the synchronization time kanuIs provided in addition to the actual telecommunication time channels.

In the change to the other Zwisehen-Woritaki associated with a shortening of the time slot 0 of the synchronization time channel K \\ nch provided in addition to the actual telecommunication time channels Ki ... AT 31, at most the relevant line slot 0 of this synchronization time channel Ksynch becomes vermittlungscinrichtungsscitig suppressed. This is. as can be seen from line n i) of FIG. 2 results in which in the right part of FIG. 2 verdeutlichten change from intermediate word clock w / b to the intermediate word clock w / a of the case: avoided in the verdeutlichten the left part of Figure 2 changes from the intermediate word clock w / a to the intermediate word clock w / b is such a time multiple suppression . In the right part of FIG. 2 there is a change from the inter-word clock w / b to the inter-word clock w / a . when the seventh clock of time slot 0 of the external word clock wtv on the receiving side falls at least partially within a predetermined limit time range according to line b) , which may be formed by the first time slot of time slot 0 in the intermediate word clock / b and the preceding eighth time clock of time slot 31 . For this purpose, as shown in FIG. 1 it can be seen that the output 4 corresponding to the fourth counting step and the output 5 of the counting device Z / 8 corresponding to the fifth counting step can be fed via an OR element to the other input b of the bistable multivibrator AB .

1st unlike the previously considered conditions not sequence the case of a higher Lcitungsbittakifre- ^ ^0th rather, given the case of a lower transmission bit clock frequency , this will be reflected in the FIG. 3 in a wandering of the external clock pulse frame [lines bc). weej \ to the right, where the phase difference k will decrease.

In the lower part of FIG. 3 it is again assumed that the one intermediate word clock according to Zeiley.a) was effective so far. like this in the line »vac. w / bc) l'ü the time slots 30 and 31 is indicated. If you only see that the phase difference between a Piilsrahnici of the receiving-side external word takis irtv un <a pulse frame of the intermediate word w / a dii falls below the predetermined limit Ar, then a pulse frame of the intermediate word rate with a lengthening of the time slot 0 of the next to the Eigencntlichei Fernmelde-Zeitkanälcn KX ... / c 31 provided synchronization time channel Ksynch connected changes to the other inter-word clock w / b made, as shown in line wzac. w / bc) in Fig. j sees is borrowed. In Fig. 3 it is indicated that this »e layer when the eighth Zcitelcmeni of the time box 0 de * receiving-side external word takis ii cc at least partially in the border line area according to line a) . Correspondingly, in the right part dei Γ i g. 3 assumes that so far the other intermediate work cycle according to line // ^ effective wa- and cUil.l a corresponding change to the intermediate work cycle according to line / a) associated with an extension of line compartment 0 is made if the eighth time element of the time slot 0 of the emplangsseiligeii external word takis wcc falls within the limit time range according to line b) . In the circuit arrangement according to FIG. 1, the limit time ranges are again determined by the at the inputs ;; and barren flip-flop AB occurring signals defined: the Takieingang the flip flop AB is now already mentioned above, the AND gate Usy each straight then supplied to a switching pulse when the equivalence gate mentioned in turn to the presence of the time bin 0 in the external Wortiakt and the gate circuit LK connected with one / wide input to the eighth counting step corresponding output 8 of the counting device Zc 8 unlock the AND element l> \\ when the eighth counting step is reached.

In the case of the change to the other intermediate Woi itaki associated with an extension of the time slot 0 of the synchronization time channel Ksync ^h provided in addition to the actual telecommunication line channels Ki ... K 31, the relevant time slot 0 of this synchronization time channel Ksynch switching device is at most ig doubled. This is. as can be seen from the line wi) of FIG. 3 results, in which in the left part of FIG. 3 illustrated change from the inter-word clock w / a to the inter-word clock w / b the case: in the right part of FIG. 3 illustrated change from the inter-word clock w / b to the inter-word clock w / a , such a time slot duplication is avoided.

The communication device suppression or doubling of the synchronization time slot leaves the information transmitted via the communication device in the time fans of the remote communication time channels unaffected. When connecting the connection, it is only necessary to ensure that this connection also takes place within the relevant time slot of the internal word cycle when a pulse frame of the internal word cycle according to FIG. 2 on the right or 3 on the left experiences a shortening or lengthening by a time factor. 1 at. that the coupling switch kkm. mkguna the time channel switches ZS are each controlled with the help of a circulating memory of the length of a word clock period, so only need the memory circulating time once for a time period corresponding to a word clock period by one time element at the points in time in question

652e

shortened b / w. to be extended.

A Schahungsprin / ip enabling this is shown in FIG. 4 can be seen. In Fig. 4 is a for the periodic pulse-wise control of Koppclschaliern b / w. Time channel switches usable address number storage devices are designated by //, which, when a corresponding output is connected via a return tray Sn to the storage input, may have a circulation T corresponding to the Woritaki period. In a time skilled corresponding Absland front of and behind said memory output, the .Speicher i ι two further memory outputs, the first and the second HS via a return Schaller Sv with the Speichereir ^ is connectable via a return switch Su. Normally the feedback switch .Vn is transferable, so that the memory circulation is equal to 7. From the left part of FIG. However, control circuit shown in Figure 4, the forth Rückluhrsehalier Sn also be opened, and it may optionally return eggs Schaller .Si; or the RürM'iÜiizo switch .S "i can be closed instead, so that the run time for the address circulating memory // is shortened or lengthened by the length of a line. The control circuit has two outgoing lines u / iind iv /. which may correspond to the clock lines of the circuit arrangement according to I 1 g. 1, which are designated in the same way * 5, so that on the line \\ / the respectively effective intermediate wording according to the lines ιν /.- ι. \\ / b) in Figs. 2 and 3 as well as on the line u / the internal word clock according to the lines wi) occurs in I 'i g. 2 and J. As can be seen from the right-hand part of Fig. 2, a a one-time shortening of the memory circulation line requiring suppression of a time slot 0 of the internal word clock to the effect that no clock pulse of the internal word clock occurs between the two clock pulses of the inter-vision word clock corresponding to the similar 0 and I. Line such Constellation is shown in I ig. 4 with the help of one of the Z wischcn-Wortiakt-Inipulse pay the. by an internal word-reading pulse in each case / u reset counter 2 / with the counting volume 2, which unlocks a subsequent AND element for the next internal word clock pulse when the / wide counting step is reached, by means of which a subsequent bistable flip-flop for the duration is activated by the timing of the internal clock; this flip-flop are over their Ausgangslcitiing u a Kntriegelungssi giial to the feedback switch SU and a Spcrrsisnal to ilen return switch Sn at, so that the I Imlauf / ince the address circular memory (/ ν for the duration of 31 time slots of the internal bit clock for the duration of a Zeilfachs erkür / t. The duration of Jl time slots of the internal bit clock is determined with the help of a counter 31 / which counts the corresponding pulses of the internal bit clock and which resets the mentioned bistable flip-flop after the last counting step monostable multivibrator for the duration of a time salmon, so that this flip-flop s monoslabilc a blocking signal to the per se from the line and via its output line ago no longer locked feedback Schaller .V /) outputs. This ensures that the addresses in the circulating memory U then circulate again in the correct phase position with the normal memory space. As shown on the left part of the I i g. j results, a duplication of a / salmon 0 of the internal word taki, which requires a one-time extension of the storage circulation line, has the effect of this. that between two clock pulses of the internal Wontakts no Taklimpuls of the intermediate Wontaki occurs. Line such a constellation is shown in the circuit arrangement according to FIG. 4 with the help of a counting device 2 / mn, which is acted upon by the line wi with counting pulses and which can be reset by the l.eituna w / her, the counting volume 2, which activates a subsequent bistable toggle switch for the duration of 32 line compartments when the second counting step is reached. During this 32 line fan-out, i.e. for the duration of a pulse frame, the bistable multivibrator emits an anti-lock signal to the feedback switch Sv and a blocking signal to the feedback switch S / 7 via its output line ν, so that the internal Word clock, ie for the duration of a clock pulse frame, the circulation time of the circulating address memory // is extended by the duration of a time slot. The 32 time slots of the internal Woniakis are counted by means of a counter 32 /, which resets the mentioned histable multivibrator to the idle state when the 32nd counting step is completed.

In L i g. 2 is to be clarified with a marking of the clock pulses of the Zeillacher 0 of the internal word takis. that these W01 ttaklimpulse in the circuit arrangement according to FIG. 1 can be suppressed when the 1-word buffer // is activated on the input side. G In the circuit arrangement of I "1. 1 thereto between the wi the internal Woritaki leading Taktlcitung and η the I-word buffer // f input side-addressing Taktsteuerleitnng is a locking member Gis inserted, which by a bislabilen multivibrator JS forth respectively from first during the time slot 0 of the external Woriiakis on the clock w / ocurring

/ wipe word clock pulse until the first after the line 0 of the external world clock on the clock system 11 / occurring inter-word clock pulse is held in the blocked state, so that the PCM word to be transmitted in line 31 for a further / eil I'ach-Zeiispannc remains stored in the 1-word buffer //. From the / rush w / us). iv / fts / der I i g. 2 and 3 it can be seen that this also applies in a corresponding manner to the transmission-line transmission of the relevant Pt M-word with the intermediate word clock. From the / rush u es / = der F i g. 2 and 3, however, it then becomes clear that the PCM word to be transmitted in the time slot 31 with the send-like external word clock is still not passed on, rather that the line slot 0 is instead on the time input plcx control line CML (see C i g. I) of the synchronizing Zcitkanals Ks \ nch can be used normally. For this purpose, the circuit arrangement according to FIG. 1 between the Parallcl-Scrien converter S \ P and the preceding 1-Worl-Zw ischcnspeicher ZE an F-inblendeinrichtung is provided, which is provided in addition to the actual telecommunication line channels synchronization Zeiikaiial KsMicli over the PCM Zcitinultiplex transfer line Synchronization word to be transmitted is displayed in time slot 0 of the external word clock that is sent. As can be seen from I "i g. I, this Linblendecineinrichtung can consist of a logic circuit, which is controlled by a counting device Zc 32 counting the time slots of the external word clock with a count volume corresponding to the number of line channels, each in line 0 of a pulse frame of the external word clock on the send side a Synchronisicrwortgeber .S) and in the other line compartments of the PuIsrahmens the I-word buffer Zl: with the

Parallel-to-serial converter .S '//' connects. Correspondingly, the serial-parallel converter SV and the following I-word / wi page memory IzX can also be used to hide a special channel via the PCM in addition to the actual learning channels. ZoiimuliipIcvObenragungsleiiung transmitted PCM words, such as a Svnchionisierworts or a Signalisici vuis. be provided as described in ii g. I is only hinted at.

/ ti that from the graphic representation u. -.! ei l · i g. 1. 2 and i apparent coincidence of the env.ifangssciiigcn external clock with the sendcscitigen external word clock. of the extensive inter-word taki with the transmission-side / wipe-woritakl and the internal work on the receiving end with the internal wording on the sending end is still on it pointed out that this representation is based on the Voraiissei / ung based, duU in the one further to the right Part of the circuit arrangement according to I- i g. I just before- ao obviously small processing b / .w. Run times occur. If this requirement is not met, then surrender there are still corresponding phase shifts of the transmit-side word clock pulse frames compared to the Woriiakl pulsiahmen on the upstream side.

Ks should also be noted in particular in the preceding Characterization of the finding / was in each case separate from an output control a preceding I-word buffer (.series-parallel converter, «-PCM C oilers) and an input cable control of a subsequent I-word buffer (parallel series Converter. PCM PAM decoder) is spoken, as in I- i g. 1 indicated Ut. that one atisgapgsseiiigc and input-side control but can also be realized in such a way that concretely for example, only the subsequent I-word buffer memory input rope is controlled.

Finally, it should also be pointed out that when several PCM Zeiinuiliiplex transmission lines KML-CM1. in Γ "i g. I with a common time division multiplex rail XMS in I" i g. I via / u coupling phases associated with the relevant lines in the case of coupling switches kkm. mkg. in I i g. 1, of course, a separate coupling phase, offset from the other coupling phases, is to be used within each time slot for each transmission line. what happens when controlling the coupling holder and also the Zeilkanalsehalier ZS'in l ^r i g involved in the relevant connections. I must be taken into account accordingly.

For this purpose 3 sheets of drawings

Claims (5)

Patent claims: 1. Double multiplex arrangement / to compensate for changes in the mutual phase position of the clock pulse frames of a PCM time multiplex transmission line, via which the one / one PCM words each in a time slot comprising a corresponding number of time elements from in pulse frames of one decisive on the time multiplex transmission line , the time elements defining the l.leitungsbiltakts cyclically successive time fans are transmitted in .Serienform, and a time-division multiplex switching device connected to it, in particular a concentrator. in which the one / one PCM words are transmitted in parallel form within a time slot from in 'pulse frame of an internal worüjikis decisive in the time-division multiplexing unit, cyclically occurring time fans, with a transmission line individual unit individual in the time-division multiplexing unit being received with a subsequent 1-word buffer on the input side in a 1-word buffer on the input side, which corresponds to the input-side external word taki that corresponds to the time-division multiplexing reception line, which is on the output side in one of two evenly offset intermediate word ticks with the period of the internal wontakts is controlled and leads to a further line-specific, output-side memory controlled in the internal word clock, and / or transmit-side a transmission line-specific parallel service converter with a preceding, output side in a de m on the Zciimuhipli-x transmission line authoritative l.citungsbiliakt corresponding transmission-side external Worilakt controlled memory is not seen, characterized in that output in the internal word file (wi) or output side in the sending-side external word taki (wc) also as an I-word Temporary memory (Z / or ZU.) Are controlled, such a 1-word buffer (ZH) controlled in the external word clock (wcs ) on the input side in the one of the two equally offset intermediate word clocks (ιιλι, η / TV is controlled and a further line-specific 1-word buffer (IZ) is connected downstream. which is controlled input in the internal word clock (ui) , and that in each case with a given (ircnz amount (I. k) above or below a phase difference between the pulse frame of an external network (wcc) and those of the currently effective double word clock (w / u. w / b) in the pulse frame of the intermediate world (w / u. w / b) cm change to the other inter-word rate (w / b, w / u) between two time fans (31. I) of two i'ernmelde-Zeilkaniilc takes place, between the Zcitflächen [31. I) in the pulse frame of the external word clock (wcc) a line compartment (0) a special provided in addition to the actual l-'crnmcldc-Zcitkaniilen (K i ... K 3i) Time channel (Ksynch) , with veriiiitllungseinrichtungsscitig at most one time slot Jes in addition to the actual Fernmclde-Zeiikaniilen provided special time channel (K \\ nch) is suppressed or doubled. 2. Zeitmultiplexayiordnupg according to claim I. characterized in that in each case with a predetermined limit (I) exceeding phase difference / between a pulse frame of the receiving external word clock (wcc) and a pulse frame of the intermediate world (w / u. W / .b) v \ n in the pulse frame of the Zwisehen wording (w / u, w / b) with a shortening of the time slot (0) of a synchronization or signaling time channel (Kysnch) provided in addition to the actual telecommunication time channels to the other Intermediate word clock (w / b. Tv / raj'statit'indet. In which the switching equipment line at most the relevant time slot (0) of this synchronization or signaling time channel (Ksynch) is suppressed. 3. Zcitmultiplexeinrichtung according to claim 1 or 2, characterized in that in each case a predetermined limit (k) unierschreitcndcn phase difference between a pulse frame of the cmreceiver-side external word clock (wcc) and a pulse frame of the intermediate word clock fit / j, w / b) a in the pulse frame of the Zwischencn-Woritaki (w / u. w / b) m \\ an extension of the line compartment (0) of a synchronization or signaling time channel (Ksynch) provided in addition to the actual telecommunication time channel (Ksynch) to the respective other intermediate -Word clock (w / b. W / u) takes place, in which the switching device side at most the relevant time slot (0) of this synchronization or signaling time channel (Ksynch) is doubled. 4. Zciimultiplex arrangement according to claim I. characterized in that one between the Scrien-parallel converter (SIP) and the subsequent 1-word buffer (EZ) provided Ausblcndcinrichtung and / or between the parallel-serial converter (SIP) and the preceding 1-word buffer store (ZH) in front of a fade-in device in a special time channel (Ksynch) provided in addition to the actual Fcrnmelde time channels over the PCM time division multiplex transmission line from or fades in PCM words. 5. Time division multiplex arrangement according to claim I, characterized in that the output or input scitig in the internal word clock (wi) controlled I-word buffer (Z /. / Z) of a plurality of PCM-Zeiimultiplcx-transmission lines (KML-CML) over coupling switches (kkm, mkg) mh of a common time-division multiplex switch (ZMS) which can be actuated to the respective lines associated with coupling phases can be connected. b. Zcitmultiplexanordnung according to claim 5, characterized in that in each case between the atisgangsseitig in the internal Woritakt (wi) driven I-word buffer (ZJ) and the associated Koppclschalter (KKM), a PCM-PAM-Decodcr and between the input side in the internal Woritakt (wi ) controlled I-word buffer (/ Z) and the associated coupling sounder (mkg), a PAM-PCM coder is inserted and that a plurality of thus combined in a concentrator on the common time multiplier (zms) forming a concentrator mulliplcx.schienc Telephone subscribers (TIn) each via one with a PAM Tcilnchmcrschaliuntr (TS) connected Zeilchannel switch (ZS) is connected. The present invention relates to a cellular module assembly To compensate for changes in the mutual phase position of the Takipulsrahmen a PCM-Zcitniultiplcx-Ubertragungslciiupg. practice the a / one PCM word each in a corresponding one Number of time elements comprising line fold of in pulse frame one on the time multiplex transmission line decisive Lehungsbittakts thinning the Zcitelemente cyclically successive Transfer the occurring time fans in Scrienform and a time division multiplex switching device connected to it. especially one Concentrator stage in which the individual PCM words each in parallel form within one line of one in the pulse frame in the time division multiplex switch authoritative internal Wortiakis cyclically successively occurring line subjects are transmitted, wherein in the line multiplex switching device A transmission line-specific at the receiving end Series-parallel converter ιίίit follow to the. on the entrance side in one on the Zeiinuiltiplev Receiving line authoritative Lcitungsbittaki corresponding Receiving-side external Wontakt controlled I-word buffer, which is output-citig in each one of two evenly offset intermediate Woriiakicn with the period of the internal word clock is controlled and to a further line-individual. output cable in the internal word clock controlled memory leads, and / or sendescitig a transmission line individual Parallcl-serial converter with a preceding, outputting in one of the on the Zcitmultiplex transmission line decisive Leiuingsbiitakt corresponding sendeseiligcn external word clock driven Memory is provided. The task of telecommunication switching systems is the establishment and subsequent release of connections between spatially separated telecommunications stations, namely the participants of the relevant Switching system that exchanges messages want to make. The Fcrnmcldcstcllcn are for this purpose via individual telecommunication lines to the switching system connected: within the actual central switching facility are connected to each other Telecommunication lines to be connected via a suitable coupling arrangement for the duration of the desired connection / usammcngeschaltci, which means a multitude of two possible ones Telecommunication stations interconnecting telecommunication transmission channels through the central Switching device runs. In conventional telecommunications, particularly telephone exchanges finds a transmission of temporally continuous analog signals in spatial separate transmission channels instead. Make newer telecommunication systems not of the multiple space principle, but of the multiple multiplex principle, whereby temporally discontinuous Analog signals are transmitted. Recently, telecommunication exchanges are also increasingly being acquired Meaning in which a transmission of digital signals, which are also discontinuous in time takes place; in this context has special The meaning of the pulse code modulation (PC M) attained! In which the amplitude instantaneous values of the speech signal are mapped periodically apart from one another by means of binary words which will then protrude. The actual central switching device forms only part of the entire switching system: the aforementioned telecommunication lines running from the central switching device to the subscribers and the subscriber parts themselves form another part To keep outlay small, it is generally known to prefer parts of the central switching device and to arrange them in the vicinity of a group of participants as a so-called concentration and only a number of simultaneous connections corresponding to / ah) of communication channels between these concentrators and the central switching device to be provided, which at the same time also reduces the number of devices to be provided in the central switching device per transmission channel accordingly, as is already the case with the introduction of Vorwä hlcrn and call seekers !! is known in conventional switching systems. In this context, it is known to combine the subscriber lines of a time-multiplexing system in correspondingly operating on a time-multiplier basis by connecting the line of each participant involved in a connection via the line-specific simultaneous channel sounder, periodically pulse-wise to a time multiplexer and disconnecting the time multiplier and multiplexer central switching device to provide only one time division multiplex transmission line, with a PAM-PCM conversion taking place between the time division multiplex concentrator and time division multiplex transmission line, so that. viewed from the transmission line. Concentrator and central switching device represent PCM time multiplex switching centers (see BST) XXXVIII. [1959] 4. 909 ff. 914). Prerequisite for proper connection through-connection in a PCM Zcitmultiplexvermittlungsstclle is that the respectively to be switched or durchgeschaltetcn binary words are each available at the correct time for their connection or further transmission stand. This requirement is not met from the outset because the frequency and / or phase of the in of such a switching device, the decisive word clock at least not automatically with the frequency or phase of the one to the PCM time division multiplexing facility in question or outgoing PCM time multiplication transmission line decisive word clock coincides, so that there are / u shifts of the pulse lines of the on the PCM-Zcitmultiplcxübcriragungsleilung authoritative external word tactics in relation to the pulse frame of the authoritative in the PCM Zcitmultiplexvermittlungseinrichtung internal word clock comes. In this context, there is a method to compensate for, in particular, due to changes in runtime in the transmission of PCM message signals from a PCM terminal via a transmission link changes in the time of occurrence of the relevant PCM message signals in the PCM