DE2322827C2 - - Google Patents

Description

The invention relates to a halftone image display device according to the preamble of the main claim.

Such a device is known from US-PS 35 90 156. The halftone levels are achieved by that the lighting condition at a different Maintain number of parts of an image period becomes. The maximum brightness is when it is lit. reached in 64 out of a total of 525 lines. The The brightness of the image is therefore insufficient. Furthermore is a separate, for each intermediate level of the gray scale complex storage arrangement required.

It is therefore an object of the invention to produce a halftone To create an image display device which is a display with great brightness. This task is accomplished by solved the device according to claim 1.

In the following the invention with reference to drawings explained in more detail. It shows

Fig. 1 is a schematic view of a conventional display device (plasma display device);

FIG. 2 shows graphical representations of the control voltages for the display device according to FIG. 1;

FIG. 3 shows graphical representations of waveforms for the operation of the display device according to the invention;

Fig. 4 shows an embodiment of the display device according to the invention;

Fig. 5 is a Y -Steuerteil another embodiment of the display device according to the invention and

Fig. 6 is a table for explaining the operation of the display device.

Switching on and off in conventional plasma display devices will first be described. FIG. 1 shows a schematic view of a conventional plasma display device, and FIG. 2 shows the course of the control voltage for the operation of this conventional plasma display device. Fig. 1 shows X - control electrodes 2 and Y 3 -Steuerelektroden a display panel 1. These are connected to control circuits 4 and 5 . Accordingly, the respective picture element, which is defined by the crossing point of an X control electrode 2 and a Y control electrode 3 of the display panel 1 , is subjected to a voltage as shown in FIG. 2C. The amplitude of the sustain voltage is chosen such that it is large enough to maintain the discharge until the respective picture element is switched off, and on the other hand it is not sufficient to switch the picture element on. Accordingly, the switched-on picture element maintains its lighting state due to the repetitive, intermittent discharge according to FIG. 2D until the picture element is acted upon by a switch-off pulse. This is referred to as a memory function of a display device.

If according to FIG. 1, an image element such. B. X ₂ Y ₃, is turned on, the control electrodes 22 and 33 in question , which intersect at the picture element in question, a switch-on pulse P is supplied. This switch-on pulse is superimposed on the maintenance voltage. This is shown in Figures 2A and 2B. The switch-on pulse has an amplitude which is not sufficient to switch on the picture element, ie which does not reach the amplitude V _f required for initiating a discharge. The picture element is only switched on when both the associated X electrode 2 and the associated Y electrode 3 are simultaneously subjected to a switch-on pulse P. Then only after Fig. 2C, the voltage across the pixel X ₂ Y ₃ at the intersection of the two electrodes exceeds the voltage V _f . Accordingly, only this picture element X ₂ Y ₃ is turned on without the switching state of the other picture elements being disturbed.

To switch off the picture element X ₁ Y ₃, a switch-off pulse Q is provided. With this switch-off pulse Q, the electrodes are applied to the region III in Fig. 2A and Fig. 2B indicated time. There are e.g. B. the two control electrodes X ₂ and Y ₃, which cross on the picture element X ₂ Y ₃, applied. If the amplitude and the duration of this switch-off pulse are selected appropriately, then only the picture element X ₂ Y ₃ is switched off without the other picture elements being disturbed thereby.

If all picture elements in a display device together with a maintenance voltage the desired picture elements can be replaced by a narrow pulse in the on or in the off Condition.  

For the following description it should be assumed that all picture elements with the maintenance voltage are applied so that only the switch-on pulses and the switch-off pulses are considered. Hereinafter is now the halftone image display device according to the present Invention are explained.

When a picture element of the scoreboard is turned on once , the lighting status is maintained until the picture is off. Thus, the average Brightness of the red dot by regulating the Time between the switch-on pulse and the switch-off pulse to be controlled. It will control the average Brightness made during an image period.

Fig. 3 shows a graph illustrating the operating principle of the halftone image display device according to the invention. A denotes an input video signal. B denotes a switch-on control pulse with which the picture element on the k- th key line is driven. C denotes a switch-off pulse for all picture elements on the kth key line. D denotes the lighting state of a picture element on the kth key line. The Fig. 3 refers to the picture element i k on the scan line. Here, a sequence of three images F ₁, F ₂ and F ₃ or three output signals F ₁, F ₂ and F ₃ is considered to generate these three images. To simplify the description, it should be assumed that there is no interlacing method. If an interlaced method is used, the following explanation of the invention applies accordingly, whereby a field is regarded as an image. The instantaneous value v of the input video signal A, which is assigned to the picture element under consideration, can be expressed as follows:

v = K ( a ₁ w ₁ + a ₂ w ₂ + a ₃ w ₃),

where the symbols a ₁, a ₂ and a ₃ stand for 1 or 0.

To simplify the description, it should be assumed that a purely binary code is used, where w ₁ = 1; w ₂ = 1/2 and w ₃ = 1/4 applies. K means a conversion factor (constant). As shown in FIG. 3B shows a turn-on pulse is then formed, if a ₁ has the value "1" in the first frame F ₁ and A ₂ in the second image F ₂ or a third image in ₃ F ₃.

According to Fig. 3C, a turn-off pulse is independent of the value of a ₁ and A ₂ and A ₃ for a period of T seconds, counted from the beginning of the switch-on pulse for the first image F ₁ or after a period of T / 2 seconds , calculated from the start of the switch-on pulse for the second picture F ₂ or after a period of T / 4 seconds, calculated from the start of the switch-on pulse for the third picture F ₃, where T means a certain period of time which is shorter than the picture period T _F.

The luminescence state of the relevant picture element in the first to third picture F ₁ to F ₃ is shown in Fig. 3D. The total luminescence can be given by the expression a ₁ · T + a ₂ · T / 2 + a ₃ · T / 4. The average brightness averaged over the three images F ₁ to F ₃ can be expressed as follows:

B = K ′ ( a ₁ T + a ₂ T / 2 + a ₃ T / 4)
= K ′ ′ ( a ₁ + a ₂1 / 2 + a ₃1 / 4)
= K ′ ′ ′ ( a ₁ w ₁ + a ₂ w ₂ + a ₃ w ₃),

where K ' to K''' are constants.

The average brightness, averaged over the three images F ₁ to F ₃, is proportional to the input video signal A encoded with 3 bits, so that one can reproduce 8 different brightness levels. This principle is the basis of the halftone image display device according to the invention. This can be achieved with a display panel which has only two different operating states, namely a luminescent state and a non-luminescent state.

An embodiment of the display device according to the invention will be explained in more detail below with reference to FIG. 4. An input video signal 100 is keyed and encoded by an encoder 62 under the control of a clock 60 . If a purely binary encoder is used as the encoder 62 , then coding is carried out with three bits ( a ₁, a ₂, a ₃). No clock frequency that meets the following condition is selected:

f _c = N _H f _H / (1- α )

where N _{H is} the number of picture elements shown on a horizontal scanning line, f _{H is} the horizontal scanning frequency and α is the blanking ratio.

On the other hand, a vertical synchronizing signal reaches a frame counter 63 via a line 102 , so that signals for the frames F ₁, F ₂, F ₃ are formed in succession. The output signals of the encoder 62 are selected by a logic circuit (gate circuit) 65 , the control being carried out by the output signals of the frame counter 63 . The first bit a ₁ of the output signals of the encoder 62 is the first image F ₁, the second bit a ₂ of the output signals of the encoder 62 is the second image F ₂ and the third bit a ₃ of the output signals of the encoder 62 is the third image F ₃ assigned. The first bit a ₁ and the second bit a ₂ and the third bit a ₃ are shifted into a memory register 40 , which is a shift register and whose number of bits is equal to the number of picture elements N _H. With each cycle on a line 61 , the output signals of the encoder 62 reach the shift register 40 via the gate circuit 65 . Accordingly, at the end of a horizontal scan period, all signals of the horizontal scan line are stored in the memory register 40 . The signals are transferred to a control register 41 by a horizontal synchronizing signal H _D via an input 101 . The signals of the next horizontal key line are subsequently stored in the memory register 40 .

A control circuit (driver circuit) 42 is formed by a switch arrangement with a number of switching units which corresponds to the number of picture elements N _H. A switch-on pulse generator 70 generates switch-on signals on a line 71 , which are passed through on the basis of the output signals of the control register 41 and which are applied in parallel to the X control electrodes 2 of the display panel 1 . On the other hand, the switch-on signal arrives at the Y control electrode 3 , which corresponds to the horizontal scanning line of the video signal A. This is done by actuating a further control circuit 51 . Accordingly, z. B. in the case of the first image F ₁ the first bit a ₁, which comes from the output of the encoder 62 , via the memory register 40 to the control register 41 , so that the picture elements on the key line, for which a ₁ has the value 1, switched on in parallel will.

Accordingly, the picture elements of the overall picture are switched on depending on the bits a 1 defined above, to the extent that the Y control electrodes 3 are progressively scanned for each horizontal synchronizing signal by a first key circuit (switch-on key circuit) 50 . In the second or third picture, the picture elements are switched on in a corresponding manner according to bits a ₂ or according to bits a ₃.

The key operations for switching on and switching off the picture elements are explained in more detail below. In the embodiment according to FIG. 4, the first key circuit 50 and a second key circuit (switch-off key circuit) have 52 bit numbers which are equal to the number N _{v of} the lines N _{v to be} scanned on the display panel. The switch-on key circuit 50 and the switch-off key circuit 52 are formed by shift registers, the shift clock corresponding to the horizontal synchronizing signal H _D on line 101 . The Y control circuit 51 is a switch arrangement with N _v outputs. The nth stage of the Y control circuit 51 passes the switch-on signal on line 71 , which is provided by the switch-on pulse generator 70 , on the basis of the n- th output signal of the switch-on key switch 50 , so that a switch-on pulse is produced. On the other hand, the nth stage passes the switch-off signal on a line 76 , which is provided by a switch-off pulse generator 75 , on the basis of the n- th output signal of the switch-off key circuit 52 , so that a switch-off pulse is produced.

In the device according to FIG. 4, the first bit of the switch-on key circuit 50 has the value "1" for each vertical synchronizing signal on a line 102 . This bit "1" is shifted by one level for each horizontal synchronizing signal on line 101 . Accordingly, with each horizontal synchronizing signal on line 101, the Y control electrode 3 of the display panel 1 is selected for one line by the Y control circuit 51 , which is controlled by the switch-on switch circuit 50 , and the switch-on pulse is applied to it.

The switch-off process will be explained below. For this purpose, the output signal from stage m, stage m / 2 and stage m / 4 is taken from the switch-on switch circuit 50 , ie it becomes the output signal of stage m for the first image F ₁ or the output signal of stage m / 2 for the second image F ₂ or the output signal of stage m / 4 for the third image F ₃ selected by a second gate circuit 66 which is controlled by the signals for the images F ₁, F ₂ and F ₃ of the frame counter 63 . These selected signals are given in the first stage of the switch-off button circuit 52 , where m = Tf _H , where T and f _{H have} the meaning given above.

In the switch-off pushbutton circuit 52, there is a shift by one step each time a horizontal synchronizing signal on the line 101 . Accordingly, the nth signal of the switch-off button circuit 52 is delayed by the following time period compared to the nth signal of the switch-on button circuit 50 :

T seconds, ie m bit in the first picture F ₁,
T / 2 seconds, ie m / 2-bit in the second picture F ₂ and
T / 4 seconds, ie m / 4-bit in the third picture F ₃.

Accordingly, the Y control circuit 51 controlled by the switch-off pushbutton circuit 52 supplies a switch-off pulse to the respective Y control electrode 3 after the following period of time, calculated from the start of the switch-on pulse:

T seconds for the first image F ₁,
T / 2 seconds for the second picture F ₂ and
T / 4 seconds for the third picture F ₃.

The amplitude of the switch-off pulse with which the Y control electrode 3 is applied is selected such that all activated picture elements which are assigned to the respective Y control electrode 3 are switched off. All picture elements assigned to the respective Y control electrode 3 are thus set to the switched-off state independently of the video signal A.

As mentioned above, FIG. 4 eg invention. B. the picture element of the row i on the key line k controlled such that it z. B. switched on and switched off again after T / 4 seconds. In the first picture, the switching on takes place based on the output signal with a ₁ = 1 of the encoder 62 , and the switching off takes place after T seconds. In the second picture, compliance with the output signal with a ₂ = 1 of the encoder 62 takes place, and the switch-off takes place after T / 2 seconds. In the third picture, the switch-on takes place on the basis of the output signal with a ₃ = 1 of the encoder 62 , and the switch-off takes place after T / 4 seconds. Accordingly, the brightness averaged over the first, the second and the third image is proportional to the brightness level of the video signal A encoded with 3 bits .

An embodiment for the interlaced method is shown in FIG. 5. Two groups of push-button circuits are provided, which include switch-on push-button circuits 50 A, 50 B and switch-off push-button circuits 52 A , 52 B and gate switches 66 A, 66 B. The circuits 50 A, 52 A, 66 A are the odd fields; and the circuits 50 B, 52 B and 66 B are assigned to the even fields. The number of stages of the key circuits is equal to the number of the assigned key lines.

In Fig. 5, reference numeral 67 designates a vertical synchronizing signal separating circuit which is acted upon by the vertical synchronizing signal on line 102 and which separates the synchronizing signals on line 68 A for odd fields from the synchronizing signals on line 68 B for even numbered fields. The key circuit formed by the circuits 50 A, 52 A and 66 A for odd fields and the key circuit formed by circuits 50 B, 52 B and 66 B for the even Hall images are each operated separately for each odd field or for each even field . The switch-on and switch-off pulses reach the display panel 1 via the Y control circuit 51 . The number of output signals of the Y control circuit 51 corresponds to the number of key lines in the picture.

On the other hand, the output signals F ₁, F ₂ and F ₃ of the frame counter 63 by the vertical synchronizing signal on the line 102 for each field in the order F ₁, F ₂, F ₃, F ₁, F ₂,. . . 6, the time interval between the switch-on pulse and the switch-off pulse and the coded input signal of the memory register 40 being shown in FIG . In this way, a halftone display is possible for each field.

Above, the invention has been made in the case of a conventional one Plasma scoreboard with a memory function explained. Of course, the present one is suitable Invention for any other scoreboard with two stable ones Conditions. The invention has been made for the case above of a pure binary encoder explained. However, one can other discrete codes, e.g. B. 1-2-2-4.

Claims (4)

1. Halftone image display device with a display panel, which has a plurality of pulse-controlled picture elements, each of which can be in a stable lighting state or in a stable non-lighting state, and with a control device having an encoder for switching on the picture elements with a current value of an input video signal proportional duty cycle, characterized in that the encoder ( 62 ) the instantaneous value (v) of the input video signal for the respective picture element with n weights w _k ( k = 1, 2, ... , n ) according to the formula encodes, in which the coefficients a _{k have} the value 1 or 0 and K is a constant and that the control of the respective picture element in n successive pictures or fields takes place in such a way that in the k th picture or field the picture element is in the illuminated state, if a _k = 1 applies, or in the non-illuminated state if a _k = 0 applies, and that the duty cycle of the picture element is proportional to the weight w _k . 2. Halftone image display device according to claim 1, characterized in that the control device comprises an n -digit image or field counter ( 63 ), the n output signals ( F ₁, F ₂, F ₃) with output signals ( a ₁, a ₂, a ₃) of the encoder ( 62 ) are linked in a logic circuit ( 65 ) such that in the k th picture or field the output signal a _{k of} the encoder ( 62 ) is connected to a driver circuit ( 42 ) for the X electrodes ( 2 ) the scoreboard ( 1 ) is present as a switch-on signal, and a first push-button circuit ( 50 ) for applying Y- electrodes ( 3 ) with switch-on pulses and a second push-button circuit ( 52 ) for applying the Y- electrodes ( 3 ) with switch-off pulses with a time delay compared to Switch-on pulses, which is proportional to the weight w _k in the respective picture or field. 3. Halftone image display device according to claim 2, characterized by a Y control circuit ( 51 ), the stages of which are controlled by the corresponding stages of the first key circuit ( 50 ) and the second key circuit ( 52 ) and the Y electrodes ( 3 ) of the display panel ( 1 ) connect to a switch-on pulse generator ( 70 ) or a switch-off pulse generator ( 75 ). 4. Halftone image display device according to one of claims 2 or 3, characterized by a shift register ( 40 ) connected to the output of the logic circuit ( 65 ), the content of which is transferred to a control register ( 41 ) for each horizontal synchronizing signal, which registers the driver circuit ( 42 ) for the X electrodes ( 2 ).