DE2248105B2 - Synchronisation signal generating circuit for PAL television system - uses large number of flip-flops for processing and frequency dividing - Google Patents

Abstract

The synchronisation signal generating circuit, for a PAL television system, produces the vertical and horizontal synchronisation pulses, the vertical and horizontal blanking pulses, the compensating pulses, the burst pulses, the burst blanking pulses and the H and V camera control pulses from an oscillator of frequency 17.734375 MHz by frequency division by 2/5 and 1/227 of an H/2 pulse train. The 2/5 division is accomplished by a JK flip-flop circuit with 3 flip-flops that use the oscillator output as a triggering signal. The 1/227 division is accomplished by a JK flip-flop circuit containing eight flip-flops. All the other control pulses are derived with the air of further flip-flop.

Description

2. Circuit arrangement according to claim 1, characterized in that a pulse with de pulse width of 2.5 H, which is in the middle of de: V-frequency camera control signal (KD), with means of a 7 / f flip-flop (F30 , Fig. 12) is generated, the clock signal of the vertical synchronous pulse (VS), the reset signal of the V-frequenti camera control pulse (VD) and the trigger signali the flip-flop output signals (ßl9, β20, β21, β 22) and the inverted flip-flop output signals (Q21) are supplied.

The invention relates to a circuit arrangement according to the preamble of claim 1. Such a circuit arrangement is from de

DT-AS 19 48 317 known In this case are shown and the multivibrators used by successive pulse delay, the frequency division of the signal ρ 1 of the F i g. 18 A creates time constants by increasing the temperature and supply. The frequency of the ß-output signal Q 11 of the voltage fluctuations can be changed. Flip-flops FIl is therefore V ₂₂₇ of 7.093750 MHz,

The invention is based on the object of _5, ie 31.25 kHz and is thus twice as large as the circuit arrangement corresponding to the preamble of the horizontal frequency of 15.6-5 kHz, so that its of claim 1 is designed in such a way that it has a period of VH if H is the period of a temperature and supply voltage fluctuation line.
gen is largely independent. _{With 3 is a} ! / ,, - frequency divider in the form of a JK-

This object is achieved according to the invention _{10 designated} flip-flops F12, the F i g. 3 shows. The features given by the characterizing part of claim 1 ß-output signal ßll of the flip-flop FIl of the Freangenden. By using the logic divider 3, a trigger signal is sent to the flip element to generate the required flop F12, in order to generate a synchronizing or control signal as a β output signal, it is possible to generate the H-frequency pulse SH.
A circuit arrangement as integrated circuit i Removing ₅ By a ß-output of the first Flipzubilden and thus at lower Kos * s in greater flops Fl of the frequency divider 2 signal obtained β 1 Stückzah! to manufacture. _unc j different from frequency dividers 2 and 3

The invention is described below on the basis of the signals emitted, the vertical synchronous F i g. 1 to 22, for example. It shows impulse VS, the compensation impulse £ ß, the horizontal

F i g. 1 is a block diagram of the circuit _{arrangement 20} blanking pulse HBL, the camera control pulses HD, the voltage according to the invention, horizontal sync pulse HS and the burst identification

2 to 16 circuit diagrams of individual modules pulse BF generated, as will be described below, the circuit arrangement of FIG. 1 and 4 is a vertical sync pulse generator

17 to 22 show the course of signals which is drawn in, which consists of a / ^ - flip-flop Fl3, the assemblies of FIG. 2 to 16 occur. ₂₅ as in FIG. 4 shows that the signal ρ 1 is used as a clock signal

1 shows a block diagram that is supplied by the invention. The ρ output signals ρ5 and ß9 according to the circuit arrangement. 1 is an oscillator, until ßll the flip-flops F5 and F9 to FIl of the Fredessen output signal SO with a frequency of quenzteilers 2 are an AND gate A4 generated-17.734375 MHz. This output signal is, whose output signal to that of a _^2/5 ■ '/ ^ by means of a divider 2 as / input signal of - dividing sub ₃₀ flip-flop F13 is supplied to the as K-Eingangsworfen. signal the ß-output signal β9 of the flip-flop F9

The frequency divider consists z. B. obtained from 11 JK-F \ ip- . The flip-flop F13 therefore generates as β-off-flops Fl to FIl, such as F i g. 2 shows. The flip-flops Fl output signal the vertical sync pulse KS, to F3 serve as a ² / s frequency divider and the flip-F i g. 18 V shows and its repetition frequency twice as flops F4 to FIl as a Va ^ frequency divider. The Oscil- ₃₅ is equal to the horizontal frequency as in the latorausgangssignal SO g as a trigger signal to the i in F. 181 shown signal ßll is the case.
Flip-flops Fl to F3 given. The ß-output signal 5 denotes a compensation pulse generator,

of the flip-flop Fl is given as / - and / (T input signal, which is designed as / AT flip-flop F14, as shown in FIG. 5 on the flip-flop F2. The β output signals shows. The signal Ql , The vertical sync pulse VS of the flip-flops Fl and F2 are given to an AND ₄ o of the Füp-flop F4 _2, the ß-output signal ß8 of the flip element Al , the output signal as / -ein flops F8 of the frequency divider 2 and the ß-output signal is given to the flip-flop F3. The signal of the flip-flop F9 are used as the clock, K, J- and ß-output signals of the flip-flop F2 as a Κ-Έλη- as a reset signal on the flip-flop Flop F4 given, the output signal given to the flip-flop F3 and the equalizing pulse EQ abß output signal of the flip-flop F3 as a ß-output signal is given as / -ein 45, which is shown in Fig. 18K and the one Subsequent output signal is given to the flip-flop Fl. As a result, it has a frequency that is twice as large as the horizontal is at the ß-output of the flip-flop Fl, which is in Fig. Frequency as this when vertically synchronous pulse VS 17B shown signal ßl output, the frequency of which is the case. The leading edge of the compensation pulse ^l / ₆ that of the one in FIG. 17 A shown oscillator ses £ ß falls with the trailing edge of the vertical synchronous output signal SO, that is 3.546875 MHz. The 50 impulses KS together.

Signal β 1 is used as a clock signal and as a trigger at the same time. 6 is a horizontal blanking pulse generator.

signal is used for the subsequent stages, which is designed as a // C flip-flop F15, but how the component α does not act as a trigger signal, F i g. 6 shows. The signal β 1 is sent to the flip-flop F15, but only the portion labeled b. Therefore has been supplied as a clock signal. The vertical sync pulse the signal β 1, which serves as a trigger signal, a Fre- 55 VS and the ß-output signal β8 of the flip-flop F8 sequence of 7.093750 MHz, ie ^a / ₆ that of the frequency divider 2 are an AND gate A 5 oscillator output signal SO. The signal ßl is supplied as, the output signal of which is given as the / input signal trigger signal to the flip-flop F4 and which is given to the flip-flop F15. The ß-outputß-output signals of the flip-flops F4 to FIl are signals ß6, ß9 and β 10 of the flip-flops F6, F9 and as a trigger signal on the immediately following flip-60 FlO of the frequency divider 2 are given to an AND-Gliec flops. The ß-output signals fed to the flip-flops A6 , whose output signal is given as A ^ input F5 and F9 to FIl on a NAND element NA 2 signal on the flip-flop F15. Dei given, whose output signal is sent to a NAND gate pulse SH with the period // of the frequency divider; NA3 is given, which also receives the output signal as a reset input signal to the flip-flop FIf of the flip-flop F4 and its output signal 65 is given. As a result, the flip-flop F15 generates a reset signal on the flip-flops F4 to FIl ß-output signal the horizontal blanking pulse HBL will give. The flip-flops F4 to FIl give output of the in F i g. 18L is shown and the one repetition rate signals from ß4 to ß11, which are shown in FIGS. 18B to 18F is equal to the horizontal frequency.

5 ^y 6

With 7 is a horizontal pulse control generator synchronizing pulse VS of FIG. 19A is, ie

draws, which is designed as a JK flip-flop F16, ^ _K Hz = 1.25 KHz. The ρ output signal ρ23

like fig. 7 shows. 25 ⁶ ^

The signal ρ 1, the output signal of an AND of the flip-flop F23 is sent as a clock signal to the next

Glieds / 47, the vertical sync pulse VS and 5 following flip-flops and the ρ output signals of the

the ρ-Α ^^ είΰΙιβ ^ ηΒίρβ of the flip-flop F8 of the flip-flop F24, F27 and F28 are switched to a NAND

Frequency divider 2 receives, and given the output signal of a member NA 14, the ρ output signal via

AND gate / 48, to which the ß-Aus £ angssigna ^ 5 and an inverter / 2 are assigned to a NAND gate NAlS

ρίΟ the flip-flops FS and FlO of the frequency divider 2 leads, which also the ρ output signal of the

are supplied, and the pulse SH of the frequency io flip-flop F24 receives. The output signal of the

divider 3 are as clock, J, K and reset signal NAND gate NA 15 is used as a reset signal

fed to the flip-flop F16, so that this is given as ρ-off flip-flops F24 to F28. Generate thereby

output signal the H-frequency control pulse HD er the flip-flops F24 to F28 ρ output signals ρ 24

testifies to how F i g. 18M shows and the camera up to ρ28, as shown in FIGS. 2OB to 2OF are shown,

control pulse is used. The leading edge of the control 15 whose repetition frequency V25 the frequency 1.250 KHz

impulses HD coincides with that of the horizontal of the ρ output signal ρ23 of the flip-flop F23

blanking pulse HBL together. F i g. 20A, ie 50 Hz and thus the

With 8 a horizontal sync pulse generator vertical frequency is the same.

denotes, which consists of a JK flip-flop F17, With a vertical control pulse generator 11 is denwie Fi g. 9 shows. The signal Q 1, the output signal ao net, which consists of a JK flip-flop F29, such as an AND gate A9, which the vertical synchronous F i g. 11 shows. The vertical sync pulse ^ S of the pulse VS and the ρ output signal ρ9 of the flip-flip-flop F4, the output signal of an AND gate flop F9 of the frequency divider 2, and the output .416, which with the ρ-output signal ρ21 of the flip output signal an AND gate AlO, the ρ-out flop sF21 and the inverted ρ-output signal output signals ρ 4, ρ 5 and ρ 10 of the flip-flops F4, F5 25 Q 23 of the flip-flop F23 of the frequency divider 10 and FlO of the frequency divider 2 receives, and the Im- is ensured, the output signal of an AND element pulse SH of the frequency divider 3 are clocked, J-, All, the with the ρ output signals ρ 19, ρ20 K- and reset signal to the flip -Flop F17 is supplied, and Q23 of the flip-flops F19, F20 and F23 is supplied so that this becomes the horizontal output signal as the ρ output signal, and the AND-linked output signal generates synchronous pulse WS, which is shown in FIG. 18N shows 30 ρ27 * ρ28 of the ρ outputs ρ27 and ρ28 of the flipist. The leading edge of the horizontal sync pulse flop F27 and F28 are fed to the flip-flop F29 as clock, J, K and ses WS coincides with that of the compensation pulse F ^ reset signal. That together. AND-linked signal ρ27 · ρ28 is a pulse, with 9 a burst identification pulse generator is designated, which consists of a JK flip-flop F18 with the ρ output signals ρ23 to ρ28, such as F i g. 9 35 flip-flops F23 to F28 are related as F i g. shows. The signal ρ 1, the output signal of an AND 2OG shows, so that the AND signal with such a member All, that with each inverted H-frequency relationship to the vertical sync pulse VS and camera control pulse WO and the ρ output signal, the ρ output signals Q 19 until ρ 23 of the flip-ρ7 of the flip-flop F7 of the frequency divider 2 and the flops F19 to F23 is obtained, as shown in Fig. 19 G inverted ρ-output signals Q8 and ß9 of the flip-4 °, and its pulse width is 12, 5 H. The flops F8 and F9 are supplied, the output signal flip-flop F29 generates the V-frequencies of an AND gate AU, which with the ρ output camera control pulse VD, FIG. 19H shows, the signals ß7 and ρ8 the flip-flops F7 and F8 have a pulse width of 7.5H.
Frequency divider 2 and the horizontal blanking pulse With 12, a pulse generator is supplied to generate an HBL , are given as clock, J, K and 45 pulses with a pulse width of 2.5 H designated reset signal to the flip-flop F18. DA consisting of a / K flip-flop F30 as shown in Fig. Il by the burst characteristic is shows pulse BF, FIGS. 180th The vertical sync pulse VS of the flip-flop; shows, which has a repetition frequency equal to that of F4, the output signal of an AND gate / 118, since: has a horizontal frequency, as the ρ output signal of the flip-flop F18 with the ρ output signal ρ 19 of the flip-flop F19. 50 the inverted ρ-Q output 21 of flip The vertical sync signal VS provided by the flip-flop F21 and the ρ-output signal ρ 22 of the flip-flop F7 is obtained, is supplied to a V25 · Vis-frequency flop F22 of the frequency divider 10 is given as a frequency divider 10. Output signal of an AND gate A 19, which is connected to the The frequency divider 10 consists of ten JK-FHp- ρ output signals ρ20 and ρ21 of the flip-flops F2i flops F19 to F28, such as F i g. 10 shows. The flip-flops 55 and F21 is supplied, and the vertical control pulse F19 to F23 form a first! ^ - frequency divider VD as clock, J, K and reset signals and the flip-flops F24 to F28 a second V25 flip -Flop F30 supplied as a ρ-output signal frequency divider. The vertical sync pulse VS emits a pulse SA , as shown in FIG. 191, which is applied as a clock signal to the flip-flop F19 and which is in the middle of the vertical control pulse VD and the ρ output signals of the flip-flops F19 to F23 are the same Repetition frequency like this and a pulse on the next following flip-flop as a clock signal width of 2.5H.

and the ρ output signals of the flip-flops F19, F22 At 13, a vertical blanking pulse generator b <

and F23 are given to a NAND gate NA 13, records, which consist of a JK flip-flop F31

its output signal as a reset signal to that shown in FIG. The ρ output signal ρ20 d <

Flip-flops F19 to F23 is given. Therefore, 65 flip-flops F20 of the frequency divider 10 produce the output

the flip-flops F19 to F23 ρ output signals ρ 19 signal of an AND gate A 20, which with the ρ-Au

to ρ23 shown in Figs. 19B to 19F, output signal ρ23 of the flip-flop F23 and the inve

whose repetition frequency V25 that of the vertically oriented output signal Q 27 · Q 28 is supplied, ur

the vertical control pulse VD are fed as a clock, J and reset signal to the flip-flop F31, the Ö input terminal of which is grounded. The flip-flop F31 are as (? Q output the Vertikalauslastimpuls VBL from the F i g. 19J shows and a repetition frequency equal to the vertical frequency, and a pulse width of 20 H has. The leading edge of vertical blanking VBL coincides with that of the vertical drive pulse VD together

14 with a Va frequency divider is designated, which consists of a .//(- flip-flop F32, as shown in FIG. 14, which is supplied with the horizontal sync pulse HS of the flip-flop F8 as a clock signal and the Q output one Emits pulse as shown in Fig. 21D, which has a pulse width of 1 H and a period of 2 H.

Denoted at 15 is a circuit which is used for generating the burst blanking pulse and which consists of / K flip-flops F33 to F35, as shown in FIG. The pulse SB with the period 2 H is sent as a clock signal to the flip-flop F33, the output signal of the flip-flop F33 is sent as a clock signal to the flip-flop F33 and the (? Output signal of the flip-flop F34 is sent as a The vertical sync pulse VS, which is generated by the circuit 4 and the AND-linked signal Q 27 · Q 28 are given as a clock and / signal to the flip-flop F36, whose Ö- The flip-flop F36 generates a pulse SD, shown in FIG. 19K, which has a pulse width of 12 H and which is fed to the flip-flops F33 to F35 as a reset pulse Repetition frequency equal to the vertical frequency and is obtained in a fixed relation to the vertical control pulse VD and the pulse SD with the pulse width of 2.5 H, as shown in Figures 19 K, 21 B and 211. Thus, the fip-flop F33 generates during the pulse SD with the pulse width 12 H at its (^ -output a pulse SE the F i g. 21E shows and has a pulse width of 2H, and the flip-flops F34 and F35 generate, as ρ output signals, pulses SF and SG shown in Figs. 21F and 21G. The pulse SB, which is fed as a clock signal to the flip-flop F33, has the period 2H, while the vertical control pulse VD, the pulse SD and the pulse SA have the period of one field, i.e. Vi. 625/2 H. so that the leading edges of the pulses SB. SE, SF and SG with respect to those of the vertical control crimp VD and the pulses SD and S // are shifted by 0.5 H for each field and all four fields coincide with these. Since the trailing edge of the pulse SG "always coincides with that of the pulse SD with the pulse width 12 H, the pulse width of the pulse SG is 4.5 H in the first field, 5 H in the second field, 5.5 H in the third field and 4 H in the fourth field.

Denoted at 16 is a burst load pulse generator which is composed of a JA 'flip-flop F37 shown in FIG. The horizontal sync pulse HS, the output of an AND gate A 21, which is supplied with the pulse SiS and the inverted output signal 5G of the circuit 15, and the output of the AND gate All, which is supplied with the pulses SE and SG , and the Pulse SD with pulse width 12 H are called clock, J-. The K and reset signals are fed to the flip-flop F37, which emits the burst blanking pulse BB as a £) output signal, which is shown in FIG. 21H and which has a pulse width of 9H. Since the leading edges of the pulses SB, SE, SF and SG are each shifted by 0.5 H with respect to those of the vertical control pulse VD and the pulse SA in each field, the burst blanking pulse BB is also shifted by 0.5 H with respect to the vertical control pulse VD and the pulse SA shifted with every field and falls with every four fields

ίο this together.

Therefore, when the synchronizing signal generator 17 is supplied with the vertical control pulse VD of the pulse width 7.5 H, the pulse SA of the pulse width 2.5 H, the vertical synchronizing pulse KS, the equalizing pulse EQ and the horizontal synchronizing pulse HS , it generates a synchronizing signal, the F i g. 22 and which has five vertical sync pulses VS occurring in the first period of 2.5 H in each field, and five equalizing pulses EQ in the period of 2.5 H before and after the pulses SF and the horizontal sync pulses HS, the relative Position of each pulse HS compared to the vertical sync pulse KS and the compensation pulse EQ in the odd and even fields is shifted by 0.5 H from one another.

The output signal SO of the frequency 17.734375 MHz of the oscillator 1 is fed to a '/ ^ frequency divider 18 in order to generate a signal of the frequency 4.43359375 MHz, the frequency of which is 25 Hz lower than the subcarrier signal frequency 4.43361875 MHz. The signal obtained in this way is fed to a modulator 19, while the vertical control pulse VD of the frequency 50 Hz of the flip-flop FU is ^{fed to a 1} I ₂ -FTt quenzteüer 20 to generate a signal of the frequency 25 Hz, which is fed to the modulator 19 will. In the modulator 19, the signal of the frequency 3.43359375 MHz of the frequency divider 18 is modulated with the signal of the frequency 25 Hz of the frequency divider 20 and thus an auxiliary carrier signal SC is generated with a frequency of 4.43361875 MHz.

The burst blanking pulse BB of the pulse width 9 H of the flip-flop F16 and the burst identification pulse BF of the flip-flop F9 are fed to a burst identification pulse generator 21 to generate the burst identification pulse BF during a different period than that of the pulse width 9 H of the burst Generate blanking pulse BB The burst blanking pulse BB of pulse width 9 H of flip-flops F16 and the pulse SB of pulse width 1 H and period 2 H of frequency divider 14 are fed to a burst switching signal generator 22 to obtain a burst toggle signal That each horizontal period in a period other than the de pulse width 9 H of the burst blanking pulse BB is reversed. By alternating separation de subcarrier signal with the burst Umsehaltsigna and the burst flag pulse BF, the burst signal Bi inserted in the back porch immediately after the horizontal sync signal HS as F i g. 2 shows.

The horizontal blanking pulse HBL and the vertical blanking pulse VBL are fed to a blanking signal generator 23 which generates a blanking signal *. The blanking signal, the horizontal control pulse WD and the Vcrtikalstcuerimpuls VD are used for Kamen stcucrunc.

In addition 5 sheets of drawings

509 583/3!

Claims (1)

Patent claims: 1. Circuit arrangement for generating the synchronization or control signals, namely the vertical sync pulses, the vertical blanking pulses, the compensating pulses, the horizontal blanking pulses, the horizontal blanking pulses, the burst identification pulses, the burst blanking pulses end H and V-frequency camera control pulses for a PAL color television system from an oscillator frequency of 17.734375 MHz, be by means of fine frequency division by _^2/5 x ^l / ₂₂₇ a H / 2 more frequent pulse train derived, and wherein the color subcarrier of 4.4361875 MHz by modulating a derived from the vertical pulse pulse train and the OszillatorimpuJsfolge and 4-division is generated, characterized in that 20th a) that the _^2/5 -division by means of a 7AT flip-flop circuit (F i g. 2) having three flip-flops (Fl to F3), which is supplied to the oscillator output signal (SO) as a trigger signal and the output signal (Ql) serves as a clock signal for subsequent stages, b) that the V227 division by means of a / # flip-flop circuit (Fig. 2) with eight flip-flops (F4 to FIl) takes place, the output signal (QIl) of the last flip-flop in a / K-FIip -Flop (F12, F i g. 3) is subjected to a 2-division to generate the H-frequency pulses (SH), c) that the vertical sync pulses (KS) generated by means of a / ^ - flip-flop (F13, F i g. 4) and the clock signal (ßl) and the flip-flop output signals (25, Q9, Q10, QU) as trigger signals will, d) that the equalization pulses (EQ) by means of a / ^ - flip-flop (F14, F i g. 5) and the clock signal (ßl), the vertical sync pulses (VS) and the flip-flop output signal (Q 8) as a trigger signal and the flip-flop output signal (09) are generated as a reset signal, e) that the horizontal blanking pulses (HBL) by means of a / K flip-flop (F15, F i g. 6) and the clock signal (Q 1), the vertical sync pulses (VS) and the flip-flop output signals (Q6, Q 8 , β 9, β 10) are generated as trigger signals and the H-frequency pulses (SH) as reset signals, f) that the H-frequency camera control pulses (HD) by means of an / AT flip-flop (F16, F i g. 7) and the clock pulse (ßl) of the vertical sync pulses ( VS), the flip-flop output signals (Q 5, β 8, β 10) are generated as trigger signals and the H-frequency pulses (SH) as reset signals, g) that the horizontal sync pulses (HS) by means of an / AT flip-flop (F17, F i g. 8) and the clock pulse (Q 1), the flip-flop output signals (ß3, ß4, ß9, β 10), and the vertical sync pulses (VS) are generated as trigger signals and the H-frequency pulses (SH) are generated as reset signals, h) that the burst identification pulses (BF) by means of a y # flip-flop (F18, F i g. 9) and the clock pulse (ßl), the inverted H-frequency camera control pulse (JTW ), the inverted flip-flop output area ( ß8, ß9) and the flip-flop output signals (ßl, Ql, ß8) are generated as trigger pulses and the horizontal blanking pulses (HBL) as Rückteilsignai. i) that the vertical sync pulses (VS) in a ./Ä- flip-flop circuit (Fig. 10) with ten flip-flops and the vertical sync pulses ( VS) are subjected to a V ₂₅ - y., ₅ division, j) that the V-frequency camera control pulses (VD) by means of a / tf flip-flops (F29, F i g. 11) and the vertical sync pulses (VS) as a clock signal, the inverted flip-flop output signals (Q 23) and the Flip-flop output signals (ßl9, β20, ß23) are generated as trigger signals and the AND-linked flip-flop output signals (Q 27 β 28) are generated as reset signals, k) that the vertical blanking pulses (VBL) by means of a / tf flip-flop (F31, F i g. 13) and the flip-flop output signal (ß20) as a clock signal, the inverted AND-linked flip-flop output signals (Qn ■ Q2S) and the flip-flop output signals (Q 20, β 23) are generated as clock signals and the V-frequency camera control pulses (VD) are generated as a reset signal. 1) that the horizontal sync pulses (HS) in a // ^ flip-flop (F32, F i g. 14) _{are subjected to a V 2} division, and m) that the burst blanking signals (BB) by means of a i / tf flip-flop Flop circuit (F i g. 15, 16) with five flip-flops (F33 to F37) and the AND-linked flip-flop output signal (Q 27 · β 28 'as the trigger signal and the vertical sync pulses (KS) as the clock signal of the first flip-flop (F36), the flip-flop output signal (ß32) as a clock signal and the flip-flop output signal (F36) as a reset signal of the second flip-flop (F33), the output signals of the previous flip-flops (F33, F34), the third and fourth flip-flops (F34, F35) as clock signals, and the horizontal sync pulse (HS) as clock signals, the flip-flop output signals (ß32, ß33, ß35) as trigger signals unc of the flip-flop Output signal (ß36) can be generated as a reset signal of the fifth flip-flop (F37).