DE2226312A1 - METHOD AND CIRCUIT ARRANGEMENT FOR GENERATING A RUNNING DISPLAY ON A DISPLAY DEVICE - Google Patents

Description

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Ma «l« illlanilraQ · <O

3. H. KINKELDEY

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DR.-ING. W. STOCKMAIR, A ©. E. <c «4.mn« t. a, «« «.,

PATENT ACTS

May 30, 1971 P4695

Bunker Rarao Corporation

900 Goimaerce Drive

Oak Brook, Illinois 60521

Method and circuit arrangement for generating a current display a display device

The invention relates to a method for generating a current display on a cyclically scanned display device as well as a circuit arrangement for carrying out the method.

Laufeade ads are usually used to display a variety of things Information used, e.g. for advertisements, newsletters or to display stock market data. The last It can usually be used as a stock market ticker display designated.

3isber's running display symbols are based on two basic principles Species formed ;. With the first kind of a running one Display the characters have been made either mechanically or electrically in a character generator and then become physical from a tape or similar arrangement on a light surface moved past. This type of display also includes the pro

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jection tickers that have a moving and printed Tape is projected on a screen. In the second type of moving display, a matrix of lamps is provided, in which the characters move from line to line on the lamps depending on timed control pulses Be formed step by step. Between the control pulses the information is either stored in the lamps themselves, if the discharge or other lamps are using Memory properties can be used, or a separate memory can be provided for each of the lamps.

Indicators of the type described above are relatively large and expensive and usually require fairly frequent maintenance. They are also not very adaptable and only designed for running display applications. However, there are applications that require ongoing information such as. For example, stock market information or news lines are to be displayed on a customary display device such as a cathode ray tube. Such a facility allows the information to be presented as part of an overall information system and no longer as a separate part, and achieves lower cost, greater reliability and a far more adaptable display.

However, in order to be able to carry out a current display of information on such a display device, a control must be provided be provided, which stores the information to be displayed and causes the simulated movement. To one also aesthetically To achieve a satisfactory display, the display should move at an approximately steady speed appear. However, such arrangements are usually designed to get their character information from a memory and receive this information via a character generator

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feed to a full character on the display device to create. Moving the information by one however, full pitch gives the display the unsatisfactory jerky appearance. They are therefore institutions required with which the information is each part of a character on the screen of a cathode ray tube can be moved in order to achieve a steady flow of data in this way.

In addition, the speed at which the information is received, particularly in the case of ticker information, may not necessarily be uniform. In order _for a full screen of information to be displayed continuously without any information being lost, the speed at which the information is moved across the display device must also vary depending on the data input speed. It is therefore necessary to provide a control with which the feed rate of the information can be changed.

The object of the invention is to provide a. Method and circuit arrangement to create a running display on an ordinary display device, such as a cathode ray tube, with which the characters prevail over the display. direction can be moved in such small steps that are smaller than a full drawing step. In addition, the The speed of advance of the information and the characters on the display area with the acquisition speed of the incoming Data to be changed.

In a method of the type mentioned, this object is achieved according to the invention in that a first predetermined number of characters to be displayed and a second predetermined one

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A number of characters waiting to be displayed in one aöreeabaren memory is stored that in the Store the starting address for the first number of lines specified that each at a given time Display cycle the number of characters waiting for their display, -buffered character is determined that the for the first Number of characters specified start address is incremented depending on the size of the previously determined number and that the first number of characters in a predetermined sequence starting with the specified starting address from the Memory is read out to control the display of the display device.

According to the method according to the invention and the circuit arrangement used to carry out the method, a ordinary display device with a cyclic grid and an addressable memory used, the addressable Storage locations for storing a first predetermined number of characters to be displayed and further storage locations which store a second predetermined number of buffered characters awaiting display. A first device is provided that provides the start address for the first number of characters, i.e. the number to be displayed Indicates characters, and a second device is provided which indicates the address at which a new character to be buffered can be saved. One during a certain time of each display cycle, e.g. during the frame return, operating device uses at least one of the specification devices to determine the number of buffered Characters that are waiting to be displayed and the address specified by the first specification device counts by one size further, which depends on the previously determined number. the The first predetermined number of characters is read out from the memory using suitable reading devices, starting with

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the address specified by the first indication device in order to control the display on the display device. Is the one specified incrementally in the first specification facility Address is a column or jump address and is a device responsive to the column address is provided in the first specifying device which determines the number of columns of the controls the character indicated by the first specifying device that is displayed, then the desired feed rate achieved in small incremental steps. By change the number of columns or jumps added to the first indication device during each display cycle, and the number of which depends on the number of characters which will be displayed in the buffer part of the memory the desired speed control of the current display depending on the feed speed of the data causes. ·

The invention is illustrated by means of one in the drawing Embodiment explained in more detail. Show in detail:

Fig. 1 is an echematic block diagram of a preferred

Embodiment of the invention, Figure 2 shows a display generated using the invention

can be,
Fig. 5 shows a portion of the display shown in Fig. 2 by one

. Display cycle later and
Figure 4- is a memory map indicating the locations in which the characters shown in Figures 2 and 3 are stored for display.

Fig. 2 shows the screen surface of a cathode ray tube, on which the "New York Stock Exchange ticker" on the upper side of the screen and the "American Stock Exchange Ticker"

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shows are. In the middle part of the screen are additional ones Stock market data are displayed and appear in the lower part of the screen News fonts. The present invention is primarily concerned with a method and one Circuit arrangement for moving the characters of the two tickers from right to left across the screen of the cathode ray tube at a steady pace, which. becomes a function the speed of the received data changes. It should be noted that the news fonts in the lower part of the Can also move across the screen from right to left. However, with six lines of a message font ad, As shown in Fig. 2, this information is preferably displayed as described in U.S. Patent 3,559,203 is. With this type of display, the lines are written one after the other, with the first line being the last Line follows. However, this information can also be displayed in such a way that one line appears at a time, with each new line appearing Line appears at the bottom of the display device on the screen and the remaining lines one line at a time be moved above

Although the manner in which the movement of the two tickers shown in Fig. 2 is the same, the following description refers to the "New York Stock Exchange tider ^M in the first part of the display, it being understood that this is in conjunction What is said with this ticker also applies in the same way to the "Aiterican stock exchange ticker" in Part 2. As can be seen from Pig which is able to display the information shown in Fig. 2. The cathode ray tube is cyclically rewritten with a raster pattern consisting, for example, of 24 full lines, each of which is made up of several scanning jumps

Intensifying a combination of seven index points on each of five sample jumps or sample columns is generated. In other words, the characters are formed in a character matrix of 5 * 7. Circuits for generating such a screen pattern are described in U.S. Patents 3,428 and 3,500,327. These patents show that two sawtooth generators are provided in the display device to control the raster generation. A first sawtooth generator controls the generation of the scanning jumps, a second sawtooth generator controls the generation of lines and the horizontal return and a third sawtooth generator controls the line spacing and the frame return ·. Synchronization pulses are given via a line 11, an OR element 16 and a line 18 to the display device 10 in order to control the various sawtooth generators. The synchronization pulses for the scanning jumps and lines, which are generated in a synchronization pulse generator 12, are supplied directly via the line 11, while the horizontal synchronization pulses from the generator 12 are supplied via the line 11 via a variable delay circuit 14. The operation of the delay circuit 14 will be explained later. .The synchronization pulses are generated under the control of a clock signal to an egg ¹ line 20 and a signal on a line 21 indicates that it is a sync pulse for a ticker display that is required. The clock signals on line 20 and other switching points of the circuit are derived from a clock generator 22. This clock generator generates output signals indicative of a bit, a Abtastsprung, öiij characters and a line count for the grid on the display device 10 in every moment and also various clocks for controlling the reading and writing of information hen the working random access Gpi.icfcor PA cn thai tone. To simplify Fig. 1 were

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no connections are given for the output signals of the clock generator 22 to the various switching points of the circuit and shown.

The video code for the characters to be displayed on the display device 10 is obtained from a character generator 26 via the OR gate 16 and the line 18. The entrance of the Character generator ^ 26 is connected to the output line 28 of the Memory 24- connected. The memory 24 is a large memory with any access, e.g. a magnetic core memory in a matrix arrangement. Different parts of this Memory stores information of various kinds which is displayed on one or more display devices a) 10 can. In connection with the present description, only that part of the memory 24 which contains the information will be considered for the "New York Stock Exchange Ticker" contains. New information is stored in the memory 24 via a line 30. Stored by the input buffer register 32. The entrance this register is connected to the ticker line 34. If a full character is created in this register with help of a detector 56 is detected, a signal is transmitted via a line 38 given to an input of an AND gate 40. The other input of AND gate 40 is a clock line 42. How will soon be seen, the information will be from the Memory 24 is read out synchronously with your writing of the characters on the display device 10. Since the access speed to memory is much greater than the speed at which the characters are rewritten by the cathode ray tube are one or more memory cycles to be registered of information is provided in memory between each readout cycle. Signals appear on clock line 42 when can be written into memory. If the AND element 40 is fully connected, a signal appears on the line 44, which is used as an input to the write-in controller

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46 is given. A second input to the write-in controller 46 is derived from the input address counter 48. This counter contains the address of the memory 24, an which can be used to store the next ticker character. As can be seen from Fig. 4, the stock market index part becomes the Ticker input signals are stored in another part of the memory separately from the price and quantity information. Of the The reason for this is that this information is shown shifted half a line on the display device and therefore formed by other horizontal lines. Further details in this regard will be provided later in connection explained with reading out the memory. However, at this point it can be seen that in addition to the input address within a part that is contained in the counter 48 is, a corresponding indication of the respective area must also be given to the write-in control 46. These Information is supplied via a line 49 from a detector 51 responsive to price and quantity information. Of the Detector 51 can be, for example, a flip-flop which is set by a signal on line 38 when the character is in register 32 is identified by a bit to indicate price or quantity information and the flip-flop is reset of a signal on line 38 if that bit does not appear. The write-in controller 46 controls this Way the character address in memory 24 at which the on the Line 30 incoming characters is stored. The signal on line 44 is also applied to the incremental division of the address in memory 48 so that the next received Character is stored in an appropriate location for the character in the appropriate area.

In the embodiment of the invention shown in FIGS. 1 to 4, 48 characters of ticker information can be added to each given time. There are also eight buffer

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Drawing spaces provided. Each area of that shown in FIG The memory therefore contains 56 address locations for the characters. Because of the way in which the characters are displayed, see "Fig.2, a character can only appear in a character space with a certain ordinal number in one of the areas. Characters appear therefore in character spaces 4, 5 and 6 of area 1 and in character spaces 7 to 1.2 of area 2. It can therefore be a A single register or counter can be used to specify the character spaces with which the display begins. This information is in a display address counter 50 shown in FIG is included. This counter contains both a character address and a scan jump aare. The character part the address is sent via a line 52 as a stick address to a Readout control 54 given. For example, if the information is as in 4 is stored, the one indicated by the counter 50 is Drawing place the drawing place 4. At the time of the first character cycle at which the grid is the first line of the Ticker display writes, therefore the character S is read out at character position 4 of area 1. During the time of the second character cycle, character I is read from character space 5 and other characters are read out in a similar manner. During the character measures 4 to 9, during which the character spaces 7 to 12 are called, no characters or spaces are read out, as can be seen from Fig. 2, so that blank spaces appear on the display device during these character clocks. Reading out the memory part 1 is continued under control of the clock signal on line 56 until the character position 51 is reached, to which Time all 48 characters to be displayed are read out.

The clock generator 12 then generates a synchronization clock pulse for the return line generated and characters are created for the »next line of the" New York-JEffektenbörsen-Ticker " read out, starting again with character position 4.

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This time there were blank letters during the first three bars of characters, the character 2 read out during the fourth and the character S during the fifth clock. Will be again under control of the clock signal on line 56, appropriate Read out characters from the memory "until 48 character spaces have been called up, i.e. the character space 51 is one memory constructed according to FIG. 4 has been achieved.

If no characters wait for their display in the buffer part of the memory 24, which, as shown for example in FIG the ticker appears, repeats the sequence of functions described above and in this way achieves a stationary display. In the example shown in FIG. 4, however, 6 characters are waiting to be displayed in the I ³ Uff part of the memory. During a clock time of the frame return, the path return usually requiring the time of 6 characters, a signal therefore appears on a clock line 60. The signal on this line causes a buffer counter 62 to be set to a count of 8 and a gate circuit 64 is switched through in order to enter the input address into the address counter 66. The contents of the address counter 66 are rlann group having character count compared in counter 50 ,, Since in the example shown in FIG. 4, the initial count in counter 66 to two while the initial Zeichea count in the counter 50 is four, produces a compare 68 au At this point in time, an output signal on a line? 0, which does not indicate any correctness, and which gives a through-connection signal to a UiTD element 72. The other input of the AND gate 72 is connected to a clock line 4, which carries a signal with every frame return with the exception of the first. At the time of the second frame return, the UKD element 72 is therefore full

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switched through and gives an output signal on a line 76, which increases the count in counter 66 to three and lowers the count in buffer counter 62 to seven.

Since from the comparator 68 there is still a no match The AND gate 72 remains still switched through when the clock pulse for the third liahmen return reaches the AND gate 72. That I the resulting output signal on line 76 counts the Counter 66 continues to a counter margin of four and reduces the counter reading of counter 62 to a counter reading of six, The character counts in counters 50 and 56 are now correct match, whereby the signal indicating no match on line 70 disappears and thus another one Change of the counter readings in the counters 66 and 62 prevented and a signal signaling the agreement Line 78 is emitted from the comparator 68. The signal on line 78 switches a gate circuit 80 by so that the count of the counter 62 to an interconnection from detectors 82-85. Because the meter reading in buffer counter 62 equals six, detector 85 responds to an output on line 90 from the Gate circuit 80 and generates an output signal on the. Line 91t that is responsible for setting one for shift 2 Flip-flops 92 in its 1-switching state and over an ODEE gate 94 for resetting the for a shift 1 responsible flip-flops 96 are used in its 0-Bä.tstatus will.

Line 98 connected to the 1 output of flip-flop 92 is connected to one input of an AND gate 100. To the Time N of the character cycle of the frame return, which is at the embodiment of the invention described above

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the clock for the tenth Bahmenrücklauf or any clock may be later, a signal on a line 102 which completely turns off the AND gate 100 appears, whereby an output signal on a line 104 appears _9, the Abtastsprungteil the address in the display address counter 50 enlarged by two. An output line 106 from the sampling jump part of the counter 50 is connected to a control input of the adjustable delay circuit 14. The delay circuit 14 also receives an input signal via a line 107 which enables the adjustable delay circuit to work only when a line 1, 1.5 or 2 of the ticker part has ended.

Reference is made to FIG. 3 to understand the mode of operation of the adjustable delay circuit 14. From this figure it can be seen that line 1 of the display is only eight characters long. At the side of this line, a horizontal or horizontal Synchronisatioas- Eücklaufimpuls from the pulse generator 12 generates ifird "This pulse is delayed by the delay circuit 14 to the ice Aasahl Abtastsprüngen of which is equal to the count of the counter in Abtastsprünge 50th In the example chosen here, this synchronization pulse is therefore delayed by two sampling jumps. The circuit "then" causes a line return and a line feed by half a line and the raster begins with a scan of the character 1 on line 1.5 · Although the return pulse was delayed in two scan jumps ©, the v cycle 22 continues normally and controls Reading out the memory 24. The reading process of the memory 24 is therefore phase-shifted by two iLfotastspragre compared to the Aaaeige, or with other Morten, the display is two scanning jumps further to the left than this is indicated by the circuit clock »In this way

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a shift by two sampling jumps is achieved. The effect of this shift of two scan jumps to the left is shown in FIG. In the same way, the synchronization pulse for the horizontal return at the end of the cables 1.5 in the delay circuit 14- is also shifted by two scanning jumps. However, since this character space, namely the character space 52, is empty for line 1.5 _; nothing is displayed during these sampling jumps,

Since the return line was shifted by two scan jumps, line 2 begins two scanning jumps later than indicated by the clock, so that this line too is two scanning jumps is shifted to the left. This line therefore also runs two scanning jumps beyond its normal end, so that two scanning jumps of the one located at the character space 52 Character, the number 2, can be displayed before the return line occurs. The next return is a full line return to line 3 · Since this line is empty, conditional a delayed start of this line doesn't pose any problems. However, since the clock for line 3 has no input signal to the adjustable delay circuit 14 causes the horizontal return cycle at the end of this line is not delayed and normal synchronization is thus restored between the circuit cycle and the display grid. Although this It should be noted that in some applications the restoration of the Synchronization of the display may require that less than the full number of characters on line 3 be scanned.

To the zoiö of the next frame return it is stated that Still 6 characters in the buffer part of the memory are waiting to be displayed, 30 that the flip-flop 92 is in its 1-switching state remains, whereby the scanning jump counter reading in counter 50 again

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which is increased by two. While the next frame is displayed the return pulse for lines 1.5 and 2 is therefore delayed by four scanning jumps, which shifts the display by four scanning jumps to the left. However, compared to the previous display, the display is only shifted two steps to the left.

During the display of the next frame, the scanning jump counter reading is increased again by two, so that when the next frame is displayed, the display is shifted to the left by a total of six scanning jumps . At the end of this frame, the counter 30 is incremented again by two. However, since only seven AbW * ... ^ psiüssge ■ belong to a character, an increase in the Ξε-iler-stanäes by two results in an increase in the character counter status> am if there is already a scanning period of six 1 and a Rüoks © tztuigdeß scanning test counter status. 1. Mähread of the display of the next frame calls dafees? the character Q counter reading in the counter 50 shows the memory location 5 shown in FIG. M , waä -the display begins with the character stored in this memory location. The sample jump count voa 1 results in a delay of one sample jump so that a sample jump of this character is missing. It should be pointed out that at the end of this frame, when the comparison is made in the comparator 68, it is determined that there are only 5 characters waiting in the buffer part of the memory. However, since the detector 85 responds to a number of five to eight characters, an output signal appears again on the line 91 and the flip-flop 92 remains set.

The shift by two sampling jumps for each frame is continued until the one stored in memory location 5 Character was pushed out and the character count in counter 50 calls memory location 6. Assuming that

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If no new characters have been given to the buffer part of the memory in the meantime, it is determined at this point in time that the character count in the buffer part is only 4 during the next frame jerk time. The exhaust line 110 of the detector 84 is. however, connected to one input of an AND element 112, to whose other input an output line 114 connected to the 0 output of the flip-flop 92 is connected. Since the flip-flop 92 is still in its 1-3 switching state at this point in time, the output signal on the line 110 is ineffective for switching the flip-flops and the shift mn two scanning jumps per frame is continued.

If it is again assumed that no new characters have reached the memory 24 in the meantime, then the above continue until the character count in the counter 50 was increased to 9. If this is the case, so the buffer counter 62 is counted down to a count of 1 before a match is found by the comparator 68 and the detector 85 responds and gives an output signal on a line 116. The output signal on line 116 is via an OR gate 118 and a line 120 is given to the flip-flop responsible for a shift of 1 and sets this to its 1-switching state, whereby at the same time via an OR gate 122 and a line 124, the flip-flop 92 is reset to its O-switching state. With the signal from flip-flop 96 now appearing on line 126 and no signal on output line 98 from the flip-flop 92 an AND gate 128 instead of the AND gate 100 is fully switched on if at time N the clock for the frame return occurs. The output signal which is calibrated on a line 130 is given to the counter 50 in order to be able to use it in this to increase the scanning jump counter reading by 1 each time. Waiting of the next frame is the introduced delay of the

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lenrücklaufs therefore only a sampling jump larger in contrast to the delay in the preceding frame, which is greater by two sampling jumps. The speed, .with which the characters move across the screen appears diminished. Are from memory 24 during the next six or seven display cycles do not add any new letters between the time at which the flip-flop 96 is set and the time at which the number of characters was counted is again incremented in the counter 50, then is received during the increment of the character count following Frame return the counter reading in the buffer counter 62 to 0 decreased before a match is established in the comparator 68 and the detector 82 responds with it and outputs a signal on an output line 132. The signal on the line 132 is via an OR gate 94 to the flip-flop 96 given and sets this to its O-switching state return. The signal on line 132 is also used via an OR gate 122 to reset flip-flop 92 to its O-switching state used. This latter function should usually not necessary, but eat as a precautionary measure introduced. Are both flip-flops 92 and 96 in its O-switching state, none of the AND «elements can or 128 when a clock pulse occurs on the line. 192 are switched through and the count in counter 50 is not changed during a frame return. This prevents the display from being shifted or with others Words the display remains unchanged until new input data is received.

Are new data received, regardless of whether the buffer part of the memory is empty or one or more characters are left contains, the count of the input address counter 48 is increased in a suitable manner. It should be noted that

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because those stored in character locations 4 to 9 of the memory Characters are no longer used for displaying this Characters can now be overwritten. It is assumed that there are four or fewer characters in the buffer part, when new input data is received. Under these conditions, new data is received at the end of a frame were ', the buffer count to a count Decreased between 1 and 4 before matching will. The detector 84 responds and generates a Output on line 110. Since flip-flop 92 is reset and generates an output on line 114-, the AND gate 112 is fully turned on and this generates an output signal from the OR gate 118 to Set the flip-flop 96 in its 1-switching state on this is given. The circuit therefore begins a shift by 1 again or sets a shift in the previous one described way at 1. More characters are received while the one responsible for shifting by 1 Flip-flop is set so that the total number of characters in the buffer portion of the memory is 5 or more, this becomes for one Shift of 2 competent flip-flops 92 lawb and the speed with which the characters shifted across the screen will be increased.

In this way an arrangement has been created which enables characters to be shifted across the display screen of a cathode ray tube or similar display device in relatively small steps, so that the impression of a very smooth flow of data across the screen is obtained. The arrangement is also in a position, the speed at which the character _s be moved across the screen depending on the speed, arrived with the new data / e j? To change.

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Although in the preferred embodiment of the invention a cathode ray tube was specified as a display device, the teaching according to the invention can of course be combined can be used with any display device that is scanned cyclically. In the same way is the special The type of memory used is not critical, as long as it only carries out the necessary punctures able. The way in which the information is stored and read from the memory 24 can also be changed. So For example, the information arriving on the ticker line 34 may first be given to a processing unit which subjects the information to various processing steps before it is stored in the saliva 24. At this Operation, the detectors 36 and 51 are dispensable and the Signals generated by the detectors are then immediate derived from the processing unit.

It should also be noted that in the preferred embodiment of the invention, the shifting of the scanning jumps is effected by delaying the display, whereby it is required, a synchronization change between the display grid and the control clock for reading out the memory to undertake. The shift can therefore also be caused by a delay or other changes in the clock signal used for reading out the memory can be achieved. In the same way can the special procedure for determining the number of characters waiting to be displayed in the buffer section and the buffer counter readings, in which a change in the shift amount occurs can also be changed, but the basic one Invention idea is not left. The number of strokes that one shift during each retrace zyklusce3 occurs, can also be increased to 3 or more when in some applications information is faster

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be received. Although the line 18 is shown as being connected to only a single display device 10, it is also possible that this line is connected in this way *; that the same advertisement appears on several display devices at the same time. With a suitable control of the reading out of the memory and with multiplexing its outputs signals, the information of the memory 24 can also be displayed on various display parts, as in Pig. 2, for example on different parts of the display device shown.

Although the invention in connection with a preferred embodiment As shown and described, those skilled in the art can readily recognize that the foregoing and others Changes in functionality and details made can be without thereby affecting the inventive idea is left »

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Claims (1)

Claims / Iy Method for generating a running display on a cyclically scanned display device, characterized in that a first predetermined number of characters to be displayed and a second predetermined one Number of characters waiting to be displayed in an addressable Memory (24) are stored so that the start address for the first number of characters is specified in the memory, that at a certain time each display cycle determines the number of buffered characters waiting to be displayed that the start address specified for the first number of characters depends on the size of the previously determined Number is paid further, and that the first number of characters in a predetermined sequence starting with the specified Start address is read from the memory in order to control the display of the display device (10). 2. The method according to claim 1, characterized eichn e t that the address at which a new to be stored Characters to be stored is specified and the number of traversing required to determine the characters stored The steps for comparing those for saving new Characters specified addresses with the address for the start of the first number of characters and the address for specifying the number of the characters stored and waiting to be displayed in Depending on the difference between the addresses, include procedural steps required. 309811/0632 3. Method of generating a smoothly running display on a cyclically scanned ^ display device * with the ^ ede of the character to be displayed by changing the is displayed with the eye perceivable state of selected index points of several columns of a character matrix, thereby gek-ennzeich.net that a minimum of N + 1 characters representing coded information is stored, where N is the number of characters to be displayed on the display device is that the stored ones representing at least N characters Information for controlling the display of corresponding characters on the display device is used from the start of the display ab during each successive scan of the display device a number of columns smaller than the total number of columns is omitted that the number of columns is added to the characters at the end of the display and that the remaining characters of the display in the direction of the The start of the display can be shifted by the number of columns. 4. The method according to claim 3 »characterized in that that in the control steps for the display, the characters of the stored information are synchronized with the display of the characters are read out on the display device (10) and that the steps of omitting, adding and of shifting includes the step of switching synchronization between character reading out and character displaying by the acid formation of the number of columns on the display device necessary time to read. 5. circuit arrangement for generating a running display, in particular for carrying out the method according to claim 1 or 2, geken nzeich by a cyclic scannable display device (10), through an addressable 30 0 8 1 1/0632 Memory (24-) which has addressable locations for storing a first predetermined number of characters to be displayed and further addressable locations for storing a second predetermined number of buffered characters waiting to be displayed, by means (50) for specifying the start address the first number of characters, by means (62) for determining the number of characters buffered and waiting to be displayed, which operates at a predetermined time in each display cycle of the display means, and for further counting the address indicated by the indicating means (50) , to a quantity dependent on the previously determined number, and by © ine 3j © s @ device (54) to read out the first number of ZeicUm. from memory in a predetermined sequence starting irdi; the voa of the device specified address in order to control the number 5 display device. 6. Circuit arrangement naeJh Αώ spoke 5a dadmrch that © iae further device (4-8) is provided for Aagabe the address at which new buffered characters can be stored, and that the device (62) for determining the number of buffered characters has at least one of the information devices (50 _s 48) for the determination using device (64). 7. Circuit arrangement according to claim 6, characterized in that g e k θ η η, that the means (62) for determining the buffered characters a comparison means (68) for the addresses of the indication devices (50,48) and one on the Difference between the address-responding device (82 to 85) for specifying the number of those waiting for their display has buffered characters. 309011/063? 8. Circuit arrangement according to claim 7 »characterized in that the device (62) for Specification of the number of buffered characters for a mismatch the comparison device (68) responsive device with which the count of the address of the new buffered characters indicating further device (96,98) is further countable, and a device (100, 128) for determining the number by how much the address must be counted further before the comparison device agrees can be determined, this number serving as an indication of the number of buffered characters. 9. Circuit arrangement according to claim 5 »characterized in that the counting of the further Specifying device (48) specified address can be made by two or more specific different sizes and that the specific size with which an address can be counted for a given number of buffered characters the previously occurred determinations on buffered characters is changeable. 10. Circuit arrangement according to claim 5 »thereby g e k e η. η indicates that the display device (10) is a cyclically rewritten cathode ray tube and that each on the display device new characters to be written in the Memory (24 ·) can be stored as one of the first number of characters and can be triggered synchronously with the rewriting of the character is so as to control rewriting. 11. Circuit arrangement according to claim 5 »thereby g e k e η η ζ e i c h ne t that the current display comprises two lines of characters, that each of the lines has the first number of Has character positions, but the characters at corresponding 309811 / Ü632 Character positions can only appear on one of the lines that the memory (24) separately identifiable areas for Storing the characters to be displayed in each of the lines and that the device from the first to (50) "indicated Start address falls into the area of memory in which a character is stored at the corresponding address. 12. Circuit arrangement according to claim 5, characterized in that the display consists of characters that can be generated by changing the state of selected points of several columns of a character matrix, which can be perceived by the eye, with the information provided by the indicating device (50) specified address is a column address, and that a device responsive to the column address in the specification one. direction is provided, with d.er the number of columns of the character to be displayed at this address can be controlled. $ 1. Circuit arrangement according to Claim 12, characterized in that the reading device (54) the characters can be read out synchronously with the display of the characters on the display device (10) and. that the number the column controlling device means (14) for. · Change of synchronization between the reading device and the display means by the time required to form a number of columns equal to that The number specified by the column address is « 14. Circuit arrangement according to claim 12, characterized in that. which is the number of columns controlling means comprises means for suppressing a number of columns equal to the number by the column address is different from the start of the display, 309811/0632 that the number of columns match the characters at the end of the display can be added and that the remaining characters of the display can be shifted in the direction of the start of the display. . Circuit arrangement according to Claim 12, characterized in that the Cathode ray tube cyclically a predetermined grid pattern It can be scanned that with the reading device (54) from the memory (24) characters are synchronized with the reaching of individual characters Points of the grid pattern can be read out by the cathode ray on which the characters are to be displayed, and that the device controlling the number of columns is a device (14) to change the time sequence of the grid with which the line return can be delayed by such a time is equal to the write time of the column address specified columns, whereby the synchronization between Speieber and raster can be changed. 16. Circuit arrangement for generating a uniformly running display on a cyclically scanned display device, with which each character to be displayed is selected by changing the state perceptible to the eye several columns of a character matrix can be displayed, in particular for carrying out the method according to claim or 4, characterized by storing coded information representing at least 3? +1 characters Memory (24), where N is the number of characters to be displayed on the display device (10) by one of the at least Stored information representing N characters for controlling the display of the corresponding characters on the display device using device (50) and by an ar- 309811/063? beltende, a number of columns smaller than that Total number of columns, "suppressing at the start of the display and this number of columns the characters at the end of the display adding device (92,96) ·, with which the remaining characters of the display in the direction of the beginning of the display the number of columns can be moved. 17. Circuit arrangement according to claim 16, characterized in that the controlling the display Device (50) a reading device (54) for reading out the Has characters from the stored information synchronously with the display of the characters on the display device (10), and that the means (92,96) for suppressing, adding and shifting a means (14) for switching synchronization between, reading and display device at the time that is required to form the number of columns on the display device. 18. Circuit arrangement according to claim 17 »characterized by g e that the display device (10) eats a cathode ray tube with its cathode ray cyclically a predetermined raster pattern can be scanned, that characters synchronously with the reading device (54) from the memory (24) with the reaching of individual points of the grid pattern by the cathode ray can be read out at which the characters are to be displayed, and that the means (14) for synchronization change a 6 further means for changing the time sequence of the raster, so that the line return can be delayed by a time equal to the writing time of the columns specified by the column address, whereby the synchronization between the memory and the latch is a » is changeable. 309811/0032 19. Circuit arrangement according to claim 16, with the on one Cathode ray tube with a display screen a running ticker display can be carried out, marked by a memory (24) with a first area for ■ Stock market identification information and a second area for price and quantity information, each of these areas Storage locations for storing at least one buffered character in addition to the characters to be displayed has, by a reading device (54) for reading out the information from the first area synchronously with the new Writing the characters indicating the stock market symbols during a first horizontal scan of the screen and to the Reading out the information from the second area synchronously with the renewed writing of the price and volume information indicating characters during a second horizontal deflation of the screen, the means (92,96) operating during successive scanning of the screen being a Number of sample jumps smaller than the selected one Number of sample jumps, from the leftmost Characters of the horizontal scans suppressed, the number of scan jumps the furthest to the right Characters of the scanning process are added and scanning jumps for a new character from the appropriate one of the buffered character positions at the right end of the display, if necessary, and the other characters of the ticker display around the Number of scan jumps shifted to the left. 20. Circuit arrangement according to claim 19 »characterized in that the during successive Scanning of the screen operating means (92,96) means (14) for changing the synchronization between reading out the information from the memory (24) and the 309811 / 0C32 Rewriting the characters on the CRT (10) by the time it takes from the CRT to Generation of the sampling jumps is required 21. Circuit arrangement according to claim 20, characterized in that the rays of the cathode ray tube (10) write a pre-determined haste pattern, and that the device (14) for the synchronization change is the device for changing the time sequence of the cathode ray raster with which the line return can be delayed by the time required to generate the number of scanning jumps is. 2Ü circuit arrangement according to claim 21, characterized in that a device for generating a special horizontal scanning of the screen before the first horizontal scan and a special horizontal scan of the screen after the second horizontal scan, where the first particular scan is the number of scan jumps who buadded after the last signs of the haste are provided, and the second particular sample has the number of sample jumps that are determined by the The first line raster was subtracted, whereby the raster synchronization can be restored. 23 · Circuit arrangement according to claim 19 «characterized in that several buffer storage locations for the characters in each area of the memory (24) are that a device (62) for determining the Ansah! of the characters stored in the memory locations is, and that a responsive to the number of characters stored means (92,96) for controlling the Number of sample jumps to be suppressed, added and shifted during each successive rewrite cycle is provided. 309811/0632 Lee r side